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2023-01-10arm64: dts: qcom: sc7280: Fix CPU nodes compatible stringRob Herring
'arm,kryo' is not documented and is not an Arm Ltd thing either as that is Qualcomm branding. The correct compatible is 'qcom,kryo'. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221207211327.2848665-1-robh@kernel.org
2023-01-10arm64: dts: qcom: sm8450-nagara: Configure SLG51000 PMICKonrad Dybcio
Nagara devices use the Dialog SLG51000 PMIC for powering some camera sensors. Add the required nodes to support it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-7-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8450-nagara: Enable PMIC RESIN+PONKonrad Dybcio
Enable the power and volume up buttons, connected to PON and RESIN respectively. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-6-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8450-nagara: Set up camera regulatorsKonrad Dybcio
Set up gpio-controlled fixed regulators for camera on PDX223 and fix up the existing ones in common and PDX224 trees. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-5-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8450-nagara: Add GPIO keysKonrad Dybcio
With PMIC GPIOs now available, set up required pin settings and add gpio-keys. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-4-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8450-nagara: Add GPIO line names for PMIC GPIOsKonrad Dybcio
Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX223&224 DTSIs to better document the hardware. Diff between 223 and 224: pm8350b < "CAM_PWR_LD_EN", > "NC", pm8350c < "RGBC_IR_PWR_EN", > "NC", Which is due to different camera power wiring on 223 and lack of a ToF sensor on 224. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-3-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8450-nagara: Include PMIC DTSIsKonrad Dybcio
Now that SPMI is finally in place, include the DTSIs of PMICs present on Nagara. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-2-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8450: add spmi nodeVinod Koul
Add the spmi bus as found in the SM8450 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Adjusted unit address] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221229103212.984324-1-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: sm8550: add QCrypto nodesNeil Armstrong
Add the QCE and Crypto BAM DMA nodes. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-qce-v1-0-fe750dfa90f6@linaro.org
2023-01-10arm64: dts: qcom: sm8550: add I2C Master Hub nodesNeil Armstrong
Add the I2C Master Hub wrapper and I2C serial engines nodes. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-gpi-qup-v1-0-86a60cf3e57d@linaro.org
2023-01-10arm64: dts: qcom: Add base SM8550 MTP dtsAbel Vesa
Add dts file for Qualcomm MTP platform which uses SM8550 SoC. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-11-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add PMR735d pmic dtsiNeil Armstrong
Add nodes for PMR735d in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-10-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add PMK8550 pmic dtsiNeil Armstrong
Add nodes for PMK8550 in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-9-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add PM8550vs pmic dtsiNeil Armstrong
Add nodes for PM8550vs in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-8-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add PM8550ve pmic dtsiNeil Armstrong
Add nodes for PM8550ve in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-7-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add PM8550b pmic dtsiNeil Armstrong
Add nodes for PM8550b in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-6-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add PM8550 pmic dtsiNeil Armstrong
Add nodes for PM8550 in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-5-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add pm8010 pmic dtsiNeil Armstrong
Add nodes for pm8010 in separate dtsi file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-4-abel.vesa@linaro.org
2023-01-10arm64: dts: qcom: Add base SM8550 dtsiAbel Vesa
Add base dtsi for SM8550 SoC and includes base description of CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq, interconnect, thermal sensor, cpu cooling maps and SMMU nodes which helps boot to shell with console on boards with this SoC. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106201047.337409-3-abel.vesa@linaro.org
2023-01-10Merge branch '20230104093450.3150578-2-abel.vesa@linaro.org' into arm64-for-6.3Bjorn Andersson
Merge the TCSR clock binding, to gain the Devicetree include file.
2023-01-10dt-bindings: clock: Add SM8550 TCSR CC clocksAbel Vesa
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
2023-01-10Merge branch 'icc-sm8550-immutable' of ↵Bjorn Andersson
https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3 Merge the immutable SM8550 interconnect branch, to gain the include file from the binding.
2023-01-10arm64: dts: qcom: sm8450: Add compat qcom,sm8450-dsi-ctrlDmitry Baryshkov
Add silicon specific compatible qcom,sm8450-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8450 against the yaml documentation. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230110055433.734188-3-dmitry.baryshkov@linaro.org
2023-01-10arm64: dts: qcom: sm8150: Add compat qcom,sm8150-dsi-ctrlDmitry Baryshkov
Add silicon specific compatible qcom,sm8150-dsi-ctrl to the mdss-dsi-ctrl block. This allows us to differentiate the specific bindings for sm8150 against the yaml documentation. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230110055433.734188-2-dmitry.baryshkov@linaro.org
2023-01-10arm64: dts: qcom: msm8992-libra: Fix the memory mapKonrad Dybcio
The memory map was wrong. Fix it to prevent the device from randomly rebooting. Fixes: 0f5cdb31e850 ("arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221219131918.446587-2-konrad.dybcio@linaro.org
2023-01-10arm64: dts: qcom: msm8992: Don't use sfpb mutexKonrad Dybcio
MSM8992 uses the same mutex hardware as MSM8994. This was wrong from the start, but never presented as an issue until the sfpb compatible was given different driver data. Fixes: 6a6d1978f9c0 ("arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support") Reported-by: Eugene Lepshy <fekz115@gmail.com> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221219131918.446587-1-konrad.dybcio@linaro.org
2023-01-10arm64: dts: msm8994-angler: fix the memory mapDominik Kobinski
Add reserved regions for memory hole and tz app mem to prevent rebooting. Also enable cont_splash_mem, it is the same as the generic 8994 one. Reported-by: Petr Vorel <petr.vorel@gmail.com> Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com> Reviewed-by: Petr Vorel <petr.vorel@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221230194845.57780-1-dominikkobinski314@gmail.com
2023-01-10arm64: dts: qcom: sdm845: do not customize SPI0 pin drive/biasKrzysztof Kozlowski
Each board should define pin drive/bias for used busses. All boards using SPI0 (db845c and cheza) already do it, so drop the bias/drive strength from SoC DTSI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222151319.122398-4-krzysztof.kozlowski@linaro.org
2023-01-10arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schemaKrzysztof Kozlowski
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222151319.122398-3-krzysztof.kozlowski@linaro.org
2023-01-10arm64: dts: qcom: sdm845-xiaomi-beryllium: fix audio codec interrupt pin nameKrzysztof Kozlowski
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: dd6459a0890a ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222151319.122398-2-krzysztof.kozlowski@linaro.org
2023-01-10arm64: dts: qcom: sdm845-db845c: fix audio codec interrupt pin nameKrzysztof Kozlowski
The pin config entry should have a string, not number, for the GPIO used as WCD9340 audio codec interrupt. Fixes: 89a32a4e769c ("arm64: dts: qcom: db845c: add analog audio support") Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222151319.122398-1-krzysztof.kozlowski@linaro.org
2023-01-10arm64: dts: qcom: msm8998-fxtec: fix touchscreen reset GPIO polarityQuentin Schulz
The reset line is active low for the Goodix touchscreen controller so let's fix the polarity in the Device Tree node. Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221103-upstream-goodix-reset-v3-8-0975809eb183@theobroma-systems.com
2023-01-05interconnect: qcom: Add QDU1000/QRU1000 interconnect driverMelody Olvera
Add interconnect provider driver for Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Link: https://lore.kernel.org/r/20221216230914.21771-3-quic_molvera@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-05dt-bindings: interconnect: Add QDU1000/QRU1000 devicesMelody Olvera
Add separate schema for QDU1000 and QRU1000 interconnect devices to document the different NoCs on these platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221216230914.21771-2-quic_molvera@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-02arm64: dts: qcom: sm8450: align PSCI domain names with DT schemaKrzysztof Kozlowski
Bindings expect power domains to follow generic naming pattern: sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-6-krzysztof.kozlowski@linaro.org
2023-01-02arm64: dts: qcom: sm8350: align PSCI domain names with DT schemaKrzysztof Kozlowski
Bindings expect power domains to follow generic naming pattern: sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-5-krzysztof.kozlowski@linaro.org
2023-01-02arm64: dts: qcom: sm8250: align PSCI domain names with DT schemaKrzysztof Kozlowski
Bindings expect power domains to follow generic naming pattern: sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-4-krzysztof.kozlowski@linaro.org
2023-01-02arm64: dts: qcom: sm8150: align PSCI domain names with DT schemaKrzysztof Kozlowski
Bindings expect power domains to follow generic naming pattern: sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-3-krzysztof.kozlowski@linaro.org
2023-01-02arm64: dts: qcom: sm6375: align PSCI domain names with DT schemaKrzysztof Kozlowski
Bindings expect power domains to follow generic naming pattern: sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-2-krzysztof.kozlowski@linaro.org
2023-01-02arm64: dts: qcom: sc8280xp: align PSCI domain names with DT schemaKrzysztof Kozlowski
Bindings expect power domains to follow generic naming pattern: sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6', 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085452.10753-1-krzysztof.kozlowski@linaro.org
2023-01-02arm64: dts: qcom: sm8450: disable by default Soundwire and VA-macroKrzysztof Kozlowski
Soundwire is a bus and VA-macro requires a supply, thus both are expected to be explicitly enabled and populated by board DTS. The HDK8450 already enables Soundwire devices, except swr4 which as a result of this commit will stay disabled. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102123734.478433-1-krzysztof.kozlowski@linaro.org
2022-12-29arm64: dts: qcom: use generic node name for CS35L41 speakerKrzysztof Kozlowski
Node names should be generic so use consistently speaker-amp for CS35L41 speaker amplifier. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221224154255.43499-5-krzysztof.kozlowski@linaro.org
2022-12-29arm64: dts: qcom: sm8450: re-order GCC clocksKrzysztof Kozlowski
Bindings expect GCC clocks in other order: sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221224154255.43499-4-krzysztof.kozlowski@linaro.org
2022-12-29arm64: dts: qcom: sm8250: drop unused clock-frequency from va-macroKrzysztof Kozlowski
Neither qcom,sm8250-lpass-va-macro bindings nor the driver use "clock-frequency" property. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221224154255.43499-3-krzysztof.kozlowski@linaro.org
2022-12-29arm64: dts: qcom: msm8996: align bus node names with DT schemaKrzysztof Kozlowski
The node names should be generic and the bindings expect "bus" for simple-bus nodes: msm8996-mtp.dtb: agnoc@0: $nodename:0: 'agnoc@0' does not match '^bus(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221224154255.43499-1-krzysztof.kozlowski@linaro.org
2022-12-29arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEsMarijn Suijten
Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware connected to them, leaving the rest disabled to save on power. For this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to be connected to Serial Engines on GPU DMA 1 / QUP 1. Beyond this downstream only defines a UART console available on Serial Engine 4 which also resides on QUP 0. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Martin Botka <martin.botka@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221216233408.1283581-4-marijn.suijten@somainline.org
2022-12-29arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial EnginesMarijn Suijten
Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines. QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap in the middle (ranging from 5-9 with SPI 7 missing). Both QUPs have 5 I2C Serial Engines. [Marijn: Add iommus, reword patch description, reorder all properties, sort based on address, use QCOM_GPI_ constants, drop dma cells from 5 to 3] Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Martin Botka <martin.botka@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221216233408.1283581-3-marijn.suijten@somainline.org
2022-12-29arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial EnginesMartin Botka
Add pin setup for SPI/I2C Serial Engines that are supported under the Qualcomm Universal Peripheral found on SM6125. [Un-nest pins, remove duplicate pins= properties, follow new node naming conventions, fix qup_14 -> qup14 function typo] Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221216233408.1283581-2-marijn.suijten@somainline.org
2022-12-29arm64: dts: qcom: sm6125-seine: Clean up gpio-keys (volume down)Marijn Suijten
- Remove autorepeat (leave key repetition to userspace); - Remove unneeded status = "okay" (this is the default); - Remove unneeded linux,input-type <EV_KEY> (this is the default for gpio-keys); - Allow the interrupt line for this button to be disabled; - Use a full, descriptive node name; - Set proper bias on the GPIO via pinctrl; - Sort properties; - Replace deprecated gpio-key,wakeup property with wakeup-source. Fixes: 82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222192443.119103-1-marijn.suijten@somainline.org
2022-12-29arm64: dts: qcom: sm6125: Add GPI DMA nodesMartin Botka
Add nodes for GPI DMA hosts on SM6125. [Marijn: reorder properties, use sdm845 fallback compatible, disable by default, use 3 instead of 5 dma cells] Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222194600.139854-3-marijn.suijten@somainline.org
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