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2025-04-24media: imx-jpeg: Move mxc_jpeg_free_slot_data() aheadMing Qian
Move function mxc_jpeg_free_slot_data() above mxc_jpeg_alloc_slot_data() allowing to call that function during allocation failures. No functional changes are made. Fixes: 2db16c6ed72c ("media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder") Cc: stable@vger.kernel.org Signed-off-by: Ming Qian <ming.qian@oss.nxp.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-24media: imagination: fix a potential memory leak in e5010_probe()Haoxiang Li
Add video_device_release() to release the memory allocated by video_device_alloc() if something goes wrong. Fixes: a1e294045885 ("media: imagination: Add E5010 JPEG Encoder driver") Cc: stable@vger.kernel.org Signed-off-by: Haoxiang Li <haoxiang_li2024@163.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-24media: amphion: Slightly simplify vpu_core_register()Christophe JAILLET
"vpu_core->msg_buffer_size" is unused out-side of vpu_core_register(). There is no need to save this value in struct vpu_core. Remove it and use a local variable instead. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-24media: verisilicon: Enable NV15 support for Rockchip VDPU981Nicolas Dufresne
This is a "customer" format, though on Rockchip RK3588 it has been verified to be NV15 format, which matches what the GPU and display handles has 10bit pixel formats. Reviewed-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-24media: imx-jpeg: Drop the first error framesMing Qian
When an output buffer contains error frame header, v4l2_jpeg_parse_header() will return error, then driver will mark this buffer and a capture buffer done with error flag in device_run(). But if the error occurs in the first frames, before setup the capture queue, there is no chance to schedule device_run(), and there may be no capture to mark error. So we need to drop this buffer with error flag, and make the decoding can continue. Fixes: 2db16c6ed72c ("media: imx-jpeg: Add V4L2 driver for i.MX8 JPEG Encoder/Decoder") Cc: stable@vger.kernel.org Signed-off-by: Ming Qian <ming.qian@oss.nxp.com> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-24media: mediatek: vcodec: Enable HEVC main still picture decodeNathan Hebert
Mediatek devices that support HEVC also support the main still picture profile, but today, the main still picture profile is excluded. This removes the skip mask for HEVC, and enables the main still picture profile decoding. Signed-off-by: Nathan Hebert <nhebert@chromium.org> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Add support for RZ/G3E SoCLad Prabhakar
The CRU block on the Renesas RZ/G3E SoC is similar to the one found on the Renesas RZ/G2L SoC, with the following differences: - Additional registers rzg3e_cru_regs. - A different irq handler rzg3e_cru_irq. - A different rzg3e_cru_csi2_setup. - A different max input width. - Additional stride register. Introduce rzg3e_cru_info struct to handle differences between RZ/G2L and RZ/G3E and related RZ/G3E functions: - rzg3e_cru_enable_interrupts() - rzg3e_cru_enable_interrupts() - rz3e_fifo_empty() - rzg3e_cru_csi2_setup() - rzg3e_cru_get_current_slot() Add then support for the RZ/G3E SoC CRU block with the new compatible string "renesas,r9a09g047-cru". Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-18-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Add function pointer to configure CSILad Prabhakar
Add a `csi_setup` function pointer to the `rzg2l_cru_info` structure and pass it as part of the OF data. On RZ/G3E and RZ/V2H(P) SoCs, additional register configurations are required compared to the RZ/G2L SoC. Modify `rzg2l_cru_csi2_setup()` to be referenced through this function pointer and update the code to use it accordingly. This change is in preparation for adding support for RZ/G3E and RZ/V2H(P) SoCs. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-17-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Add function pointer to check if FIFO is emptyLad Prabhakar
Add a `fifo_empty` function pointer to the `rzg2l_cru_info` structure and pass it as part of the OF data. On RZ/G3E and RZ/V2H(P) SoCs, checking if the FIFO is empty requires a different register configuration. Implement `rzg2l_fifo_empty()` and update the code to use it from the function pointer. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-16-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Add IRQ handler to OF dataLad Prabhakar
Add `irq_handler` to the `rzg2l_cru_info` structure and pass it as part of the OF data. This prepares for supporting RZ/G3E and RZ/V2H(P) SoCs, which require a different IRQ handler. Update the IRQ request code to use the handler from the OF data. Add `enable_interrupts` and `disable_interrupts` function pointers to the `rzg2l_cru_info` structure and pass them as part of the OF data. This prepares for supporting RZ/G3E and RZ/V2H(P) SoCs, which require different interrupt configurations. Implement `rzg2l_cru_enable_interrupts()` and `rzg2l_cru_disable_interrupts()` functions and update the code to use them instead of directly writing to interrupt registers. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-15-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Add image_conv offset to OF dataLad Prabhakar
Add `image_conv` field to the `rzg2l_cru_info` structure to store the register offset for image conversion control. RZ/G2L uses `ICnMC`, while RZ/G3E and RZ/V2H(P) use `ICnIPMC_C0`. Update `rzg2l_cru_initialize_image_conv()` and `rzg2l_cru_csi2_setup()` to use this `image_conv` offset from the OF data, facilitating future support for RZ/G3E and RZ/V2H(P) SoCs. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-14-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Pass resolution limits via OF dataLad Prabhakar
Pass `max_width` and `max_height` as part of the OF data to facilitate the addition of support for RZ/G3E and RZ/V2H(P) SoCs. These SoCs have a maximum resolution of 4096x4096 as compared to 2800x4095 on RZ/G2L SoC. This change prepares the driver for easier integration of these SoCs by defining the resolution limits in the `rzg2l_cru_info` structure. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-13-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: Add register mapping supportLad Prabhakar
Prepare for adding support for RZ/G3E and RZ/V2HP SoCs, which have a CRU-IP that is mostly identical to RZ/G2L but with different register offsets and additional registers. Introduce a flexible register mapping mechanism to handle these variations. Define the `rzg2l_cru_info` structure to store register mappings and pass it as part of the OF match data. Update the read/write functions to check out-of-bound accesses and use indexed register offsets from `rzg2l_cru_info`, ensuring compatibility across different SoC variants. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-12-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: csi2: Add support for RZ/V2H(P) SoCLad Prabhakar
The D-PHY on the RZ/V2H(P) SoC is different from the D-PHY on the RZ/G2L SoC. To handle this difference, function pointers for D-PHY enable/disable have been added, and the `struct rzg2l_csi2_info` pointer is passed as OF data. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-11-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoCTommaso Merciai
The RZ/V2H(P) SoC does not require a `system` clock for the CSI-2 interface. To accommodate this, introduce a `has_system_clk` bool flag in the `rzg2l_csi2_info` structure and update the rzg2l_csi2_probe() to conditionally request the clock only when needed. This patch is in preparation for adding support for RZ/V2H(P) SoC. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-10-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: csi2: Introduce SoC-specific D-PHY handlingLad Prabhakar
In preparation for adding support for the RZ/V2H(P) SoC, where the D-PHY differs from the existing RZ/G2L implementation, introduce a new rzg2l_csi2_info structure. This structure provides function pointers for SoC-specific D-PHY enable and disable operations. Modify rzg2l_csi2_dphy_setting() to use these function pointers instead of calling rzg2l_csi2_dphy_enable() and rzg2l_csi2_dphy_disable() directly. Update the device match table to store the appropriate function pointers for each compatible SoC. This change prepares the driver for future extensions without affecting the current functionality for RZ/G2L. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-9-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: rzg2l-core: Use devm_pm_runtime_enable()Tommaso Merciai
Use newly added devm_pm_runtime_enable() into rzg2l_cru_probe() and drop unnecessary pm_runtime_disable() from rzg2l_cru_probe() and rzg2l_csi2_remove(). Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-8-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: rzg2l-core: Use local variable for struct device in ↵Lad Prabhakar
rzg2l_cru_probe() Use a local variable for the struct device pointers. This increases code readability with shortened lines. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-7-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: csi2: Use devm_pm_runtime_enable()Tommaso Merciai
Use newly added devm_pm_runtime_enable() into rzg2l_csi2_probe() and drop error path accordingly. Drop also unnecessary pm_runtime_disable() from rzg2l_csi2_remove(). Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-6-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rzg2l-cru: csi2: Use local variable for struct device in ↵Lad Prabhakar
rzg2l_csi2_probe() Use a local variable for the struct device pointers. This increases code readability with shortened lines. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-5-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G3E SoCTommaso Merciai
The CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC has five interrupts: - image_conv: image_conv irq - axi_mst_err: AXI master error level irq - vd_addr_wend: Video data AXI master addr 0 write end irq - sd_addr_wend: Statistics data AXI master addr 0 write end irq - vsd_addr_wend: Video statistics data AXI master addr 0 write end irq This IP has only one input port 'port@1' similar to the RZ/G2UL CRU. Document the CRU block found on the Renesas RZ/G3E ("R9A09G047") SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-4-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G3E CSI-2 blockTommaso Merciai
Document the CSI-2 block which is part of CRU found in Renesas RZ/G3E SoC. The CSI-2 block on the RZ/G3E SoC is identical to one found on the RZ/V2H(P) SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-3-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/V2H(P) SoCLad Prabhakar
The MIPI CSI-2 block on the Renesas RZ/V2H(P) SoC is similar to the one found on the Renesas RZ/G2L SoC, with the following differences: - A different D-PHY - Additional registers for the MIPI CSI-2 link - Only two clocks Add a new compatible string, `renesas,r9a09g057-csi2`, for the RZ/V2H(P) SoC. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Link: https://lore.kernel.org/r/20250411170624.472257-2-tommaso.merciai.xr@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: rcar-vin: Fix stride setting for RAW8 formatsNiklas Söderlund
Earlier versions of the datasheet where unclear about the stride setting for RAW8 capture formats. Later datasheets clarifies that the stride only process in this mode for non-image data. For image data the full stride shall be used. Compare section "RAW: 8 Bits and Embedded 8-Bit Non-Image Data, User Defined 8-bit Data" vs "RAW: 8 Bits". Remove the special case from pixel formats that carry image data and treat it as any other image format. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20250402183302.140055-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: media: renesas,fcp: Document RZ/V2H(P) SoCLad Prabhakar
The FCPVD block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,fcpv` will be used as a fallback compatible string on the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20250408193158.80936-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-23media: dt-bindings: media: renesas,vsp1: Document RZ/V2H(P)Lad Prabhakar
The VSPD block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,r9a07g044-vsp2` will be used as a fallback compatible string on the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20250408193158.80936-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: venus: pm_helpers: add compatibility for dev_pm_genpd_set_hwmode on V4Renjiang Han
There are two ways to switch GDSC mode. One is to write the POWER_CONTROL register and the other is to use dev_pm_genpd_set_hwmode(). However, they rely on different clock driver flags. dev_pm_genpd_set_hwmode() depends on the HW_CTRL_TRIGGER flag and POWER_CONTROL register depends on the HW_CTRL flag. By default, the dev_pm_genpd_set_hwmode() is used to switch the GDSC mode. If it fails and dev_pm_genpd_set_hwmode() returns -EOPNOTSUPP, it means that the clock driver uses the HW_CTRL flag. At this time, the GDSC mode is switched to write the POWER_CONTROL register. Clock driver is using HW_CTRL_TRIGGER flag with V6. So hwmode_dev is always true on using V6 platform. Conversely, if hwmode_dev is false, this platform must be not using V6. Therefore, replace IS_V6 in poweroff_coreid with hwmode_dev. Also, with HW_CTRL_TRIGGER flag, the vcodec gdsc gets enabled in SW mode by default. Therefore, before disabling the GDSC, GDSC should be switched to SW mode so that GDSC gets enabled in SW mode in the next enable. Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Vikash Garodia <quic_vgarodia@quicinc.com> [bod: added media prefix] Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: venus: vdec: queue dpb buffers to firmware for video seekRenjiang Han
For the seek case, the input port will be called stream_off and then stream_on in the driver. Firmware will flush all buffers during stream_off input port. Therefore, driver needs to queue DPB buffers to firmware during stream_on input port to ensure that decoder can decode normally when it receives enough input and output buffers. Otherwise, decoder will not be able to decode due to lack of DPB buffer even if there are enough input and output buffers. Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com> Reviewed-by: Dikshita Agarwal <quic_dikshita@quicinc.com> [bod: added media prefix] Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: venus: Fix probe error handlingLoic Poulain
Video device registering has been moved earlier in the probe function, but the new order has not been propagated to error handling. This means we can end with unreleased resources on error (e.g dangling video device on missing firmware probe aborting). Fixes: 08b1cf474b7f7 ("media: venus: core, venc, vdec: Fix probe dependency error") Cc: stable@vger.kernel.org Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <quic_dikshita@quicinc.com> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11dt-bindings: media: add support for video hardware on QCS615 platformRenjiang Han
QCS615 uses the same video core as SC7180. Therefore, add qcom,qcs615-venus compatible to qcom,sc7180-venus.yaml to enable video hardware support on QCS615 platform. Make qcom,qcs615-venus fallback to qcom,sc7180-venus to ensure compatibility with existing configurations. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Renjiang Han <quic_renjiang@quicinc.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: iris: fix error code in iris_load_fw_to_memory()Dan Carpenter
Return -ENOMEM if memremap() fails. Don't return success. Fixes: d19b163356b8 ("media: iris: implement video firmware load/unload") Cc: stable@vger.kernel.org Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Dikshita Agarwal <quic_dikshita@quicinc.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11dt-bindings: media: qcom,sm8550-iris: document SA8775p IRIS acceleratorVikash Garodia
Document the IRIS video decoder and encoder accelerator found in the SA8775p platform. SA8775p and SM8550 are irisv3 with same core and bindings, hence SA8775p is made fallback to SM8550. QCS8300 is a downscaled version of irisv3 and have different hardware capabilities. SM8650 is an irisv3 with different (higher) number of reset lines compared to SM8550. QCS8300 is yet to come in future posting, while SM8650 is posted as https://lore.kernel.org/all/20250305-topic-sm8x50-iris-v10-v2-1-bd65a3fc099e@linaro.org/ Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vikash Garodia <quic_vgarodia@quicinc.com> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Add x1e80100 specific supportBryan O'Donoghue
Populate CAMSS with x1e80100 specific hooks. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: csiphy-3ph: Add 4nm CSIPHY 2ph 5Gbps DPHY v2.1.2 init ↵Bryan O'Donoghue
sequence For various SoC skews at 4nm CSIPHY 2.1.2 is used. Add in the init sequence with base control reg offset of 0x1000. This initial version will support X1E80100. Take the silicon verification PHY init parameters as a first/best guess pass. SKEW_CAL is included as received from the qcom silicon init sequence. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Add support for 3ph CSIPHY write settle delayBryan O'Donoghue
Currently we have an s32 value called delay which has been inherited from the CamX code for PHY init. This unused value relates to a post-write delay latching time. In the silicon test-bench which provides the basis for the CamX code the write settle times are specified in nanoseconds. In the upstream kernel we currently take no notice of the delay value and use all zero in any case. Nanosecond granularity timing from the perspective of the kernel is total overkill, however for some PHY init sequences introduction of a settle delay has a use. Add support to the 3ph init sequence for microsecond level delay. A readback of written data would probably accomplish the same thing but, since the PHY init sequences in the wild provide a delay value - we can just add support here for that delay and consume the values given. Generally these delays are probably not necessary but, they do speak to a theoretical delay that silicon test-benches utilise and therefore are worthwhile to replicate if the given PHY init sequence has the data. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Add VFE680 supportBryan O'Donoghue
Add silicon enabling support for VFE680 as found on sm8450, x1e and derivatives thereof. References work from Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> [bod: fix minor checkpatch linelenght splat @ lines 21, 22] Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Add CSID 680 supportBryan O'Donoghue
Add CSI Decoder (CSID) 680 support to CAMSS. This version of CSID has been shipped with SM8450 and x1e chips. References work from Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Use the CSIPHY id property to find clock namesBryan O'Donoghue
Use the CSIPHY id property to find clock names instead of relying on generating the clock names based on the control-loop index. x1e80100 has CSIPHY0, CSIPHY1, CSIPHY2 and CSIPHY4 so simple index naming won't work whereas and 'id' property allows any ordering and any stepping between the CSIPHY names. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Add an id property to struct resourcesBryan O'Donoghue
In various places in CAMSS we assume a linear set of declared devices {csiphy0, csiphy1, csiphy2} which currently works for upstream SoCs but for upcoming SoCs some of the SoC resources will result in a set such as {csiphy0, csiphy2} which will break the naive for() loops we have. Introduce an identity property which resource declarations can populate hence facilitating non-linear resource naming. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: vfe: suppress VFE version log spamJohan Hovold
A recent commit refactored the printing of the VFE hardware version, but (without it being mentioned) also changed the log level from debug to info. This results in several hundred lines of repeated log spam during boot and use, for example, on the Lenovo ThinkPad X13s: qcom-camss ac5a000.camss: VFE:1 HW Version = 1.2.2 qcom-camss ac5a000.camss: VFE:0 HW Version = 1.2.2 qcom-camss ac5a000.camss: VFE:2 HW Version = 1.2.2 qcom-camss ac5a000.camss: VFE:2 HW Version = 1.2.2 qcom-camss ac5a000.camss: VFE:3 HW Version = 1.2.2 qcom-camss ac5a000.camss: VFE:5 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:6 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:4 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:5 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:6 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:7 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:7 HW Version = 1.3.0 qcom-camss ac5a000.camss: VFE:7 HW Version = 1.3.0 ... Suppress the version logging by demoting to debug level again. Fixes: 10693fed125d ("media: qcom: camss: vfe: Move common code into vfe core") Cc: stable@vger.kernel.org Cc: Depeng Shao <quic_depengs@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: csid: suppress CSID log spamJohan Hovold
A recent commit refactored the printing of the CSID hardware version, but (without it being mentioned) also changed the log level from debug to info. This results in repeated log spam during use, for example, on the Lenovo ThinkPad X13s: qcom-camss ac5a000.camss: CSID:0 HW Version = 1.0.0 qcom-camss ac5a000.camss: CSID:0 HW Version = 1.0.0 qcom-camss ac5a000.camss: CSID:0 HW Version = 1.0.0 qcom-camss ac5a000.camss: CSID:0 HW Version = 1.0.0 qcom-camss ac5a000.camss: CSID:0 HW Version = 1.0.0 Suppress the version logging by demoting to debug level again. Fixes: f759b8fd3086 ("media: qcom: camss: csid: Move common code into csid core") Cc: stable@vger.kernel.org Cc: Depeng Shao <quic_depengs@quicinc.com> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: qcom: camss: Restrict endpoint bus-type to D-PHYLuca Weiss
Currently the Qualcomm CAMSS driver only supports D-PHY while the hardware on most SoCs also supports C-PHY. Until this support is added, check for D-PHY to make it somewhat explicit that C-PHY won't work. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Tested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11dt-bindings: media: Add qcom,x1e80100-camssBryan O'Donoghue
Add bindings for qcom,x1e80100-camss in order to support the camera subsystem for x1e80100 as found in various Co-Pilot laptops. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11dt-bindings: media: camss: Restrict bus-type propertyLuca Weiss
The CSIPHY of Qualcomm SoCs support both D-PHY and C-PHY standards for CSI-2, but not any others so restrict the bus-type property describing this to the supported values. The only exception here is MSM8916 which only supports D-PHY. C-PHY was introduced with newer SoCs. Do note, that currently the Linux driver only supports D-PHY. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: MAINTAINERS: Add myself to iris ReviewersBryan O'Donoghue
There's some crossover between venus and iris, I'd like to help out with the reviews for iris to ensure we keep upstream chugging along. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: MAINTAINERS: Amend venus Maintainers and ReviewersBryan O'Donoghue
Stan has stepped back from active venus development as a result I'd like to volunteer my help in keeping venus maintained upstream. Discussing with the qcom team on this we agreed +M for Dikshita +R for me Many thanks to Stan for his hard work over the years from originating this driver upstream to his many years of maintenance of it too. Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Dikshita Agarwal <quic_dikshita@quicinc.com> Acked-by: Stanimir Varbanov <stanimir.k.varbanov@gmail.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: mediatek: vcodec: add description for vsi structYunfei Dong
The vsi (video shared information) struct needs to be synchronized between firmware and host, as a change that is only done in the host version of the struct but isn't synchronized to the firmware. This can lead to decoding issues with H264 bitstreams. Highlight this requirement within the struct descriptions. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: mediatek: vcodec: support extended h264 decodeYunfei Dong
Add a new extended vsi_ext struct besides the existing vsi struct, to enable calculating the end of the address range of the current working buffer for architectures, where simply adding the buffer size to the start of the address range isn't sufficient. Additionally, on extended architectures, the NAL information can be fetched directly from the firmware, which allows skipping the parsing step within the kernel. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: mediatek: vcodec: remove vsi operation in common interfaceYunfei Dong
Extend the VSI (video shared information) struct to allow sending slice parameters to SCP, as the parameters have changed on MT8188 architecture. Remove VSI related information from the common interface to ensure that the interface is usable by architectures with and without the extended parameters. The new VSI extensions will be introduced in later patches. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-04-11media: mediatek: vcodec: Correct vsi_core framebuffer sizeFei Shao
The framebuffer size for decoder instances was being incorrectly set - inst->vsi_core->fb.y.size was assigned twice consecutively. Assign the second picinfo framebuffer size to the C framebuffer instead, which appears to be the intended target based on the surrounding code. Fixes: 2674486aac7d ("media: mediatek: vcodec: support stateless hevc decoder") Cc: stable@vger.kernel.org Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 01:13:09 +0000