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2023-10-09drm/amd/display: Disable virtual linksStylon Wang
[Why] This could work around the issue with DP tunneling producing a NULL pointer dereference. [How] Disable the virtual links. Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Disable SubVP if test pattern is enabledGeorge Shen
[Why] Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled while an MCLK switch is taking place with SubVP, it will cause the MCLK to never complete. This is because SubVP MCLK switch relies a HUBP VLine interrupt, which will never occur when HUBP is constantly in blank. [How] Disable SubVP when test pattern is enabled. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Refactor DPG test pattern logic for ODM casesGeorge Shen
[Why] Current DPG test pattern logic does not account for ODM configuration changes after test pattern has already been programmed. For example, if ODM2:1 is enabled after test pattern is already being output, the second pipe is not programmed to output test pattern, causing half the screen to be black. [How] Move DPG test pattern parameter calculations into separate function. Whenever ODM pipe configuration changes, re-calculate DPG test pattern parameters and program DPG if test pattern is currently enabled. Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Don't set dpms_off for seamless bootDaniel Miess
[Why] eDPs fail to light up with seamless boot enabled [How] When seamless boot is enabled don't configure dpms_off in disable_vbios_mode_if_required. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Refactor HWSS into component folderMounika Adhuri
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by: Martin Leung <martin.leung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Mounika Adhuri <moadhuri@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Revert "drm/amd/display: Add a check for idle power ↵Sung Joon Kim
optimization" Revert commit 434cf7af492f ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: add hub->ctx_distance in setup_vmid_configYifan Zhang
add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Lang Yu <lang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Don't use fsleep for PSR exit waitsNicholas Kazlauskas
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the fsleep with a udelay. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Update cursor limits based on SW cursor fallback limitsAlvin Lee
[Why&How] For determining the cursor size limit, use the same checks that are used for determining SW cursor fallback instead of only using SubVP Reviewed-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Update dml ssb from pmfw clock tableMuhammad Ahmed
[why] Need to use real clock table [How] Update the clock table Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Update stream maskDuncan Ma
[Why] Whenever stream changes because of new pipe arrangements such as ODM. The new stream mask is not reflected in DMCUB. The mismatch in stream mask is blocking ips entry in some scenarios. [How] Whenever stream arrangement changes, update stream mask and notify DMCUB. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Duncan Ma <duncan.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Revert "drm/amd/display: remove duplicated edp relink to ↵Aric Cyr
fastboot" Revert commit 984abb5384b0 ("drm/amd/display: remove duplicated edp relink to fastboot") Because it cause 4k EDP not light up on boot Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Modify Vmin default valueMax Tseng
Fine tune the Vmin clock value Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Max Tseng <max.tseng@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Update pmfw_driver_if new structureCharlene Liu
[why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: VSIF v3 set Max Refresh RateMuhammad Ansari
[WHY] FreeSync spec requires PB8 and PB12 to be set to nominal refresh rate regardless of fixed rate or variable [HOW] Removed the condition that checks and overwrites max refresh rate and set PB8/PB12 to be set to max refresh rate always Reviewed-by: Anthony Koo <anthony.koo@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Muhammad Ansari <muhammad.ansari@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Modify SMU message logsSung Joon Kim
[why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: Fix potential null pointer derefernceStanley.Yang
The amdgpu_ras_get_context may return NULL if device not support ras feature, so add check before using. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: enable S/G display for for recent APUs by defaultYifan Zhang
With S/G display becomes stable, enable S/G display for recent APUs by default rather than white list. v2: explicitly disable sg on pre-CZ chips (Alex) v3: add parens for every clause (Alex) Co-authored-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09Documentation/amdgpu: Add FRU attribute detailsLijo Lazar
Add documentation for the newly added manufacturer and fru_id attributes in sysfs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: Add more FRU field informationLijo Lazar
Add support to read Manufacturer Name and FRU File Id fields. Also add sysfs device attributes for external usage. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: Refactor FRU product informationLijo Lazar
Keep FRU related information together in a separate structure. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: enable FRU device for SMU v13.0.6Yang Wang
v1: enable GFX v9.4.3 FRU device to query board information. v2: use MP1 version to identify different asic Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: update ib start and size alignmentBoyuan Zhang
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: add check in validate_only in dml2Gabe Teeger
[what] does_configuration_meet_sw_policies check was not done in the validate_only portion of dml2, so some unsupported modes were passing bw validation, only to fail the same check later in validate_and_build. now we add the check to validate_only. Also add line in dcn35_resource to ensure that value set for enable_windowed_mpo_odm gets passed to dml. [why] Immediate black screen during video playback at 4k144hz. The debugger showed that we were failing validation in dml on every updateplanes(). Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Port replay vblank logic to DML2Daniel Miess
Update DML2 with replay vblank logic found in DML1. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Daniel Miess <daniel.miess@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Modify Pipe Selection for Policy for ODMSaaem Rizvi
[Why] There are certain cases during a transition to ODM that might cause corruption on the display. This occurs when we choose certain pipes in a particular state. [How] We now will store the pipe indexes of the any pipes that might be problematic to switch to during an ODM transition, and only use them as a last resort. Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Saaem Rizvi <syedsaaem.rizvi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: correct dml2 input and dlg_refclkCharlene Liu
dc->dml2_options.use_native_pstate_optimization flag will make driver use dcn32 legacy_svp_drr related tuning. Set this to false fixed the stutter underflow issue also based on HW suggest disable ODM by default and let DML choose it. Reviewed-by: Zhan Liu <zhan.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Fix Chroma Surface height/width initializationSung Joon Kim
[why] Surface height/width for Chroma has another variable that it should be intialized to, chroma_size. Fixing this will help pass DML2.0 validation for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012. [how] Assign SurfaceHeight/WidthC to chroma_size.height/width Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move stereo timing check to helperTaimur Hassan
Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Split pipe for stereo timingsTaimur Hassan
[Why & How] DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe splitting is needed in this case to pass stereo tests. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Use fixed DET Buffer SizeSung Joon Kim
[why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Handle multiple streams sourcing same surfaceSung Joon Kim
[why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Add z8_marks in dmlCharlene Liu
Add z8 watermarks to struct for later ASIC use. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Add DCN35 DML2 supportQingqing Zhuo
Enable DML2 for DCN35. Changes since V1: - Remove hard coded values Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Introduce DML2Qingqing Zhuo
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Co-developed-by: Roman Li <roman.li@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move dml code under CONFIG_DRM_AMD_DC_FP guardRodrigo Siqueira
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move bw_fixed from DML folderRodrigo Siqueira
bw_fixed does not need any FPU operation, and it is used on DCE and DCN. For this reason, this commit moves bw_fixed to the basic folder outside DML. Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move custom_float from DML folderRodrigo Siqueira
The custom_float file does not have any FPU operation, so it should be inside DML. This commit moves the file to the basic folder. Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move dce_calcs from DML folderRodrigo Siqueira
dce_calcs does not have FPU operations, and it is required for DCE and DCN. Remove this file from the DML folder and add it to the basic folder visible for DCE and DCN. Reviewed-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amdgpu: Enable SMU 13.0.0 optimizations when ROCm is active (v2)Alex Deucher
When ROCm is active enable additional SMU 13.0.0 optimizations. This reuses the unused powersave profile on PMFW. v2: move to the swsmu code since we need both bits active in the workload mask. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move the memory allocation out of ↵Sebastian Andrzej Siewior
dcn20_validate_bandwidth_fp(). dcn20_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. To preserve previous "clean" state of "pipes" add a memset() before the second invocation of dcn20_validate_bandwidth_internal() where the variable is used. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Move the memory allocation out of ↵Sebastian Andrzej Siewior
dcn21_validate_bandwidth_fp(). dcn21_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928 Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd/display: Add a warning if the FPU is used outside from task context.Sebastian Andrzej Siewior
Add a warning if the FPU is used from any context other than task context. This is only precaution since the code is not able to be used from softirq while the API allows it on x86 for instance. Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd: Fix UBSAN array-index-out-of-bounds for Polaris and TongaMario Limonciello
For pptable structs that use flexible array sizes, use flexible arrays. Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/radeon: Fix UBSAN array-index-out-of-bounds for Radeon HD 5430Mario Limonciello
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by: Felix Held <felix.held@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/amd: Fix UBSAN array-index-out-of-bounds for SMU7Mario Limonciello
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by: Felix Held <felix.held@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-10-09drm/rockchip: dsi: Use devm_platform_get_and_ioremap_resource()Yang Li
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230421081303.122452-1-yang.lee@linux.alibaba.com
2023-10-09drm/rockchip: remove redundant of_match_ptrZhu Wang
The driver depends on CONFIG_OF, so it is not necessary to use of_match_ptr here. Even for drivers that do not depend on CONFIG_OF, it's almost always better to leave out the of_match_ptr(), since the only thing it can possibly do is to save a few bytes of .text if a driver can be used both with and without it. Hence we remove of_match_ptr. Signed-off-by: Zhu Wang <wangzhu9@huawei.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20230731125304.87059-1-wangzhu9@huawei.com
2023-10-09drm/rockchip: cdn-dp: Fix some error handling paths in cdn_dp_probe()Christophe JAILLET
cdn_dp_audio_codec_init() can fail. So add some error handling. If component_add() fails, the previous cdn_dp_audio_codec_init() call should be undone, as already done in the remove function. Fixes: 88582f564692 ("drm/rockchip: cdn-dp: Don't unregister audio dev when unbinding") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/8494a41602fadb7439630921a9779640698f2f9f.1693676045.git.christophe.jaillet@wanadoo.fr
2023-10-09drm/rockchip: vop2: Convert to use maple tree register cacheMark Brown
The maple tree register cache is based on a much more modern data structure than the rbtree cache and makes optimisation choices which are probably more appropriate for modern systems than those made by the rbtree cache. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20231001-drm-rockchip-maple-v1-1-ca396ab75be7@kernel.org
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-01 22:29:45 +0000