summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2023-08-12Merge tag 'renesas-dts-for-v6.6-tag1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.6 - Add Clocked Serial Interface (CSI) support for the RZ/V2M SoC, - Add PMIC, RTC, and PWM support for the RZ/G2L, RZ/G2LC, and RZ/V2L SMARC EVK development boards, - Add PWM (MTU3a) support for the RZ/G2UL and RZ/Five SoCs, - Add External interrupt (INTC-EX) support for the R-Car S4-8 SoC, - Add LED support for the Spider development board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: spider-cpu: Add GP LEDs arm64: dts: renesas: r8a779f0: Add INTC-EX node arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3 arm64: dts: renesas: r9a07g043: Add MTU3a node ARM dts: renesas: armadillo800eva: Switch to enable-gpios arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTC arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3 arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3 arm64: dts: renesas: Add missing space before { ARM: dts: renesas: Add missing space before { arm64: dts: renesas: Minor whitespace cleanup around '=' arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTC arm64: dts: renesas: r9a09g011: Add CSI nodes arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typos arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channels Link: https://lore.kernel.org/r/cover.1690545144.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-12Merge tag 'tegra-for-6.6-arm64-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.6-rc1 The majority of this is fixes all over the place for DT schema validation warnings. However, there are also cleanups for some things in DT and audio support is added on IGX Orin. Jetson Orin NX and Nano also gain a new thermal trip point to help keep the device cool at moderate loads. * tag 'tegra-for-6.6-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (22 commits) arm64: tegra: Add blank lines for better readability arm64: tegra: Remove {clock,reset}-names from VIC powergate arm64: tegra: Drop incorrect maxim,disable-etr on Smaug arm64: tegra: Add SPI device tree nodes for Tegra234 arm64: tegra: Enable UARTA and UARTE for Orin Nano arm64: tegra: Add UARTE device tree node on Tegra234 arm64: tegra: Adapt to LP855X bindings changes arm64: tegra: Add PCIe and DP 3.3V supplies arm64: tegra: Add missing reset-names for Tegra HS UART arm64: tegra: Remove current-speed for SBSA UART arm64: tegra: smaug: Remove reg-shift for high-speed UART arm64: tegra: Remove dmas and dma-names for debug UART arm64: tegra: Add 35°C trip point for Jetson Orin NX/Nano arm64: tegra: Remove duplicate PCI nodes arm64: tegra: Sort PCI nodes correctly on Orin arm64: tegra: Add audio support for IGX Orin arm64: tegra: Update CPU OPP tables arm64: tegra: Fix HSUART for Smaug arm64: tegra: Fix HSUART for Jetson AGX Orin arm64: tegra: Add missing alias for NVIDIA IGX Orin ... Link: https://lore.kernel.org/r/20230728094129.3587109-4-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-12Merge tag 'tegra-for-6.6-arm-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt ARM: tegra: Device tree changes for v6.6-rc1 This contains various fixes for DT schema validation and the Pegatron Chagall and Nexus 7 get specific compatible strings for the panels that they use. * tag 'tegra-for-6.6-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Provide specific compatible string for Nexus 7 panel ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron Chagall ARM: tegra: Reuse I2C3 for NVEC ARM: tegra: Add missing reset-names for Tegra HS UART ARM: tegra: Remove reset-names for UART devices ARM: tegra: Remove dmas and dma-names for debug UART Link: https://lore.kernel.org/r/20230728094129.3587109-3-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-12Merge tag 'tegra-for-6.6-dt-bindings' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Changes for v6.6-rc1 A number of Tegra-specific bindings are converted to json-schema and the reserved-memory and BPMP bindings get support for Tegra264. * tag 'tegra-for-6.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCs dt-bindings: reserved-memory: Add support for DRAM MRQ GSCs dt-bindings: thermal: tegra: Convert to json-schema dt-bindings: arm: tegra: nvec: Convert to json-schema dt-bindings: clock: tegra: Document Tegra132 compatible dt-bindings: cpu: Document NVIDIA Tegra186 CCPLEX cluster dt-bindings: serial: tegra-hsuart: Convert to json-schema dt-bindings: arm: tegra: ahb: Convert to json-schema dt-bindings: arm: tegra: flowctrl: Convert to json-schema Link: https://lore.kernel.org/r/20230728094129.3587109-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-07-27ARM: tegra: Provide specific compatible string for Nexus 7 panelThierry Reding
panel-lvds alone is not a valid compatible string and we always need a specific compatible string as well. Nexus 7 can come with one of (at least) two panels, so pick one of them as the specific compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron ChagallThierry Reding
The LVDS bindings require a specific compatible string in addition to the generic "panel-lvds". Add the HannStar HSD101PWW2 which is used on a similar device (ASUS TF201) and seems to work fine with slightly modified timings in DT. Suggested-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27ARM: tegra: Reuse I2C3 for NVECThierry Reding
Instead of duplicating the I2C3 node and adding NVEC specific properties, reuse the I2C3 node, extend it with NVEC specific properties and drop properties that are not needed by NVEC. This results in a DTB that is a bit cleaner and avoids accidentally using I2C3 and NVEC which would have them fight over the same hardware resources. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add blank lines for better readabilityThierry Reding
Add a few blank lines to visually separate blocks in the Jetson AGX Orin device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Remove {clock,reset}-names from VIC powergateThierry Reding
According to the device tree bindings, the powergate definition nodes don't contain clock-names and reset-names properties, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Drop incorrect maxim,disable-etr on SmaugKrzysztof Kozlowski
There is no "maxim,disable-etr" property (but there is maxim,enable-etr), neither in the bindings nor in the Linux driver: tegra210-smaug.dtb: regulator@1c: Unevaluated properties are not allowed ('maxim,disable-etr' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add SPI device tree nodes for Tegra234Gautham Srinivasan
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers found on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Enable UARTA and UARTE for Orin NanoGautham Srinivasan
Activate UARTA and UARTE functionalities for Orin Nano. - UARTA is accessible via the 40-pin header with pin 8 and 10 (TX/RX) - UARTE utilizes the M2.E connector Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add UARTE device tree node on Tegra234Gautham Srinivasan
This commit adds the device tree node for UARTE on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: dts: renesas: spider-cpu: Add GP LEDsGeert Uytterhoeven
Describe the two General Purpose LEDs LED7 and LED8 on the Spider CPU board, so they can be used as indicator LEDs. Note that General Purpose LEDs LED9 to LED11 are not added, as they are connected to GPIO block 4, which can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/fdaf6c700b624851039a60733c7f73a413c6d2c5.1690447094.git.geert+renesas@glider.be
2023-07-27arm64: dts: renesas: r8a779f0: Add INTC-EX nodeGeert Uytterhoeven
Add the device node for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/8f5612c0353b8c90f98366978563340d93c7ae58.1690447013.git.geert+renesas@glider.be
2023-07-27arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3Biju Das
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27arm64: dts: renesas: r9a07g043: Add MTU3a nodeBiju Das
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27ARM dts: renesas: armadillo800eva: Switch to enable-gpiosKrzysztof Kozlowski
The recommended name for enable GPIOs property in regulator-gpio is "enable-gpios". This is also required by bindings: r8a7740-armadillo800eva.dtb: regulator-vccq-sdhi0: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230726070241.103545-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-26arm64: tegra: Adapt to LP855X bindings changesArtur Weber
Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add PCIe and DP 3.3V suppliesShubhi Garg
Add the 3.3V supplies for PCIe C1 controller and Display Port controller for the NVIDIA IGX Orin platform. Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add missing reset-names for Tegra HS UARTThierry Reding
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove current-speed for SBSA UARTThierry Reding
The SBSA UART device tree bindings don't define a current-speed property, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: smaug: Remove reg-shift for high-speed UARTThierry Reding
The device tree bindings for the high-speed UART don't define a reg-shift property, so delete it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove dmas and dma-names for debug UARTThierry Reding
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add 35°C trip point for Jetson Orin NX/NanoThierry Reding
It turns out that these devices can get quite hot to the touch with the standard cooling configuration, so add another trip point at 35°C along with a cooling map to help keep the system reasonably cool at very low system load. Reviewed-by: Yi-Wei Wang <yiweiw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove duplicate PCI nodesThierry Reding
The PCI nodes for Jetson Orin NX are already defined at the carrier board level, so the duplicates can be dropped at the platform level. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Sort PCI nodes correctly on OrinThierry Reding
Recent changes to several Orin boards didn't order some device tree nodes correctly. Resort them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add audio support for IGX OrinMohan Kumar
Add audio support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Move the common device-tree nodes to a new file tegra234-p3701.dtsi and use this for Jetson AGX Orin and NVIDIA IGX Orin platforms Signed-off-by: Mohan Kumar <mkumard@nvidia.com> [treding@nvidia.com: properly sort nodes] Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCsPeter De Schrijver
Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26dt-bindings: reserved-memory: Add support for DRAM MRQ GSCsPeter De Schrijver
Add bindings for DRAM MRQ GSC support. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25dt-bindings: thermal: tegra: Convert to json-schemaThierry Reding
Convert the Tegra thermal bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25dt-bindings: arm: tegra: nvec: Convert to json-schemaThierry Reding
Convert the NVIDIA embedded controller bindings from the free-form text format to json-schema. Acked-by: Marc Dietrich <marvin24@gmx.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25dt-bindings: clock: tegra: Document Tegra132 compatibleThierry Reding
The Tegra132 clock and reset controller is largely compatible with the version found on Tegra124 but it does have slight differences in what clocks it exposes, so a separate compatible string is needed. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-25arm64: dts: renesas: rzg2lc-smarc-som: Enable PMIC and built-in RTCBiju Das
Enable PMIC RAA215300 and the built-in RTC on the RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712151342.82690-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0Biju Das
The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy nodeConor Dooley
dtbs_check w/ W=1 complains: Warning (unit_address_vs_reg): /soc/ethernet@11c20000/ethernet-phy@7: node has a unit name, but no reg or ranges property Warning (avoid_unnecessary_addr_size): /soc/ethernet@11c20000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property The ethernet@11c20000 node is guarded by an `#if (!SW_ET0_EN_N)` in rzg2ul-smarc-som.dtsi, where the phy child node is added. In rzfive-smarc-som.dtsi, the ethernet node is marked disabled & the interrupt properties are deleted from the phy child node. As a result, the produced dts looks like: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; /* snip */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; ethernet-phy@7 { }; }; Adding a corresponding `#if (!SW_ET0_EN_N)` around the node in rzfive-smarc-som.dtsi avoids the complaint, as the empty child node is not added: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; /* snip */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712-squealer-walmart-9587342ddec1@wendy Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2lc-smarc: Add support for enabling MTU3Biju Das
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2LC SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230707155849.86649-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3Biju Das
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC EVK. The MTU3a PWM pins are muxed with spi1 pins and counter external input phase clock pins are muxed with scif2 pins. Disable these IPs when PMOD_MTU3 macro is enabled. Apart from this, the counter Z phase clock signal is muxed with the SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: Add missing space before {Krzysztof Kozlowski
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230705145912.293315-2-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25ARM: dts: renesas: Add missing space before {Krzysztof Kozlowski
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230705145912.293315-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: Minor whitespace cleanup around '='Krzysztof Kozlowski
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230702185252.44462-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l-smarc-som: Enable PMIC and built-in RTCBiju Das
Enable PMIC RAA215300 and the built-in RTC on the RZ/{G2L,V2L} SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230623140948.384762-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: r9a09g011: Add CSI nodesFabrizio Castro
The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI) IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only allowed access to CSI0 and CSI4. This commit adds SoC specific device tree support for CSI0 and CSI4. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230622113341.657842-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l: Fix txdv-skew-psec typosChris Paterson
It looks like txdv-skew-psec is a typo from a copy+paste. txdv-skew-psec is not present in the PHY bindings nor is it in the driver. Correct to txen-skew-psec which is clearly what it was meant to be. Given that the default for txen-skew-psec is 0, and the device tree is only trying to set it to 0 anyway, there should not be any functional change from this fix. Fixes: 361b0dcbd7f9 ("arm64: dts: renesas: rzg2l-smarc-som: Enable Ethernet") Fixes: 6494e4f90503 ("arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform") Fixes: ce0c63b6a5ef ("arm64: dts: renesas: Add initial device tree for RZ/G2LC SMARC EVK") Cc: stable@vger.kernel.org # 6.1.y Reported-by: Tomohiro Komagata <tomohiro.komagata.aj@renesas.com> Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230609221136.7431-1-chris.paterson2@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channelsBiju Das
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow interrupt names start with 'tci' instead of 'tgi'. Replace the below overflow/underflow interrupt names: - tgiv0->tciv0 - tgiv1->tciv1 - tgiu1->tciu1 - tgiv2->tciv2 - tgiu2->tciu2 - tgiv3->tciv3 - tgiv4->tciv4 - tgiv6->tciv6 - tgiv7->tciv7 - tgiv8->tciv8 - tgiu8->tciu8 Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230724091927.123847-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-24dt-bindings: cpu: Document NVIDIA Tegra186 CCPLEX clusterThierry Reding
Add device tree bindings for the CCPLEX cluster found on NVIDIA Tegra186 SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21ARM: tegra: Add missing reset-names for Tegra HS UARTThierry Reding
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21ARM: tegra: Remove reset-names for UART devicesThierry Reding
The UART devices found on Tegra chips have a single reset connected to them, so a reset-names property isn't needed. In fact, the device tree bindings don't allow this property, so remove them to allow the nodes to be properly validated. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21ARM: tegra: Remove dmas and dma-names for debug UARTThierry Reding
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-21dt-bindings: serial: tegra-hsuart: Convert to json-schemaThierry Reding
Convert the Tegra High-Speed UART bindings from the free-form text format to json-schema. While at it, also fix fix the example to reflect the correct compatible string for Tegra30 chips. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 03:06:57 +0000