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2018-02-19drm/amd/powerplay: delete some dead codeDan Carpenter
We deleted some code in e154162ef75d ("drm/amd/powerplay: refine pp code for raven") but there were a few related bits that were missed. Let's delete them as well. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/powerplay: Zero out power data in AMDGPU_PP_SENSOR_GPU_POWER readoutTom St Denis
Since 12 of the 16 bytes are not initialized with anything let's ensure they're sensibly zeroed out otherwise debugfs callers will read back garbage (because they assume debugfs wrote sensible data back...) Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Add primary tmz_c and meta tmz tmz_c.Yongqiang Sun
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: enable #PME code path for RV.Charlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: dal 3.1.32Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Optimize regamma calculationsKrunoslav Kovac
There are several optimizations: 1) Use predefined SRGB, don't calculate. This is the most common case. 2) Precompute HW X points at boot since they're fixed in ColModule 3) Precompute PQ - it never changes and is very CPU intensive in fixed pt. 4) Reduce number of points in ColModule to 512 (32x16) from 1024. This also requires reducing some regions for legacy DCEs to 16 pts at most. Performance 1) is super-fast, build_output_tf is 1-2us, down from 25000-30000. Programming also fast since only one reg write. 2)+3) gives build_output_tf for PQ in ~100us range, down from ~80000-110000 2) + 4) results in slightly over 50% improvement. It gives an idea of the savings when we can't use SRGB or PQ table (e.g. sdr white level > 80). There's also a bit of refactoring: renaming some stuff that was misleading and removing a lot of magic numbers that novices might not be able to understand where they come from and what they mean. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: resume from S3 bypass power down HW block.Charlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: add eDP 1.2+ polling for T7Charlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: dal 3.1.31Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Fixed if statement parameters to add a delay on disconnectJohn Barberiz
Signed-off-by: John Barberiz <jbarberi@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Add return value for detect dp.Yongqiang Sun
System soft hang when hotplug specific 4K DP panel due to link caps read error and incorrect link setting parmas to enable dp. Add status check for DPCD read and add return value for detect dp, in case of false, return from caller, avoid further false operation. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: fix boot-up on vega10Roman Li
Fixing null-deref on Vega10 due to regression after 'fix cursor related Pstate hang' change. Added null checks in setting cursor position. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Remove couple of unused OPTC registersNikola Cornij
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: turn off cursor when disconnect planeEric Yang
As a precaution to prevent cases where cursor is enabled on a pipe that is disabled, always turn off cursor when disconnecting plane. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Expose is_rgb_cspace function in hw_sequencerEric Bernstein
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: WBSCL filter init calculation fixesKen Chalmers
* Previous code did some calculations with a mix of normal integers and integers aligned as U2.24 fixed-point values. * There were bugs in the conversion of the final result into the S4.19 values required for the registers. Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: remove unused function prototypesEric Yang
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: fix cursor related Pstate hangEric Yang
Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK If graphics plane go from 1 pipe to hsplit, the cursor updates after mpc programming and unlock. Which means there is a window of time where cursor is enabled on the wrong pipe if it's on the right side of the screen (i.e. case where cursor need to move from pipe 0 to pipe 3 post split). This will cause pstate hang. Solution is to program the cursor while still locked. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Set irq state only on existing crtcsMikita Lipski
Because AMDGPU_CRTC_IRQ_VLINE1 = 6, it expected 6 more crtcs to be programed with disabled irq state in amdgpu_irq_disable_all. That caused errors and accessed the wrong memory location. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Null check for gamma correction.Yongqiang Sun
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Check hubp in pipe_ctx not in res_pool.Yongqiang Sun
When disable plane, check power gate flag in hubp with pipe_ctx, not with res_pool. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: sync the VM PD/PT before clearing itChristian König
Otherwise we might overwrite stuff which is still in use. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: dal 3.1.30Tony Cheng
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Bypass gamma set if not standard typeJohn Barberiz
If non-standard gamma type detected set identity matrix flag so that we can bypass the gamma mode. Signed-off-by: John Barberiz <jbarberi@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: wait for T9 after backlight off mainlink blank.Charlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Fix multiple definitions of handle_crc_irqLeo (Sunpeng) Li
If CONFIG_DEBUG_FS is disabled, then CRC should also be disabled. Therefore, amdgpu_dm_crtc_handle_crc_irq was redefined as a no-op function within amdgpu_dm.h. However, since amdgpu_dm.h is included in multiple files, this caused conflicts when linking during compile. Therefore, Use a macro to define the function as a no-op instead. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Fixed non-native modes not lighting upJerry (Fangzhi) Zuo
There is no need to call drm_mode_set_crtcinfo() again once crtc timing is decided. Otherwise non-native/unsupported timing might get overwritten. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Remove return when no EDID read.Martin Tsai
Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: BL setting save/restoreCharlene Liu
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROLHarry Wentland
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <tony.cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: clear the shadow fence as wellChristian König
It also needs to be initialized. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: release the VM shadow in the error path as wellChristian König
Without it we run into a memory leak. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: remove unused display_vblank_wait interfaceAlex Deucher
No longer used since we changed the MC programming sequence. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu/dce: fix mask in dce_v*_0_is_in_vblankAlex Deucher
Using the wrong mask. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Noticed-by: Hans de Ruiter <hans@keasigmadelta.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amd/display: fix incompatible structure layoutsArnd Bergmann
Building the amd display driver with link-time optimizations revealed a bug that caused dal_cmd_tbl_helper_dce80_get_table() and dal_cmd_tbl_helper_dce110_get_table() get called with an incompatible return type between the two callers in command_table_helper.c and command_table_helper2.c: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.h:31: error: type of 'dal_cmd_tbl_helper_dce80_get_table' does not match original declaration [-Werror=lto-type-mismatch] const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void); drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.c:351: note: 'dal_cmd_tbl_helper_dce80_get_table' was previously declared here const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void) drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.h:32: error: type of 'dal_cmd_tbl_helper_dce110_get_table' does not match original declaration [-Werror=lto-type-mismatch] const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void); drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.c:361: note: 'dal_cmd_tbl_helper_dce110_get_table' was previously declared here const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void) The two versions of the structure are obviously derived from the same one, but have diverged over time, before they got added to the kernel. This moves the structure to a new shared header file and uses the superset of the members, to ensure the interfaces are all compatible. Fixes: ae79c310b1a6 ("drm/amd/display: Add DCE12 bios parser support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: cache the fence to wait for a VMIDChristian König
Beneficial when a lot of processes are waiting for VMIDs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: restructure amdgpu_vmid_grabChristian König
Now that we have the different cases for grabbing a VMID in separate functions, restructure the top level function to only have one place where VMIDs are assigned to jobs. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: move reusing VMIDs into separate functionChristian König
Let's try this once more. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: cleanup and simplify amdgpu_vmid_grab_reservedChristian König
Drop the "_locked" from the name, cleanup and simplify the logic a bit. Add missing comments. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: stop checking GPU reset counter during VMID grabChristian König
We do this later on when we flush the VMID anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: make VMID owner none atomic v2Christian König
The variable is protected by the VMID mutex anyway. v2: grab the mutex while resetting the VMID as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: split finding idle VMID into separate functionChristian König
No functional change, but makes it easier to maintain the code. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: make VMID assignment more fair v2Christian König
Similar to finding an idle one before reuse. This guarantees fairness between processes. Otherwise process with a reserved VMID have an unfair advantage while scheduling jobs. v2: improve commit message Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: Fix always_valid bos multiple LRU insertions.Bas Nieuwenhuizen
If these bos are evicted and are in the validated list things blow up, so do not put them in there. Notably, that tries to add the bo to the LRU twice, which results in a BUG_ON in ttm_bo.c. While for the bo_list an alternative would be to not allow always valid bos in there, that does not work for the user fence. v2: Fixed whitespace issue pointed out by checkpatch.pl Signed-off-by: Bas Nieuwenhuizen <basni@chromium.org> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-02-19Revert "drm/amdgpu/gfx8: Fix compute ring failure after resetting"Andrey Grodzovsky
This reverts commit 75737cb4eb78c7f185e4700b4aa20cf7a3381aca. Fixes compute rings test failure on bare metal during full GPU reset. RCA: the ring buffer has to be filled with valid packets (such as NOPs) first before submitting MAP_QUEUEs packet into KIQ. Once a compute engine is mapped, it will immediately execute the ring buffer if the RTPR is not equal to the WTPR from the MQD. It could lead to engine hang if the ring buffer filled with random data. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlbChristian König
Keep that at a common place instead of spread over all engines. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement vcn_v1_0_(dec|enc)_ring_emit_reg_wait v2Christian König
Add emit_reg_wait implementation for VCN v1. v2: cleanup the existing code as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement vce_v4_0_emit_reg_wait v2Christian König
Add emit_reg_wait implementation for VCE v4. v2: call new function directly from existing code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement uvd_v7_0_(enc_|)ring_emit_reg_wait v2Christian König
Add emit_reg_wait implementation for UVD v7. v2: call new function directly from the existing code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement sdma_v4_0_ring_emit_reg_waitChristian König
Add emit_reg_wait implementation for SDMA v4. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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