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2016-02-19Merge branch 'sh-pfc-for-v4.6' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2016-02-19pinctrl: mediatek: add input-enable and direction setting for eint resourcesBiao Huang
To use pin as eint, user should make sure that: 1. pin is set to right mode, this is done in .irq_request_resources implementation already. 2. direction of the pin is input, which should call GPIO API to set pin to input gpio. We add what step 2 do to .irq_request_resources so that user doesn't need call GPIO API any more when pin for eint usage. Signed-off-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-19pinctrl: mediatek: add input-enable setting in gpio_request_enableBiao Huang
Since input-disable cuts off input signal of gpio, add input-enable setting in .gpio_request_enable implementation to ensure gpio function well Signed-off-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-18pinctrl: sh-pfc: r8a7794: Add EtherAVB pin groupsSergei Shtylyov
Add the EtherAVB pin groups to the R8A7794 PFC driver. Based on the patches by Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18pinctrl: sh-pfc: Rework PFC GPIO supportMagnus Damm
The sh-pfc pinctrl driver is currently handling SoC-specific PFC hardware blocks on ARM64, ARM and SH architectures. For older SoCs using SH cores and some 32-bit ARM SoCs the PFC hardware also provides GPIO functionality. On the majority of 32-bit ARM SoCs from Renesas and so far all ARM64 SoCs the GPIO feature is provided by separate hardware blocks. So far GPIO support in the PFC driver has been compiled-in for the majority of the SoCs, but with this patch applied the SoCs with PFC support may select from one of the following: - CONFIG_PINCTRL_SH_PFC - Used if PFC lacks GPIO hardware - CONFIG_PINCTRL_SH_PFC_GPIO - Used if PFC includes GPIO support This patch results in the following changes: - The GPIO functionality is only compiled-in on relevant SoCs - The number of lines of code is reduced Build tested using the following configurations: - r8a7795 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM64) - r8a7790 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM) - r8a7790 + r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM) - r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM) - sh7751 -> CONFIG_PINCTRL_SH_PFC=n -> OK (SH rts7751r2d1) - sh7724 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (SH ecovec24) Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> [geert: s/def_bool n/bool/] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18pinctrl: sh-pfc: r8a7795: Add PWM supportTakeshi Kihara
This patch adds PWM[0-6] pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: adapted to mainline PFC driver] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pinsMagnus Damm
Most pins on the r8a7795 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Tested on r8a7795 Salvator-X with an external loop back adapter on EXIO_D that connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06). Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18pinctrl: sh-pfc: r8a7794: Add audio clock pin groupsRyo Kataoka
Add the audio clock pin groups to the R8A7794 PFC driver. [Sergei: fixed pin group names to reflect the reality, fixed pin names in the comments to *_pins[], lowercased the separator comment, resolved rejects, added the changelog, renamed the patch.] Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-18pinctrl: sh-pfc: r8a7794: Add SSI pin groupsRyo Kataoka
Add the SSI pin groups to the R8A7794 PFC driver. [Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin groups into data/control ones, moved SSI7 data B group to its proper place, fixed pin names in the comments to *_pins[], extended Cogent Embedded's copyright, added the changelog, renamed the patch.] Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-17pinctrl: mtk2701: skip setting .ownerLinus Walleij
The device core will handle this and Coccinelle complains. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-16pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl supportVaradarajan Narayanan
Add pinctrl driver support for IPQ4019 platform Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> [Dropped .owner assignment] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-16pinctrl: mediatek: fix handling return value of mtk_pmx_find_gpio_modeAndrzej Hajda
The function can return negative values, so its result should be assigned to signed variable. The problem has been detected using coccinelle semantic patch scripts/coccinelle/tests/assign_signed_to_unsigned.cocci. Fixes: 59ee9c9 ('pinctrl: mediatek: Add gpio_request_enable support') Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-16pinctrl: Turn AMD support to tristateJean Delvare
The pinctrl-amd driver builds just fine as a module so give users this option. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-15pinctrl: coh901: fix initconst annotationArnd Bergmann
Clang correctly points out that the section attribute for u300_gpio_confdata is in the wrong place: drivers/pinctrl/pinctrl-coh901.c:130:37: error: '__section__' attribute only applies to functions and global variables This moves it from the type name to the variable, so it actually gets discarded. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-15pinctrl: Fix return value check in amd_gpio_probe()Wei Yongjun
In case of error, the function devm_ioremap_nocache() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-15pinctrl: zynq: fix typo in group name for qspi1Helmut Buchsbaum
Due to a typo Zynq pin controller does not set pin function of qspi1 when using function qspi1. So pin group for qspi1 has to be renamed to "qspi1_0_grp" as outlined in the corresponding bindings documentation. This also removes kernel message: zynq-pinctrl 700.pinctrl: invalid group "qspi1_0_grp" for function "qspi1" Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-13pinctrl: mediatek: guard sub-directory with CONFIG_PINCTRL_MTKMasahiro Yamada
CONFIG_PINCTRL_MTK is more suitable than CONFIG_ARCH_MEDIATEK to guard the drivers/pinctrl/mediatek/ directory. (I renamed CONFIG_PINCTRL_MTK_COMMON to CONFIG_PINCTRL_MTK.) This allows COMPILE_TEST to descend into drivers/pinctrl/mediatek without CONFIG_ARCH_MEDIATEK define. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-12pinctrl: intel: Remove unneeded header includesJean Delvare
pinctrl-intel doesn't use anything from <linux/init.h>, <linux/acpi.h>, <linux/gpio.h> or <linux/pm.h>, so it should not include these header files. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-11pinctrl: sunxi: Use pin number when calling sunxi_pmx_setKrzysztof Adamski
sunxi_pmx_set accepts pin number and then calculates offset by subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand, gets offset so we have to convert it to pin number so we won't get negative value in sunxi_pmx_set. This was only used on A10 so far, where there is only one GPIO chip with pin_base set to 0 so it didn't matter. However H3 also requires this workaround but have two pinmux sections, triggering problem for PL port. Signed-off-by: Krzysztof Adamski <k@japko.eu> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-11pinctrl: sunxi: Add H3 R_PIO controller supportKrzysztof Adamski
H3 has additional PIO controller similar to what we can find on A23. It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350. Signed-off-by: Krzysztof Adamski <k@japko.eu> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-10pinctrl: rockchip: add support for the rk3399David Wu
The pinctrl of rk3399 is much different from other's, especially the 3bits of drive strength. Signed-off-by: David Wu <david.wu@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-10pinctrl: uniphier: add COMPILE_TEST optionMasahiro Yamada
Add COMPILE_TEST for the compilation test coverage. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-09Merge branch 'devel-mt2701' into develLinus Walleij
2016-02-09pinctrl: stm32: Fix compile testing selectionMaxime Coquelin
While selecting the driver for compile testing seemed possible, the driver was not compiled because the driver directory was only added if ARCH_STM32 was selected. This patch now makes the pinctrl Makefile to add stm32 directory if PINCTRL_STM32 is selected. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-09pinctrl: stm32: Remove dependency with DT bindings header filesMaxime Coquelin
Some macros where defined in DT bindings headers, whereas only used in the driver. This patch moves these macros to the driver side. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-08pinctrl: sh-pfc: r8a7795: Add USB2.0 host supportTakeshi Kihara
This patch adds USB[0-2] (USB2.0 host) pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-08pinctrl: sh-pfc: r8a7795: Remove bits SEL_VSP_1 and SEL_VSP_0Geert Uytterhoeven
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact, as the definitions were not really used. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-08pinctrl: sh-pfc: r8a7795: Rename SSI_{WS,SCK}0129 to SSI_{WS,SCK}01239Geert Uytterhoeven
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact, as the string used for configuration ("ssi01239_ctrl") was already correct. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-08pinctrl: sh-pfc: Rename PINMUX_IPSR_DATA() to PINMUX_IPSR_GPSR()Geert Uytterhoeven
This macro describes a pinmux configuration that needs configuration in both a Peripheral Function Select Register (IPSR) and in a GPIO/Peripheral Function Select Register 1 (GPSR). Reflect that in the macro name for clarity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-02-08pinctrl: sh-pfc: Improve pinmux macros documentationGeert Uytterhoeven
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-02-05pinctrl: pinctrl-pic32: Add PIC32 pin control driverJoshua Henderson
Add a driver for the pin controller present on the Microchip PIC32 including the specific variant PIC32MZDA. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-05pinctrl: Add DT bindings for PIC32 pin control and GPIOJoshua Henderson
Document the devicetree bindings for PINCTRL and GPIO found on Microchip PIC32 class devices. Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com> Cc: Ralf Baechle <ralf@linux-mips.org> Acked-by: Rob Herring <robh@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-05pinctrl: stm32: fix compile error and modernizeLinus Walleij
- Fix the dev->parent assignment compile error - Use gpiochip_get_data() to get the data pointer for the banks Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-05pinctrl: tegra: move Tegra pinctrl drivers to sub-directoryMasahiro Yamada
Tegra has several pinctrl drivers. Now it is reasonable enough to move them into drivers/pinctrl/tegra/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-02-05pinctrl: mediatek: Add gpio_request_enable supportBiao Huang
Implement the .gpio_request_enable() callbacks in struct pinmux_ops in mediatek pinctrl driver. Make sure that when gpio_request is called, GPIO on the pin is enabled. Signed-off-by: Biao Huang <biao.huang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28pinctrl: sunxi: guard sub-directory with CONFIG_PINCTRL_SUNXIMasahiro Yamada
CONFIG_PINCTRL_SUNXI is more suitable than CONFIG_ARCH_SUNXI to guard the drivers/pinctrl/sunxi/ directory. (I renamed CONFIG_PINCTRL_SUNXI_COMMON to CONFIG_PINCTRL_SUNXI.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28pinctrl: nomadik: stn8815 CLCD alternate functionsLinus Walleij
The STn8815 has 22 dedicated pins for CLCD with up to 16 bits in parallel, but pins 32 thru 39 can be used for an additional CLCD signal lines 16 thru 23. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28pinctrl: pxa: guard sub-directory with CONFIG_PINCTRL_PXAMasahiro Yamada
CONFIG_PINCTRL_PXA is more suitable than CONFIG_ARCH_PXA to guard the drivers/pinctrl/pxa/ directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28pinctrl: mediatek: Add Pinctrl/GPIO/EINT driver for mt2701Biao Huang
Add mt2701 support using mediatek common pinctrl driver. MT2701 have some special pins need an extra setting register than other ICs, so adding this support to common code. Signed-off-by: Biao Huang <biao.huang@mediatek.com> Acked-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-28pinctrl: dt bindings: Add pinfunc header file for mt2701Biao Huang
Add pinfunc header file, mt2701 related dts will include it Signed-off-by: Biao Huang <biao.huang@mediatek.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27pinctrl: qcom: spmi-mpp: Skip pullup on ULT type MPPsStephen Boyd
The ULT type of MPPs don't have a pullup. Skip configuring the pullup on these types of pins. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27pinctrl: freescale: imx: implement gpio_disable_free for VybridStefan Agner
The Freescale Vybrid SoC has GPIO capabilities as part of the IOMUXC. To enable GPIO's, the gpio_request_enable callback has been implemented, however the corsponding gpio_disable_free callback is missing. So far, disabling (unexporting) a GPIO left the pin in its last state. Implement a proper gpio_disable_free function which clears the three enable bits which influence the state (IBE, OBE and PUE). Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27pinctrl: mediatek: mt8* make driver explicitly non-modularPaul Gortmaker
The Kconfig for these drivers are currently: config PINCTRL_MT8127 bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127 config PINCTRL_MT8135 bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135 config PINCTRL_MT8173 bool "Mediatek MT8173 pin control" ...meaning that they are currently not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. A recent commit moved these from module_init to arch_initcall already, so the init ordering remains untouched with this commit. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. Cc: Daniel Kurtz <djkurtz@chromium.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: linux-gpio@vger.kernel.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27pinctrl: Add STM32 MCUs supportMaxime Coquelin
This patch adds pinctrl and GPIO support to STMicroelectronic's STM32 family of MCUs. While it only supports STM32F429 for now, it has been designed to enable support of other MCUs of the family (e.g. STM32F746). Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27Documentation: dt-bindings: Document STM32 pinctrl driver DT bindingsMaxime Coquelin
Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-27pinctrl: st: activate strict mux modePatrice Chotard
This activates strict mode muxing for the ST pin controllers, as these do not allow GPIO and functions to use the same pin simultaneously. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-24Linux 4.5-rc1v4.5-rc1Linus Torvalds
2016-01-24Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for 4.5 plus some 4.4 fixes. The executive summary: - ATH79 platform improvments, use DT bindings for the ATH79 USB PHY. - Avoid useless rebuilds for zboot. - jz4780: Add NEMC, BCH and NAND device tree nodes - Initial support for the MicroChip's DT platform. As all the device drivers are missing this is still of limited use. - Some Loongson3 cleanups. - The unavoidable whitespace polishing. - Reduce clock skew when synchronizing the CPU cycle counters on CPU startup. - Add MIPS R6 fixes. - Lots of cleanups across arch/mips as fallout from KVM. - Lots of minor fixes and changes for IEEE 754-2008 support to the FPU emulator / fp-assist software. - Minor Ralink, BCM47xx and bcm963xx platform support improvments. - Support SMP on BCM63168" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (84 commits) MIPS: zboot: Add support for serial debug using the PROM MIPS: zboot: Avoid useless rebuilds MIPS: BMIPS: Enable ARCH_WANT_OPTIONAL_GPIOLIB MIPS: bcm63xx: nvram: Remove unused bcm63xx_nvram_get_psi_size() function MIPS: bcm963xx: Update bcm_tag field image_sequence MIPS: bcm963xx: Move extended flash address to bcm_tag header file MIPS: bcm963xx: Move Broadcom BCM963xx image tag data structure MIPS: bcm63xx: nvram: Use nvram structure definition from header file MIPS: bcm963xx: Add Broadcom BCM963xx board nvram data structure MAINTAINERS: Add KVM for MIPS entry MIPS: KVM: Add missing newline to kvm_err() MIPS: Move KVM specific opcodes into asm/inst.h MIPS: KVM: Use cacheops.h definitions MIPS: Break down cacheops.h definitions MIPS: Use EXCCODE_ constants with set_except_vector() MIPS: Update trap codes MIPS: Move Cause.ExcCode trap codes to mipsregs.h MIPS: KVM: Make kvm_mips_{init,exit}() static MIPS: KVM: Refactor added offsetof()s MIPS: KVM: Convert EXPORT_SYMBOL to _GPL ...
2016-01-24Merge tag 'platform-drivers-x86-v4.5-2' of ↵Linus Torvalds
git://git.infradead.org/users/dvhart/linux-platform-drivers-x86 Pull x86 platform driver updates from Darren Hart: "Emergency travel prevented me from completing my final testing on this until today. Nothing here that couldn't wait until RC1 fixes, but I thought it best to get it out sooner rather than later as it does contain a build warning fix. Summary: A build warning fix, MAINTAINERS cleanup, and a new DMI quirk: ideapad-laptop: - Add Lenovo Yoga 700 to no_hw_rfkill dmi list MAINTAINERS: - Combine multiple telemetry entries intel_telemetry_debugfs: - Fix unused warnings in telemetry debugfs" * tag 'platform-drivers-x86-v4.5-2' of git://git.infradead.org/users/dvhart/linux-platform-drivers-x86: ideapad-laptop: Add Lenovo Yoga 700 to no_hw_rfkill dmi list MAINTAINERS: Combine multiple telemetry entries intel_telemetry_debugfs: Fix unused warnings in telemetry debugfs
2016-01-24Merge branch 'next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux Pull thermal management updates from Zhang Rui: "The top merge commit was re-generated yesterday because two topic branches were dropped from this pull request in the last minute due to some unaddressed comments. All the other material has been in linux-next for quite a while. Specifics: - Enhance thermal core to handle unexpected device cooling states after fresh boot and system resume. From Zhang Rui and Chen Yu. - Several fixes and cleanups on Rockchip and RCAR thermal drivers. From Caesar Wang and Kuninori Morimoto. - Add Broxton support for Intel processor thermal reporting device driver. From Amy Wiles" * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: thermal: trip_point_temp_store() calls thermal_zone_device_update() thermal: rcar: rcar_thermal_get_temp() return error if strange temp thermal: rcar: check irq possibility in rcar_thermal_irq_xxx() thermal: rcar: check every rcar_thermal_update_temp() return value thermal: rcar: move rcar_thermal_dt_ids to upside thermal: rockchip: Support the RK3399 SoCs in thermal driver thermal: rockchip: Support the RK3228 SoCs in thermal driver dt-bindings: rockchip-thermal: Support the RK3228/RK3399 SoCs compatible thermal: rockchip: fix a trivial typo Thermal: Enable Broxton SoC thermal reporting device thermal: constify pch_dev_ops structure Thermal: do thermal zone update after a cooling device registered Thermal: handle thermal zone device properly during system sleep Thermal: initialize thermal zone device correctly
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 16:02:50 +0000