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2025-01-03drm/i915/hdmi: propagate errors from intel_hdmi_init_connector()Jani Nikula
Propagate errors from intel_hdmi_init_connector() to be able to handle them at callers. This is similar to intel_dp_init_connector(). Cc: Sergey Senozhatsky <senozhatsky@chromium.org> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reported-and-tested-by: Sergey Senozhatsky <senozhatsky@chromium.org> Closes: https://lore.kernel.org/r/20241031105145.2140590-1-senozhatsky@chromium.org Reviewed-by: Sergey Senozhatsky <senozhatsky@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/cdaf9e32cc4880c46e120933438c37b4d87be12e.1735568047.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-01-03drm/i915/ddi: change intel_ddi_init_{dp, hdmi}_connector() return typeJani Nikula
The caller doesn't actually need the returned struct intel_connector; it's stored in the ->attached_connector of intel_dp and intel_hdmi. Switch to returning an int with 0 for success and negative errors codes to be able to indicate success even when we don't have a connector. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Tested-by: Sergey Senozhatsky <senozhatsky@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/8ef7fe838231919e85eaead640c51ad3e4550d27.1735568047.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-24drm/i915/dp_mst: Use link.{min/max}_bpp_x16Ankit Nautiyal
The link.{min/max}_bpp_x16 is already set in crtc_state, use that while computing link config for MST. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-15-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Set the DSC link limits in intel_dp_compute_config_link_bpp_limitsAnkit Nautiyal
The helper intel_dp_compute_config_link_bpp_limits is the correct place to set the DSC link limits. Move the code to this function and remove the #TODO item. v2: Add argument intel_connector to the helper to get correct connector for DP MST. (Imre) v3: Remove redundant calls to intel_dp_dsc_sink_max_compressed_bpp as its already accounted while setting link bpp limits. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-14-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Make dsc helpers accept const crtc_state pointersAnkit Nautiyal
Modify the dsc helpers to get max/min compressed bpp to accept `const struct intel_crtc_state *` pointers instead of `struct intel_crtc_state *`. These helpers are not supposed to modify `crtc_state`. Accepting const pointers will allow these helpers to be called from functions that have const pointer to crtc_state. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-13-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Use clamp for pipe_bpp limits with DSCAnkit Nautiyal
Currently to get the max pipe_bpp with dsc we take the min of limits->pipe.max_bpp and dsc max bpp (dsc max bpc * 3). This can result in problems when limits->pipe.max_bpp is less than the computed dsc min bpp (dsc min bpc * 3). Replace the min/max functions with clamp while computing limits->pipe.max/min_bpp to ensure that the pipe_bpp limits are constrained within the DSC-defined minimum and maximum values. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-12-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp_mst: Use pipe_bpp->limits.{max/min}_bpp for dscAnkit Nautiyal
The dsc limits->pipe.max/min_bpp are already set in intel_dp_compute_config_limits. Use the limits while computing the link config with DSC for MST. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-11-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Refactor pipe_bpp limits with dscAnkit Nautiyal
With DSC there are additional limits for pipe_bpp. Currently these are scattered in different places. Instead set the limits->pipe.max/min_bpp in one place and use them wherever required. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-10-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Drop max_requested_bpc for dsc pipe_min/max bppAnkit Nautiyal
Currently we are including both max_requested_bpc and limits->pipe.bpp_max while computing maximum possible pipe bpp with dsc. However, while setting limits->pipe.max_bpp, the max_requested_bpc is already taken into account. Drop the redundant check for max_requested_bpc and use only limits->pipe.bpp_max. This will also result in dropping conn_state argument in functions where it was used only to get max_requested_bpc. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-9-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp_mst: Use helpers to get dsc min/max input bpcAnkit Nautiyal
Use helpers for source min/max input bpc with DSC. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-8-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Return int from dsc_max/min_src_input_bpc helpersAnkit Nautiyal
Use ints for dsc_max/min_bpc instead of u8 in dsc_max/min_src_input_bpc helpers and their callers. This will also help replace min_t/max_t macros with min/max ones. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-7-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Remove HAS_DSC macro for intel_dp_dsc_max_src_input_bpcAnkit Nautiyal
DSC support is already checked before the helper intel_dp_dsc_max_src_input_bpc is called. Remove the check from the helper. v2: Drop the argument struct drm_i915_private *i915. (Suraj) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-6-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Drop check for FEC in intel_dp_fec_compute_configAnkit Nautiyal
Support for FEC is already checked by intel_dp_supports_dsc() in intel_dp_dsc_compute_config() which gets called before intel_dp_fec_compute_config(). Therefore the check can be dropped from the helper intel_dp_fec_compute_config(). v2: Changed commit message for clarity. (Suraj) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-5-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Separate out helper for compute fec_enableAnkit Nautiyal
Make a separate function for setting fec_enable in crtc_state. v2: Rename helper to align with encoder->compute_config() callback and other minor fixes. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-4-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Return early if DSC not supportedAnkit Nautiyal
Check for DSC support before computing link config with DSC. For DP MST we are already doing the same. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-3-ankit.k.nautiyal@intel.com
2024-12-24drm/i915/dp: Refactor FEC support check in intel_dp_supports_dscAnkit Nautiyal
Forward Error Correction is required for DP if we are using DSC but is optional for eDP. Currently the helper intel_dp_supports_dsc checks if fec_enable is set for DP or not. The helper is called after fec_enable is set in crtc_state. Instead of this a better approach would be to: first, call intel_dp_supports_dsc to check for DSC support (along with FEC requirement for DP) and then set fec_enable for DP (if not already set) in crtc_state. To achieve this, remove the check for fec_enable in the helper and instead check for FEC support for DP. With this change the helper intel_dp_supports_dsc can be called earlier and return early if DSC is not supported. The structure intel_dp is added to the helper to get the FEC support for DP. v2: Pass intel_dp to adjust_limits_for_dsc_hblank_expansion_quirk instead of deriving it from connector. (Jani) Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217093244.3938132-2-ankit.k.nautiyal@intel.com
2024-12-20drm/i915/selftests: Use preemption timeout on cleanupJanusz Krzysztofik
Many selftests call igt_flush_test() on cleanup. With default preemption timeout of compute engines raised to 7.5 seconds, hardcoded flush timeout of 3 seconds is too short. That results in GPU forcibly wedged and kernel taineted, then IGT abort triggered. CI BAT runs loose a part of their expected coverage. Calculate the flush timeout based on the longest preemption timeout currently configured for any engine. That way, selftest can still report detected issues as non-critical, and the GPU gets a chance to recover from preemptible hangs and prepare for fluent execution of next test cases. Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061 Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20241213190122.513709-2-janusz.krzysztofik@linux.intel.com
2024-12-20drm/i915/dg1: Fix power gate sequence.Rodrigo Vivi
sub-pipe PG is not present on DG1. Setting these bits can disable other power gates and cause GPU hangs on video playbacks. VLK: 16314, 4304 Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13381 Fixes: 85a12d7eb8fe ("drm/i915/tgl: Fix Media power gate sequence.") Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241219210019.70532-1-rodrigo.vivi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-12-20drm/i915/dmc_wl: store register ranges in rodataJani Nikula
Add const to register range arrays to store them in rodata. They don't need to be modified. Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241218141734.2583601-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-18drm/i915/display: drop unnecessary i915_drv.h includesJani Nikula
Now that we don't include i915_drv.h via any headers from display, we can reliably remove unnecessary i915_drv.h includes and be sure they're not indirectly included. Add other includes where needed. v2: Fix 32-bit build Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241217132147.2008057-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-18drm/i915/cx0_phy: Fix C10 pll programming sequenceSuraj Kandpal
According to spec VDR_CUSTOM_WIDTH register gets programmed after pll specific VDR registers and TX Lane programming registers are done. Moreover we only program into C10_VDR_CONTROL1 to update config and setup master lane once all VDR registers are written into. Bspec: 67636 Fixes: 51390cc0e00a ("drm/i915/mtl: Add Support for C10 PHY message bus and pll programming") Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241216181554.2861381-1-suraj.kandpal@intel.com
2024-12-17drm/i915/dsc: Expose dsc sink max slice count via debugfsSwati Sharma
Number of DSC slices can be shown in the DSC debugfs so that test can take a call whether the configuration can support forcing bigjoiner/ultrajoiner. v2: used intel_dp_is_edp() as the parameter to drm_dp_dsc_sink_max_slice_count() (Jani N) Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> (v1) Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/3387 Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213093008.2149452-1-swati2.sharma@intel.com
2024-12-16drm/i915/display: drop i915_drv.h include from intel_display_trace.hJani Nikula
Finish the job of removing implicit dependencies on i915_drv.h via other includes in display code. Add a few missing explicit includes. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c51352a2152cebd56ab3597ae5a791d2bb41439e.1732104170.git.jani.nikula@intel.com
2024-12-16drm/i915/display: add struct drm_device to struct intel_display conversion ↵Jani Nikula
function Add a __drm_to_display() conversion function to hide the to_i915() usage and the implicit dependency on i915_drv.h from intel_display_types.h. The goal is for this implementation to be a transitional helper only. One idea I've floated around in the past would be to require a struct intel_display pointer member to be placed right after struct drm_device member in struct drm_i915_private and struct xe_device [1][2]. [1] https://lore.kernel.org/r/7777ff70e2be0663de4398aa6f75f0c54146cbfc.1709727127.git.jani.nikula@intel.com [2] https://lore.kernel.org/r/0b9459da6c8cba0f74bf2781d69182fa6801cd97.1709727127.git.jani.nikula@intel.com Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/cbbf26fa58ef662946303c972b1a1ff1547ddcfe.1732104170.git.jani.nikula@intel.com
2024-12-16drm/i915/uncore: add to_intel_uncore() and use itJani Nikula
Add to_intel_uncore() function to avoid the inclusion of i915_drv.h from intel_de.h. This reveals a number of implicit dependencies on i915_drv.h that need to be added. For now, to_intel_uncore() can be an inline function, with all the includes in compat intel_uncore.h, as long as i915_drv.h isn't included. The implicit dependencies on i915_drv.h is a problem in display code, but the same is not true for xe_device.h etc. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/377e2b400d126776224fc49874ed9cb03ac3123c.1732104170.git.jani.nikula@intel.com
2024-12-16drm/i915/display: add intel_display_conversion.c to hide stuff betterJani Nikula
The __to_intel_display() generics require the definition of struct drm_i915_private i.e. inclusion of i915_drv.h. Add intel_display_conversion.c with a __i915_to_display() function to do the conversion without the intel_display_conversion.h having an implicit dependency on i915_drv.h. The long term goal is to remove __to_intel_display() and the intel_display_conversion.[ch] files altoghether, and this is merely a transitional step to make the dependencies on i915_drv.h explicit. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/39e99b765b8c1a05d001659c39686a661ac268e2.1732104170.git.jani.nikula@intel.com
2024-12-16drm/i915: extract intel_uncore_trace.[ch]Jani Nikula
The i915_reg_rw tracing is a small isolated part of i915_trace.h. Its users are orthogonal to the other i915_trace.h users as well, and its implementation does not require all the includes of i915_trace.h. Split i915_reg_rw tracing to separate intel_uncore_trace.[ch]. The main underlying goal is to reduce implicit includes of i915_drv.h from display code. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1a3623fbb120adc55bc1cab1e27aca6e55487163.1732104170.git.jani.nikula@intel.com
2024-12-16drm/i915/gvt: always pass struct intel_display * to register macrosJani Nikula
The long term goal is to remove the __to_intel_display() generics from display macros, such as register macros. This requires that all such macro usage passes struct intel_display * rather than struct drm_i915_private * to the macros. The short term goal is to hide the struct drm_i915_private access in intel_display_conversions.h into a function. This is problematic with gvt, because it's a separate module, and the conversion function would need to be exported. Make the conversion to always passing struct intel_display * in gvt to unblock both of the above. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/266616e14db8d9a342fd93ec9752f561149a799b.1732104170.git.jani.nikula@intel.com
2024-12-16drm/i915/dp: finish link training conversion to struct intel_displayJani Nikula
Convert the final stragglers to struct intel_display now that we have platform identification via it too. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/14a214fc358eafba8d57c25e0d26c8c35856dc89.1734083244.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915/dp: convert interfaces to struct intel_displayJani Nikula
Convert the intel_dp.[ch] external interfaces to struct intel_display. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/7d55f5fd9fc0619be3113098a49259d5374013c6.1734083244.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915/dp: convert to struct intel_displayJani Nikula
Going forward, struct intel_display is the main device data structure for display. Switch to it internally in DP code. v2/v3: Rebase Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d712a2894addde5fd7a8b593fbea87314df37e1f.1734083244.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915/dp: s/intel_connector/connector/Jani Nikula
Use the contemporary naming convention of struct intel_connector *connector. Avoid struct drm_connector use altogether. In a few cases add local struct drm_display_info and struct intel_display pointers to help move away from struct drm_connector usage. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/2951b76d7476adcffb6d16079ab52207d1aab92d.1734083244.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915/dp: s/intel_encoder/encoder/Jani Nikula
Use the contemporary naming convention of struct intel_encoder *encoder. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d1d3fb9254871d9a334e3f20b219bdf772426e66.1734083244.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915/mst: use intel_dp_compute_config_limits() for DP MSTJani Nikula
There's a lot of duplication between mst_stream_compute_config_limits() and intel_dp_compute_config_limits(). Adjust the latter to suit the needs of the former, and use the same function for both. This reduces duplication and highlights the differences for SST and MST and UHBR. Remove the kernel-doc for intel_dp_compute_config_link_bpp_limits() which now becomes static. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211144310.701895-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915/xe3: do not configure auto min dbuf for cursor WMsVinod Govindapillai
Cursor planes do not have the minimum dbuf configuration. The ddb allocation and registration routines handle this correctly. But the plane wm handling for cursor need to be differentiated for this case. Auto minimum buf enable bit should not be enabled for cursor wm registers in xe3. Fixes: a831920c370c ("drm/i915/xe3: Use hw support for min/interim ddb allocations for async flip") Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213120357.300584-1-vinod.govindapillai@intel.com Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2024-12-16drm/i915: move DDI_CLK_VALFREQ next to other Cx0 PHY registersJani Nikula
Relocate DDI_CLK_VALFREQ register definition next to other Cx0 PHY register macros. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-3-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915: relocate _VGA_MSR_WRITE register definitionJani Nikula
Move _VGA_MSR_WRITE to intel_crt_regs.h. It's not necessarily the optimal place for it, but hands down better than i915_reg.h. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-16drm/i915: split out i9xx_wm_regs.hJani Nikula
Very few files need the i9xx watermark related registers. Split them out to a dedicated file. Reviewed-by: Luca Coelho <luciano.coelho@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213115111.335474-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-12drm/i915/xe3: Use hw support for min/interim ddb allocations for async flipStanislav Lisovskiy
Xe3 is capable of switching automatically to min ddb allocation (not using any extra blocks) or interim SAGV-adjusted allocation in case if async flip is used. Introduce the minimum and interim ddb allocation configuration for that purpose. Also i915 is replaced with intel_display within the patch's context v2: update min/interim ddb declarations and handling (Ville) update to register definitions styling consolidation of minimal wm0 check with min DDB check Bspec: 69880, 72053 Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-4-vinod.govindapillai@intel.com
2024-12-12drm/i915/display: add a gelper to relative data rate handlingVinod Govindapillai
Add a helper to the relative data rate handling in skl_watermarks.c where other similar functions are implemented. Also get rid of use_min_ddb() and use use_minimal_wm0() instead to decide whether the relative data rate can be returned as 0 v2: re-phrase the commit description (uma) Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-3-vinod.govindapillai@intel.com
2024-12-12drm/i915/display: update to plane_wm register access functionVinod Govindapillai
Future platforms can have new additions in the plane_wm registers. So update skl_wm_level_from_reg_val() to have possiblity for such platform differentiations. This is in preparation for the rest of the patches in this series where hw support for the minimum and interim ddb allocations for async flip is added. Replace all the i915 uses to intel_display in this function while updating this function Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241121112726.510220-2-vinod.govindapillai@intel.com
2024-12-11drm/i915/dg2: Implement Wa_14022698537Raag Jadav
G8 power state entry is disabled due to a limitation on DG2, so we enable it from driver with Wa_14022698537. For now we enable it for all DG2 devices with the exception of a few, for which, we enable only when paired with whitelisted CPU models. This works with native ASPM and reduces idle power consumption. $ echo powersave > /sys/module/pcie_aspm/parameters/policy $ lspci -s 0000:03:00.0 -vvv LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk- v2: Fix Wa_ID and include it in subject (Badal) Rephrase commit message (Jani) v3: Move workaround to i915_pcode_init() (Badal, Anshuman) Re-order macro (Riana) v4: Spell fix (Riana) Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-5-raag.jadav@intel.com
2024-12-11drm/i915: Introduce intel_cpu_info.c for CPU IDsRaag Jadav
Having similar naming convention in intel-family.h and intel_device_info.h results in redefinition of a few platforms. Define CPU IDs in its own file to avoid this. v3: Move file out of gt directory, add kernel doc (Riana) Rephrase file description (Jani) Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-4-raag.jadav@intel.com
2024-12-11drm/i915/dg2: Introduce DG2_D subplatformRaag Jadav
Introduce DG2_D subplatform for the devices that span across multiple DG2 subplatforms but are within same segment and will be useful for segment specific features. v3: Rework subplatform naming (Jani) Split subplatform check into separate case (Jani) Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-3-raag.jadav@intel.com
2024-12-11drm/intel/pciids: Refactor DG2 PCI IDs into segment rangesRaag Jadav
Refactor DG2 PCI IDs into D, E and M ranges which will be useful for segment specific features. v3: Rework subplatform naming (Jani) Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211115952.1659287-2-raag.jadav@intel.com
2024-12-11Merge drm/drm-next into drm-intel-nextRodrigo Vivi
Catching up with 6.13-rc2. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2024-12-11drm/i915/dp: move g4x_dp_set_clock() call to g4x_dp_compute_config()Jani Nikula
It does not look like anything in intel_dp_compute_config() after the g4x_dp_set_clock() call depends on the changes it makes, namely setting dpll and clock_set in crtc_state. Move the call one level higher to g4x_dp_compute_config() to reduce the clutter in intel_dp_compute_config(). Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211125431.680227-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-11drm/i915/dp: add g4x_dp_compute_config()Jani Nikula
Add g4x_dp_compute_config() instead of using intel_dp_compute_config() directly, in order to slightly reduce the clutter in the latter wrt ->has_pch_encoder. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241211125431.680227-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-11drm/i915/display: clean up DP Adaptive Sync SDP state mismatch loggingJani Nikula
Pass the drm_printer from intel_pipe_config_compare(), and use it for logging, along with pipe_config_mismatch(), to simplify and unify. While at it, differentiate the VSC and AS SDP log texts from each other. Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241205093042.3028608-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-12-10drm/i915/display: use drm_print_hex_dump() for buffer mismatch dumpsJani Nikula
Use the drm_printer based printer to get the device specific printing of the hex dump, and avoid the manual loglevel hacking. Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a536050b5f9dc2d7de32d29766c98477f58d746c.1733392101.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 22:58:36 +0000