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2022-10-17arm64: dts: qcom: sdm845-xiaomi-beryllium-ebbg: introduce Xiaomi Poco F1 ↵Joel Selvaraj
EBBG variant Introduce support for the Xiaomi Poco F1 EBBG variant. The EBBG variant uses EBBG FT8719 panel manufactured by EBBG. Signed-off-by: Joel Selvaraj <joelselvaraj.oss@gmail.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909035447.36674-4-joelselvaraj.oss@gmail.com
2022-10-17dt-bindings: arm: qcom: Add Xiaomi Poco F1 EBBG variant bindingsJoel Selvaraj
Add documentation for "xiaomi,beryllium-ebbg" device. Signed-off-by: Joel Selvaraj <joelselvaraj.oss@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909035447.36674-3-joelselvaraj.oss@gmail.com
2022-10-17arm64: dts: qcom: split beryllium dts into common dtsi and tianma dtsJoel Selvaraj
There are two panel variants of Xiaomi Poco F1. Tianma and EBBG panel. The previous beryllium dts supported the Tianma variant. In order to add support for EBBG variant, the common nodes from beryllium dts are moved to a new common dtsi and to make the variants distinguishable, sdm845-xiaomi-beryllium.dts is now named as sdm845-xiaomi-beryllium-tianma.dts. The model property is updated to distinguish between the variants. The compatibility property is moved to the tianma variant, but it is not updated to avoid any further conflict with other projects/users that might depend on it. Signed-off-by: Joel Selvaraj <joelselvaraj.oss@gmail.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909035447.36674-2-joelselvaraj.oss@gmail.com
2022-10-17arm64: dts: qcom: sm8450: add display clock controllerDmitry Baryshkov
Add device node for display clock controller on Qualcomm SM8450 platform Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-5-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: use generic node name "gpio" in SPMI PMICKrzysztof Kozlowski
GPIO controller nodes are named by convention just "gpio", not "gpios". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908080938.29199-2-krzysztof.kozlowski@linaro.org
2022-10-17arm64: dts: qcom: sc7280: assign DSI clock source parentsRajeev Nandan
Assign DSI clock source parents to DSI PHY clocks. Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662550553-28933-1-git-send-email-quic_rajeevny@quicinc.com
2022-10-17arm64: dts: qcom: sm8250: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sm8250 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-12-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sdm845: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sdm845 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Steev Klimaszewski <steev@kali.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-11-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sdm630: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sdm630 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-10-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sdm660: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sdm660 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-9-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sc7280: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sc7280 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-8-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sc7180: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the sc7180 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-7-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: msm8996: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the msm8996 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-6-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: msm8916: Drop redundant phy-names from DSI controllerBryan O'Donoghue
phy-names has been marked deprecated. Remove it from the msm8916 DSI controller block. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220907000105.786265-5-bryan.odonoghue@linaro.org
2022-10-17arm64: dts: qcom: sc7280: Update SNPS Phy params for SC7280 IDP deviceKrishna Kurapati
Overriding the SNPS Phy tuning parameters for SC7280 IDP device. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662480933-12326-4-git-send-email-quic_kriskura@quicinc.com
2022-10-17arm64: dts: qcom: sc7180: Configure USB as wakeup sourceMatthias Kaehlcke
The dwc3 USB controller of the sc7180 supports USB remote wakeup, configure it as a wakeup source. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901102946.v2.1.I347ea409ee3134bd32a29e33fecd1a6ef32085a0@changeid
2022-10-17arm64: dts: qcom: sm8450: Add description of camera control interfacesVladimir Zapolskiy
Add description of two CCI controllers found on QCOM SM8450. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901073504.3077363-1-vladimir.zapolskiy@linaro.org
2022-10-17arm64: dts: qcom: Add sc7180-pazquel360Yunlong Jia
Create first version device tree for pazquel360 pazquel360 is convertible and the pazquel it is based on is clamshell. sku 20 for lte & wifi sku 21 for wifi only sku 22 for lte w/o esim & wifi Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901024827.v3.2.Iea2d2918adfff2825b87d428b5732717425c196f@changeid
2022-10-17dt-bindings: arm: qcom: Document additional skus for sc7180 pazquel360Yunlong Jia
pazquel360 is an extension project based on pazquel. We create 3 sku on pazquel360: sku 20 for LTE with physical SIM _and_ eSIM and WiFi sku 21 for WiFi only sku 22 for LTE with only a physical SIM Both sku20 and sku22 are LTE SKUs. One has the eSIM stuffed and one doesn't. There is a single shared device tree for the two. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220901024827.v3.1.I3aa360986c0e7377ea5e96c116f014ff1ab8c968@changeid
2022-10-17arm64: dts: qcom: sdm845: add displayport nodeDmitry Baryshkov
Add displayport controller device node, describing DisplayPort hardware block on SDM845. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810035424.2796777-3-bjorn.andersson@linaro.org
2022-10-17arm64: dts: qcom: sdm845: switch usb_1 phy to use combo usb+dp phyDmitry Baryshkov
Change sdm845's usb_1_qmpphy to use combo usb+dp phy bindings, rather than just usb phy. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220810035424.2796777-2-bjorn.andersson@linaro.org
2022-10-17arm64: dts: qcom: msm8916: Drop MSS fallback compatibleStephan Gerhold
MSM8916 was originally using the "qcom,q6v5-pil" compatible for the MSS remoteproc. Later it was decided to use SoC-specific compatibles instead, so "qcom,msm8916-mss-pil" is now the preferred compatible. Commit 60a05ed059a0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") updated the MSM8916 device tree to make use of the new compatible but still kept the old "qcom,q6v5-pil" as fallback. This is inconsistent with other SoCs and conflicts with the description in the binding documentation (which says that only one compatible should be present). Also, it has no functional advantage since older kernels could not handle this DT anyway (e.g. "power-domains" in the MSS node is only supported by kernels that also support "qcom,msm8916-mss-pil"). Make this consistent with other SoCs by using only the "qcom,msm8916-mss-pil" compatible. Fixes: 60a05ed059a0 ("arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS") Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220718140344.1831731-2-stephan.gerhold@kernkonzept.com
2022-10-17arm64: dts: qcom: correct white-space before {Krzysztof Kozlowski
Add missing space or remove redundant one before opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919163333.129989-1-krzysztof.kozlowski@linaro.org
2022-10-17arm64: dts: qcom: sm8250-edo: Add NXP PN553 NFCKonrad Dybcio
Add a node for NXP PN553 NFC, using the nxp-nci driver. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221008181714.253634-1-konrad.dybcio@somainline.org
2022-10-17arm64: dts: qcom: sdm845-cheza: fix AP suspend pin biasKrzysztof Kozlowski
There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: 79e7739f7b87 ("arm64: dts: qcom: sdm845-cheza: add initial cheza dt") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010114417.29859-3-krzysztof.kozlowski@linaro.org
2022-10-17arm64: dts: qcom: sdm845-db845c: correct SPI2 pins drive strengthKrzysztof Kozlowski
The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either: 1. "pins" property and the actual configuration, 2. another set of nodes with above point. The qup_spi2_default pin configuration uses alreaady the second method with a "pinmux" child, so configure drive-strength similarly in "pinconf". Otherwise the PIN drive strength would not be applied. Fixes: 8d23a0040475 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010114417.29859-2-krzysztof.kozlowski@linaro.org
2022-10-17arm64: dts: qcom: sdm630: fix UART1 pin biasKrzysztof Kozlowski
There is no "bias-no-pull" property. Assume intentions were disabling bias. Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221010114417.29859-1-krzysztof.kozlowski@linaro.org
2022-10-17arm64: dts: qcom: ipq8074-hk01: add VQMMC supplyRobert Marko
Since now we have control over the PMP8074 PMIC providing various system voltages including L11 which provides the SDIO/eMMC I/O voltage set it as the SDHCI VQMMC supply. This allows SDHCI controller to switch to 1.8V I/O mode and support high speed modes like HS200 and HS400. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818221815.346233-5-robimarko@gmail.com
2022-10-17arm64: dts: qcom: add PMP8074 DTSIRobert Marko
PMP8074 is a companion PMIC to the Qualcomm IPQ8074 series that is controlled via SPMI. Add DTSI for it providing GPIO, regulator, RTC and VADC support. RTC is disabled by default as there is no built-in battery so it will loose time unless board vendor added a battery, so make it optional. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818221815.346233-4-robimarko@gmail.com
2022-10-17arm64: dts: qcom: ipq8074: add clocks to APCSRobert Marko
APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the A53 PLL and XO clocks in order to use APCS as the CPU clocksource for APSS scaling. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220849.339732-4-robimarko@gmail.com
2022-10-17Merge branch '20220818220628.339366-8-robimarko@gmail.com' into HEADBjorn Andersson
2022-10-17arm64: dts: qcom: ipq8074: add thermal nodesRobert Marko
IPQ8074 has a tsens v2.3.0 peripheral which monitors temperatures around the various subsystems on the die. So lets add the tsens and thermal zone nodes, passive CPU cooling will come in later patches after CPU frequency scaling is supported. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
2022-10-17arm64: dts: qcom: sc7280: Add the reset reg for lpass audiocc on SC7280Satya Priya
Add the reset register offset for clock gating. Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers") Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1663674495-25748-1-git-send-email-quic_c_skakit@quicinc.com
2022-10-17arm64: dts: qcom: sc8280xp: fix UFS PHY serdes sizeJohan Hovold
The size of the UFS PHY serdes register region is 0x1c8 and the corresponding 'reg' property should specifically not include the adjacent regions that are defined in the child node (e.g. tx and rx). Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> #Qdrive3/sa8540p-adp-ride Reviewed-by: Brian Masney <bmasney@redhat.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220915141601.18435-1-johan+linaro@kernel.org
2022-10-17arm64: dts: qcom: sc8280xp: drop broken DP PHY nodesJohan Hovold
The DP PHY register layout of the current binding do not apply to the newer USB4/USB3/DP PHY which uses a different register layout entirely. Drop the DP PHY subnodes until the binding has been updated to prevent the driver from corrupting unrelated registers. Note that this is also needed in order to not break USB with an upcoming PHY driver change that checks for overlapping register regions. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919094454.1574-5-johan+linaro@kernel.org
2022-10-17arm64: dts: qcom: sc8280xp: fix USB PHY PCS registersJohan Hovold
With the current binding, the PCS register block (0x1400) needs to include the PCS_USB registers (0x1700). Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919094454.1574-4-johan+linaro@kernel.org
2022-10-17arm64: dts: qcom: sc8280xp: fix USB1 PHY RX1 registersJohan Hovold
The USB1 SS PHY node had the RX1 register block (0x600) replaced with RX2 (0xc00). Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919094454.1574-3-johan+linaro@kernel.org
2022-10-17arm64: dts: qcom: sc8280xp: fix USB0 PHY PCS_MISC registersJohan Hovold
The USB0 SS PHY node had the PCS_MISC register block (0x1200) replaced with PCS_USB (0x1700). Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220919094454.1574-2-johan+linaro@kernel.org
2022-10-17arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phyBrian Masney
The first UFS host controller fails to start on the SA8540P automotive board (QDrive3) due to the following errors: ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 ufshcd-qcom 1d84000.ufs: ufshcd_query_flag: Sending flag query for idn 18 failed, err = 253 ufshcd-qcom 1d84000.ufs: ufshcd_query_flag_retry: query attribute, opcode 5, idn 18, failed with error 253 after 3 retries The system eventually fails to boot with the warning: gcc_ufs_phy_axi_clk status stuck at 'off' This issue can be worked around by adding clk_ignore_unused to the kernel command line since the system firmware sets up this clock for us. Let's fix this issue by updating the ref clock on ufs_mem_phy. Note that the downstream MSM 5.4 sources list this as ref_clk_parent. With this patch, the SA8540P is able to be booted without clk_ignore_unused. Signed-off-by: Brian Masney <bmasney@redhat.com> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221006145529.755521-1-bmasney@redhat.com
2022-10-17arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clockJohan Hovold
The GCC_UFS_REF_CLKREF_CLK must be enabled or the second UFS controller fails to enumerate on sa8295p-adp. Note that the vendor kernel enables both GCC_UFS_REF_CLKREF_CLK and GCC_UFS_1_CARD_CLKREF_CLK and it is possible that the former should be modelled as a parent of the latter. The clock driver also has a GCC_UFS_CARD_CLKREF_CLK clock which the firmware appears to enable on the ADP. The usual lack of documentation for Qualcomm SoCs makes this a highly annoying guessing game, but as the second controller works on the ADP without either card reference clock enabled, only enable GCC_UFS_REF_CLKREF_CLK for now. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221005143305.388-1-johan+linaro@kernel.org
2022-10-17arm64: dts: qcom: msm8996pro: expand Adreno OPP tableDmitry Baryshkov
There are minor differeces between msm8996 and msm8996pro in terms of GPU frequencies support. For example msm8996pro supports 652.8 MHz frequency for the Adreno. Reclect these differences in msm8996pro.dtsi. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-8-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: msm8996: fix GPU OPP tableDmitry Baryshkov
Fix Adreno OPP table according to the msm-3.18. Enable 624 MHz for the speed bin 3 and 560 MHz for bins 2 and 3. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-7-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: msm8996: add support for speed bin 3Dmitry Baryshkov
Add support for msm8996, speed bin 3. It supports full range of frequencies on the power cluster, but is limited to 1.8 GHz on performance cluster. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-6-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: msm8996: fix supported-hw in cpufreq OPP tablesDmitry Baryshkov
Adjust MSM8996 cpufreq tables according to tables in msm-3.18. Some of the frequencies are not supported on speed bins other than 0. Also other speed bins support intermediate topmost frequencies, not supported on speed bin 0. Implement all these differencies. Fixes: 90173a954a22 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-5-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: msm8996-xiaomi-scorpio, natrium: Use MSM8996 ProYassine Oudjana
The Xiaomi Mi Note 2 has the MSM8996 Pro SoC. Rename the dts to match, include msm8996pro.dtsi, and add the qcom,msm8996pro compatible. To do that, the msm8996.dtsi include in msm8996-xiaomi-common has to be moved to msm8996-xiaomi-gemini, the only device that needs it included after this change. Since MSM8996Pro is largely compatible with MSM8996, keep old compatible too rather than insiting on qcom,msm8996pro only. This allows the code that doesn't yet know about msm8996pro to continue supporting these devices. [DB: Dropped msm-id changes.] Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> [DB: Applied the same change to Xiaomi Mi 5s Plus (natrium).] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-4-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: msm8996: Add MSM8996 Pro supportYassine Oudjana
Qualcomm MSM8996 Pro is a variant of MSM8996 with higher frequencies supported both on CPU and GPU. There are other minor hardware differencies in the CPU and GPU regulators and bus fabrics. However this results in significant differences between 8996 and 8996 Pro CPU OPP tables. Judging from msm-3.18 there are only few common frequencies supported by both msm8996 and msm8996pro. Rather than hacking the tables for msm8996, split msm8996pro support into a separate file. Later this would allow having additional customizations for the CBF, CPR, retulators, etc. [DB: dropped all non-CPU-OPP changes] Fixes: 90173a954a22 ("arm64: dts: qcom: msm8996: Add CPU opps") Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> [DB: Realigned supported-hw to keep compat with current cpufreq driver] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-3-dmitry.baryshkov@linaro.org
2022-10-17dt-bindings: arm: qcom: separate msm8996pro bindingsDmitry Baryshkov
Xiaomi Mi 5s Plus (natrium) and Xiaomi Mi Note 2 (scorpio) use MSM8996Pro rather than plain MSM8996. Describe this in the arm/qcom.yaml bindings. Since MSM8996Pro is largely compatible with MSM8996, keep old compatible too rather than insiting on qcom,msm8996pro only. This allows the code that doesn't yet know about msm8996pro to continue supporting these devices. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220724140421.1933004-2-dmitry.baryshkov@linaro.org
2022-10-17arm64: dts: qcom: sc7280: Include sc7280-herobrine-audio-rt5682.dtsi in ↵Judy Hsiao
herobrine-r1 Include sc7280-herobrine-audio-rt5682.dtsi in herobrine-r1 as it uses rt5682 codec. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220721083849.1571744-4-judyhsiao@chromium.org
2022-10-17arm64: dts: qcom: sc7280: Add sc7280-herobrine-audio-rt5682.dtsiJudy Hsiao
Audio dtsi for sc7280 boards that using rt5682 headset codec: 1. Add dt nodes for sound card which use I2S playback and record through rt5682s and I2S playback through max98357a. 2. Enable lpass cpu node and add pin control and dai-links. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220721083849.1571744-3-judyhsiao@chromium.org
2022-10-17arm64: dts: qcom: sc7280: herobrine: Add pinconf settings for mi2s1Judy Hsiao
1. Add drive strength property for mi2s1 on sc7280 based platforms. 2. Disable the pull-up for mi2s1 lines. Signed-off-by: Judy Hsiao <judyhsiao@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220721083849.1571744-2-judyhsiao@chromium.org
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