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2022-11-20ARM: dts: aspeed: rainier: Fix pca9551 nodesSantosh Puranik
The pca9551 compatible LED drivers are under the pca9546 mux on Rainier pass > 1. On pass 1, they are directly connected to the aspeed i2c. Signed-off-by: Santosh Puranik <santosh.puranik@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221102223554.1738642-1-joel@jms.id.au
2022-11-20ARM: dts: aspeed: p10bmc: Add occ-hwmon nodesEddie James
Add the occ-hwmon nodes in order to specify that the occ-hwmon driver should not poll the OCC during initialization. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20221101213212.643472-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed-g6: Add aliases for mdio nodesPotin Lai
Add aliases for mdio nodes so that we can use name to lookup the bus address of Aspeed SOC. For example: root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio0 /ahb/mdio@1e650000 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio1 /ahb/mdio@1e650008 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio2 /ahb/mdio@1e650010 root@bletchley:~# cat /sys/firmware/devicetree/base/aliases/mdio3 /ahb/mdio@1e650018 Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Link: https://lore.kernel.org/r/20221025055046.1704920-1-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Remove MihawkJoel Stanley
The platform has been removed from OpenBMC as it is unmaintained. Link: https://lore.kernel.org/r/20221020224420.635938-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: rainier,everest: Move reserved memory regionsAdriana Kobylak
Move the reserved regions to account for a decrease in DRAM when ECC is enabled. ECC takes 1/9th of memory. Running on HW with ECC off, u-boot prints: DRAM: already initialized, 1008 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:off) And with ECC on, u-boot prints: DRAM: already initialized, 896 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:on, ECC size:896 MiB) This implies that MCR54 is configured for ECC to be bounded at the bottom of a 16MiB VGA memory region: 1024MiB - 16MiB (VGA) = 1008MiB 1008MiB / 9 (for ECC) = 112MiB 1008MiB - 112MiB = 896MiB (available DRAM) The flash_memory region currently starts at offset 896MiB: 0xb8000000 (flash_memory offset) - 0x80000000 (base memory address) = 0x38000000 = 896MiB This is the end of the available DRAM with ECC enabled and therefore it needs to be moved. Since the flash_memory is 64MiB in size and needs to be 64MiB aligned, it can just be moved up by 64MiB and would sit right at the end of the available DRAM buffer. The ramoops region currently follows the flash_memory, but it can be moved to sit above flash_memory which would minimize the address-space fragmentation. Signed-off-by: Adriana Kobylak <anoo@us.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20220916195535.1020185-1-anoo@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: Add IBM Bonnell system BMC devicetreeEddie James
Add a devicetree for the new Bonnell system. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Jim Wright <wrightj@linux.ibm.com> Link: https://lore.kernel.org/r/20220818202422.741275-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Enable emmc and ehci1Potin Lai
Enable both emmc-controller and emmc nodes for storage soultion on bletchley, and enable ehci1 node as second storage plan. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220929013130.1916525-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Update and fix gpio-line-namesPotin Lai
Update new GPIOM7 line name, and fixed typo of GPION6 line name New GPIO: - GPIOM7: USB_DEBUG_PWR_BTN_N Fixed GPIO: - GPION6: LED_POSTCODE_5 --> LED_POSTCODE_6 Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220929013130.1916525-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Update fusb302 nodesPotin Lai
1. Add interrupt pin of fusb302 on each sled. 2. Add vbus-supply property in each fusb302 node. 3. Fix BMC power-role at source and data-role at host. 4. Disable PD to avoid "HARD Reset" due to incompatible PD ver. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-5-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Bind presence-sledX pins via gpio-keysPotin Lai
Bind presence-sledX pins via gpio-keys driver to monitor and export GPIO pin values on DBUS using phosphor-gpio-presence service. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-4-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Disable GPIOV2 pull-downPotin Lai
The external pull-up cannot drive GPIOV2, so disable GPIOV2 internal pull-down resistor by the request form HW team. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-3-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-20ARM: dts: aspeed: bletchley: Change LED sys_log_id to active lowPotin Lai
change LED sys_log_id to active low base on DVT schematic. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Patrick Williams <patrick@stwcx.xyz> Link: https://lore.kernel.org/r/20220613095150.21917-2-potin.lai.pt@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-11-19arm64: dts: freescale: Rename DTB overlay source files from .dts to .dtsoAndrew Davis
DTB Overlays (.dtbo) can now be built from source files with the extension (.dtso). This makes it clear what is the content of the files and differentiates them from base DTB source files. Convert the DTB overlay source files in the arm64/freescale directory. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19Merge remote-tracking branch 'robh/dt/dtbo-rename' into imx/dt64Shawn Guo
2022-11-19arm64: dts: imx8mm-evk: add vcc supply for pca6416Adrian Alonso
pca6146 requires vcc-supply to work on i.MX8MM-EVK board. Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulatorHaibo Chen
Some SD Card controller and power circuitry has increased capacitance, so the usual toggling of regulator to power the card off and on is insufficient. According to SD spec, for sd card power reset operation, the sd card supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise, next time power back the sd card supply voltage to 3.3v, sd card can't support SD3.0 mode again. This patch add the off-on-delay-us, make sure the sd power reset behavior is align with the specification. Without this patch, when do quick system suspend/resume test, some sd card can't work at SD3.0 mode after system resume back. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mn-evk: enable uart1Peng Fan
Enable uart1 for BT usage Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart could only support max 1.5M buadrate if using OSC_24M as clock source. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mn-evk: add i2c gpio recovery settingsPeng Fan
Add I2C gpio recovery iomuxc settings Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mn-evk: set off-on-delay-us in regulatorPeng Fan
Some SD Card controller and power circuitry has increased capacitance, so the usual toggling of regulator to power the card off and on is insufficient. According to SD spec, for sd card power reset operation, the sd card supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise, next time power back the sd card supply voltage to 3.3v, sd card can't support SD3.0 mode again. This patch add the off-on-delay-us, make sure the sd power reset behavior is align with the specification. Without this patch, when do quick system suspend/resume test, some sd card can't work at SD3.0 mode after system resume back. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mn-evk: update vdd_soc dvs voltagePeng Fan
Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2. BUCK2 is for A53, which is handled by DVFS, so no need dvs property. nxp,dvs-run-voltage is not needed, since bootloader must configure voltage to make system boot well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mp-evk: enable I2C2 nodePeng Fan
Enable I2C node for i.MX8MP-EVK Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evkHan Xu
enable fspi nor on imx8mp evk dts Reviewed-by: Frank Li <frank.li@nxp.com> Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mp-evk: enable uart1/3 portsPeng Fan
Enable uart1/3 ports for evk board. Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart could only support max 1.5M buadrate if using OSC_24M as clock source. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM64: dts: imx8mp-evk: add pwm supportClark Wang
Enable pwm1/2/4 support. Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM pwm4 on pin SAI5_RXFS for J21-32 Acked-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mp: add mlmix power domainPeng Fan
Add mlmix power domain Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19ARM: dts: colibri-imx6ull: Enable dual-role switchingPhilippe Schenker
The Colibri standard provides a GPIO called USBC_DET to switch from USB Host to USB Device and back. Make use of this GPIO by adding it with usb-connector framework. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-19arm64: dts: imx8mq: fix dtschema warning for imx7-csiMartin Kepplinger
According to dtschema for the csi bridge, compatible is an enum and only one must be used. Fixing this removes the following warning: compatible: 'oneOf' conditional failed, one must be fixed Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-11-18kbuild: Cleanup DT Overlay intermediate files as appropriateAndrew Davis
%.dtbo.o and %.dtbo.S files are used to build-in DT Overlay. They should should not be removed by Make or the kernel will be needlessly rebuilt. These should be removed by "clean" and ignored by git like other intermediate files. Reported-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Andrew Davis <afd@ti.com> Fixes: 941214a512d8 ("kbuild: Allow DTB overlays to built into .dtbo.S files") Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Masahiro Yamada <masahiroy@kernel.org> Link: https://lore.kernel.org/r/20221114205939.27994-1-afd@ti.com Signed-off-by: Rob Herring <robh@kernel.org>
2022-11-18arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc nodeDinh Nguyen
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc nodeDinh Nguyen
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: remove "clk-phase" in sdmmc_clkDinh Nguyen
Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm: dts: socfpga: align mmc node names with dtschemaDinh Nguyen
dwmmc0@ff704000: $nodename:0: 'dwmmc0@ff704000' does not match '^mmc(@.*)?$' Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-11-18arm64: dts: renesas: spider-ethernet: Enable Ethernet Switch and SERDESYoshihiro Shimoda
Enable Ethernet Switch and SERDES for R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221118120953.1186392-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-18arm64: dts: renesas: r8a779f0: Add Ethernet Switch and SERDES nodesYoshihiro Shimoda
Add Ethernet Switch and SERDES nodes into R-Car S4-8 (r8a779f0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221118120953.1186392-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-18ARM: tegra: Remove duplicate pin entry in pinmuxThierry Reding
For Tegra30 Pegatron Chagall, the sdmmc3_dat3_pb5 pin was defined multiple times, leading to a DT validation error. Remove the duplicate entry. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Remove unused interrupt-parent propertiesThierry Reding
Some boards are using the interrupt-parent property to point at the GPIO controller since it handles the interrupts for the GPIO keys. However, a node needs an interrupts property for interrupt-parent to be meaningful, which these boards don't have. gpio-keys in these cases will directly use the GPIO lines specified in the key definitions and rely on the implicit conversion of those GPIOs to interrupts by the operating system, so explicit specification of the interrupts is not required. Remove the unnecessary interrupt-parent properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fix nvidia,io-reset propertiesThierry Reding
Rename the unknown nvidia,ioreset property to nvidia,io-reset, as specified in the DT bindings and supported by the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Add missing power-supply for panelsThierry Reding
Tegra124 Nyan and Venice 2 boards were missing the required power-supply property in their display panel device tree nodes. Add these properties to fix validation errors. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Fixup pinmux node namesThierry Reding
Pinmux node names should have a pinmux- prefix and not use underscores. Fix up some cases that didn't follow those rules. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-18ARM: tegra: Use correct compatible string for ASUS TF101 panelThierry Reding
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-17riscv: dts: renesas: rzfive-smarc: Enable CANFD/I2CLad Prabhakar
Enable CANFD and I2C on RZ/Five SMARC EVK. Note, these blocks are enabled in RZ/G2UL SMARC EVK DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC EVK DTSI enables them here too as we include [0] in RZ/Five SMARC EVK DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal ↵Lad Prabhakar
Zones/TSU Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM: - ADC - OPP - Thermal Zones - TSU Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them here too as we include [0] in RZ/Five SMARC SoM DTSI. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: renesas: r9a09g011: Add system controller nodeBiju Das
Add system controller node to RZ/V2M SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221116102140.852889-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-17arm64: dts: renesas: r8a779g0: Add CA76 operating pointsGeert Uytterhoeven
Add operating points for running the Cortex-A76 CPU cores on R-Car V4H at various speeds, up to the Normal (1.7 GHz) performance mode. Based on a patch in the BSP by Tho Vu. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8afb32f5dc123ebf2b941703483152ff0992191d.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add CPU core clocksGeert Uytterhoeven
Describe the clocks for the four Cortex-A76 CPU cores. CA76 Sub-Systems 0/1 (both clusters / all CPU cores) are clocked by Z0φ. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/aa6e9ae21e451ebd40d54d986bd0296571128d5b.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add CPUIdle supportGeert Uytterhoeven
Support CPUIdle for ARM Cortex-A76 on R-Car V4H. Based on patches in the BSP by Tho Vu and Vincent Bryce. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/f6d4076983eb45cf23595a045747f28cbdcdf4e6.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU coresGeert Uytterhoeven
Complete the description of the Cortex-A76 CPU cores and L3 cache controllers on the Renesas R-Car V4H (R8A779G0) SoC, including CPU topology and PSCI support for enabling CPU cores. R-Car V4H has 4 Cortex-A76 cores, grouped in 2 clusters. Based on a patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/ccb55458bd87f8ba70d28c61bcc254f22184824c.1668429870.git.geert+renesas@glider.be
2022-11-17arm64: dts: renesas: r8a779g0: Add L3 cache controllerGeert Uytterhoeven
Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
2022-11-17riscv: dts: microchip: remove unused pcie clocksConor Dooley
The PCIe root port in the designs that ship with the PolarBerry and M100PFSEVP are connected via one, not two Fabric Interface Controllers (FIC). The one at 0x20_0000_0000 is fic0, so remove the fic1 clocks from the dt node. The same clock provides both, so this is harmless but inaccurate. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-11-17riscv: dts: microchip: remove pcie node from the sev kitConor Dooley
The SEV kit reference design does not hook up the PCIe root port to the core complex including it is misleading. The entry is a re-use mistake - I was not aware of this when I moved the PCIe node out of mpfs.dtsi so that individual bistreams could connect it to different fics etc. The node is disabled, so there should be no functional change here. Fixes: 978a17d1a688 ("riscv: dts: microchip: add sevkit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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