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2024-09-03arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IPNiklas Söderlund
To make it easier to support new R-Car Gen4 SoCs add a family fallback compatible similar to what was done for VIN on R-Car Gen4. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V4H for DTS checks if they are not added. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240826144352.3026980-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03arm64: dts: renesas: r8a779h0: Add family fallback for VIN IPNiklas Söderlund
The usage of the R-Car V4M VIN bindings where merged before the bindings where approved. At that time the family fallback compatible was not part of the bindings, add it. Fixes: 2bb78d9fb7c9 ("arm64: dts: renesas: r8a779h0: Add video capture nodes") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/20240704161620.1425409-7-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03arm64: dts: renesas: r8a779a0: Add family fallback for VIN IPNiklas Söderlund
To make it easier to support new R-Car Gen4 SoCs a family fallback compatible similar to what is used for R-Car Gen2 has been added to the VIN bindings. Add this fallback to the R-Car V3U DTSI. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V3U for DTS checks if they are not added. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/20240704161620.1425409-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03arm64: dts: renesas: r8a779g0: Add family fallback for VIN IPNiklas Söderlund
To make it easier to support new R-Car Gen4 SoCs a family fallback compatible similar to what is used for R-Car Gen2 has been added to the VIN bindings. Add this fallback to the R-Car V4H DTSI. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V4H for DTS checks if they are not added. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/20240704161620.1425409-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03dt-bindings: arm: fsl: drop usage of VAR-SOM-MX8MM SoM compatible aloneKrzysztof Kozlowski
The Variscite VAR-SOM-MX8MM System-on-Module cannot be used alone without motherboard, so drop the usage of its compatible alone. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-09-02arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdogLad Prabhakar
Enable WDT1 watchdog on RZ/V2H EVK platform. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHILad Prabhakar
Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2 connector) on the RZ/V2H EVK platform. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodesLad Prabhakar
Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodesLad Prabhakar
Add SDHI0-SDHI2 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodesLad Prabhakar
Add RIIC0-RIIC8 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodesLad Prabhakar
Add OSTM0-OSTM7 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: Add initial DTS for RZ/V2H EVK boardLad Prabhakar
Add initial DTS for RZ/V2H EVK board (based on R9A09G057H44), adding the below support: - Memory - Clock inputs - PINCTRL - SCIF Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoCLad Prabhakar
Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are the list of blocks added: - EXT CLKs - 4X CA55 - SCIF - PFC - CPG - SYS - GIC - ARMv8 Timer Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02Merge tag 'renesas-r9a09g057-dt-binding-defs-tag' into renesas-dts-for-v6.12Geert Uytterhoeven
Renesas RZ/V2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/V2H (R9A09G057) SoC, shared by driver and DT source files.
2024-09-02dt-bindings: soc: renesas: Document RZ/V2H EVK boardLad Prabhakar
Add "renesas,rzv2h-evk" which targets the Renesas RZ/V2H ("R9A09G057") EVK board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPGLad Prabhakar
Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatiblesThomas Bonnefille
Document the compatible strings for the Sipeed LicheeRV Nano B board which uses the SOPHGO SG2002 SoC. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/r/20240711-sg2002-v4-2-d97ec2367095@bootlin.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02dt-bindings: interrupt-controller: Add SOPHGO SG2002 plicThomas Bonnefille
Add compatible string for SOPHGO SG2002 Platform-Level Interruter Controller. Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1] Reviewed-by: Inochi Amaoto <inochiama@outlook.com> Link: https://lore.kernel.org/r/20240711-sg2002-v4-1-d97ec2367095@bootlin.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02riscv: dts: sophgo: Add mcu device for Milk-V PioneerInochi Amaoto
Add mcu device and thermal zones node for Milk-V Pioneer. Tested-by: Chen Wang <unicorn_wang@outlook.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB4953C675C28B35723E87A36BBB822@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02riscv: sophgo: dts: add gpio controllers for SG2042 SoCChen Wang
Add support for the GPIO controller of Sophgo SG2042. SG2042 uses IP from Synopsys DesignWare APB GPIO and has three GPIO controllers. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20240819080851.1954691-1-unicornxw@gmail.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-09-02riscv: sophgo: dts: add mmc controllers for SG2042 SoCChen Wang
SG2042 has two MMC controller, one for emmc, another for sd-card. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/03ac9ec9c23bbe4c3b30271e76537bdbe5638665.1722847198.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
2024-09-02riscv: dts: sophgo: Add i2c device support for sg2042Inochi Amaoto
The i2c ip of sg2042 is a standard Synopsys i2c ip, which is already supported by the mainline kernel. Add i2c device node for sg2042. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB49530E59974AF0FCA4FAB6DBBBB72@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02riscv: dts: sophgo: Use common "interrupt-parent" for all peripherals for sg2042Inochi Amaoto
As all peripherals of sg2042 share the same "interrupt-parent", there is no need to use peripherals specific "interrupt-parent". Define "interrupt-parent" in the SoC level. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Tested-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB49531F6DFD2F116207C1397DBBB72@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02riscv: dts: sophgo: Add sdhci0 configuration for Huashan PiInochi Amaoto
Add configuration for sdhci0 for Huashan Pi to support sd card. Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/IA1PR20MB49538AC83C5DB314D10F7186BBA92@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02riscv: dts: sophgo: cv18xx: add DMA controllerInochi Amaoto
Add DMA controller dt node for CV18XX/SG200x. Link: https://lore.kernel.org/r/IA1PR20MB4953BD73E12B8A1CDBD9E1A3BB042@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2024-09-02dt-bindings: arm: fsl: rename gw7905 to gw75xxTim Harvey
The GW7905 was renamed to GW7500 before production release. While we typically do not change compatibles, the GW7905 was never released before its product name was changed to a GW7500. The use the the 'xx' wildcard is to denote the fact that this device-tree can support range of board models from GW7500 to GW7599 as has been done historically with the Gateworks baseboards to support various build customizatoins based on the same PCB. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-09-02ARM: dts: imx6qdl-mba6b: remove doubled entry for I2C1 pinmuxMarkus Niebel
Since the muxing is described already in imx6qdl-tqma6 can be reused by this variant. No functional change. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-09-02ARM: dts: imx6qdl-mba6: improve compatible for LM75 temp sensorMarkus Niebel
Use national,lm75a to specify exact variant used. This should cause no functional changes. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-09-02ARM: dts: imx6qdl-tqma6: improve compatible for LM75 temp sensorMarkus Niebel
Use national,lm75a to specify exact variant used. This should cause no functional changes. While at it change node name to 'temperature-sensor@48' to describe the function of the IC. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-09-02ARM: dts: imx6qdl-tqma6: move i2c3 pinmux to imx6qdl-tqma6bMarkus Niebel
Move the pinmux entries to the variant where they are actual used. No functional changes. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2024-09-01arm64: dts: ti: k3-j722s-evm: Enable Inter-Processor CommunicationApurva Nandan
The K3 J722S-EVM platform is based on the J722S SoC which has one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. The Inter-Processor communication between the A53 cores and these R5F and DSP remote cores is achieved through shared memory and Mailboxes. Thus, add the memory carveouts and enable the mailbox clusters required for communication. Also, The remoteproc firmware like of R5F and DSPs in the MAIN voltage domain use timers. Therefore, change the status of the timer nodes to "reserved" to avoid any clash during booting of remotecores. Usage is described as below: +===================+=============+ | Remoteproc Node | Timer Node | +===================+=============+ | main_r5fss0_core0 | main_timer0 | +-------------------+-------------+ | c7x_0 | main_timer1 | +-------------------+-------------+ | c7x_1 | main_timer2 | +-------------------+-------------+ Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Link: https://lore.kernel.org/r/20240830161742.925145-3-b-padhi@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-j722s-main: Add R5F and C7x remote processor nodesApurva Nandan
The K3 J722S SoCs have one single-core Arm Cortex-R5F processor in each of the WAKEUP, MCU and MAIN voltage domain, and two C71x DSP subsystems in MAIN voltage domain. Add the DT nodes to support Inter-Processor Communication. Signed-off-by: Apurva Nandan <a-nandan@ti.com> [ refactoring changes to k3-j722s-main.dtsi ] Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20240830161742.925145-2-b-padhi@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am68-sk-som: Update Partition info for OSPI FlashPrasanth Babu Mantena
Commit 73f1f26e2e4c ("arm64: dts: ti: k3-am68-sk-som: Add support for OSPI flash") introduced the flash node with discontinuous partitions. Updating the partition offset to be continuous from the previous partition to maintain linearity. Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Link: https://lore.kernel.org/r/20240828060830.555733-1-p-mantena@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: Add k3-am67a-beagley-aiRobert Nelson
BeagleBoard.org BeagleY-AI is an easy to use, affordable open source hardware single board computer based on the Texas Instruments AM67A, which features a quad-core 64-bit Arm CPU subsystem, 2 general-purpose digital-signal-processors (DSP) and matrix-multiply-accelerators (MMA), GPU, vision and deep learning accelerators, and multiple Arm Cortex-R5 cores for low-power, low-latency GPIO control. https://beagley-ai.org/ https://openbeagle.org/beagley-ai/beagley-ai Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Link: https://lore.kernel.org/r/20240829213929.48540-2-robertcnelson@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01dt-bindings: arm: ti: Add BeagleY-AIRobert Nelson
This board is based on ti,j722s family using the am67a variation. https://beagley-ai.org/ https://openbeagle.org/beagley-ai/beagley-ai Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Jared McArthur <j-mcarthur@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240829213929.48540-1-robertcnelson@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: iot2050: Declare Ethernet PHY ledsDiogo Ivo
Each Ethernet PHY on IOT2050 platforms drives 3 LEDs whose triggers can be configured to signal link properties such as connection status or speed. Declare the LEDs, exposing their trigger controls to userspace. Signed-off-by: Diogo Ivo <diogo.ivo@siemens.com> Link: https://lore.kernel.org/r/20240829-ivo-iot2050_leds-v1-1-792a512b2178@siemens.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am65: Add ESM nodesJudith Mendez
Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 9.4 Interrupt Sources. There are no ESM0_ESM_INT* events routed to MCU ESM, so it is not possible to reset the CPU using watchdog and ESM0 configuration. However add ESM instances for device completion. Add comments to describe what interrupt sources are routed to ESM modules. [0] http://www.ti.com/lit/pdf/spruid7 Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20240815204833.452132-7-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am64: Add more ESM interrupt sourcesJudith Mendez
Add ESM interrupt sources for rti as per TRM [0] in 9.4 Interrupt Sources. [0] https://www.ti.com/lit/pdf/spruim2 Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20240815204833.452132-6-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am62a: Add ESM nodesJudith Mendez
Add Error Signaling Module (ESM) instances in MCU and MAIN domains, set ESM interrupt sources for rti as per TRM [0] 10.4 Interrupt Sources. Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/pdf/spruj16 Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20240815204833.452132-2-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am62: Add comments to ESM nodesJudith Mendez
Add comments to describe what interrupt sources are routed to ESM modules. There is no functional change. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20240815204833.452132-5-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am62p: Fix ESM interrupt sourcesJudith Mendez
Fix interrupt sources for rti routed to the ESM0 as per [0], in 10.4 Interrupt Sources Add comments to describe what interrupt sources are routed to ESM modules. [0] https://www.ti.com/lit/pdf/spruj83 Fixes: b5080c7c1f7e ("arm64: dts: ti: k3-am62p: Add nodes for more IPs") Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20240815204833.452132-3-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESMSanthosh Kumar K
Remove 'reserved' status for MCU ESM node. Watchdog reset is propagated through ESM0 to MCU ESM to reset the CPU, so enable MCU ESM to reset the CPU with watchdog timeout. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20240815204833.452132-4-jm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-j721s2-evm-gesi-exp-board: Rename gpio-hog node nameNishanth Menon
Fix the gpio hog node name to p15-hog to match up with gpio-hog convention. This fixes dtbs_check warning: p15: $nodename:0: 'p15' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$' Acked-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20240830102822.3970269-1-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am642-evm-nand: Rename pinctrl node and gpio-hog namesNishanth Menon
Rename the pin mux and gpio-hog node names to match up with binding rules. This fixes dtbs_check warnings: 'gpmc0-pins-default' does not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+' 'gpio0-36' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$' While at it, change the phandle name to be consistent with the pinctrl naming. Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20240830113137.3986091-1-nm@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am654-idk: Fix dtbs_check warning in ICSSG dmasMD Danish Anwar
ICSSG doesn't use mgmnt rsp dmas. But these are added in the dmas for icssg1-eth and icssg0-eth node. These mgmnt rsp dmas result in below dtbs_check warnings. /workdir/arch/arm64/boot/dts/ti/k3-am654-idk.dtb: icssg1-eth: dmas: [[39, 49664], [39, 49665], [39, 49666], [39, 49667], [39, 49668], [39, 49669], [39, 49670], [39, 49671], [39, 16896], [39, 16897], [39, 16898], [39, 16899]] is too long from schema $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml# /workdir/arch/arm64/boot/dts/ti/k3-am654-idk.dtb: icssg0-eth: dmas: [[39, 49408], [39, 49409], [39, 49410], [39, 49411], [39, 49412], [39, 49413], [39, 49414], [39, 49415], [39, 16640], [39, 16641], [39, 16642], [39, 16643]] is too long from schema $id: http://devicetree.org/schemas/net/ti,icssg-prueth.yaml# Fix these warnings by removing mgmnt rsp dmas from icssg1-eth and icssg0-eth nodes. Fixes: a4d5bc3214eb ("arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports") Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240830111000.232028-1-danishanwar@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-j784s4: Include entire FSS region in rangesAndrew Davis
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although not used currently by the Linux FSS driver, these regions belong to the FSS and should be included in the ranges mapping. While here, a couple of these numbers had missing zeros which was hidden by odd alignments, fix both these issues. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Santhosh Kumar K <s-k6@ti.com> Link: https://lore.kernel.org/r/20240828172956.26630-5-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-j721s2: Include entire FSS region in rangesAndrew Davis
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although not used currently by the Linux FSS driver, these regions belong to the FSS and should be included in the ranges mapping. While here, a couple of these numbers had missing zeros which was hidden by odd alignments, fix both these issues. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Santhosh Kumar K <s-k6@ti.com> Link: https://lore.kernel.org/r/20240828172956.26630-4-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-j721e: Include entire FSS region in rangesAndrew Davis
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although not used currently by the Linux FSS driver, these regions belong to the FSS and should be included in the ranges mapping. While here, a couple of these numbers had missing zeros which was hidden by odd alignments, fix both these issues. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Santhosh Kumar K <s-k6@ti.com> Link: https://lore.kernel.org/r/20240828172956.26630-3-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am65: Include entire FSS region in rangesAndrew Davis
Add FSS regions at 0x50000000, 0x400000000, and 0x600000000. Although not used currently by the Linux FSS driver, these regions belong to the FSS and should be included in the ranges mapping. While here, a couple of these numbers had missing zeros which was hidden by odd alignments, fix both these issues. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Santhosh Kumar K <s-k6@ti.com> Link: https://lore.kernel.org/r/20240828172956.26630-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-09-01arm64: dts: ti: k3-am64: add USB fallback compatible to J721EThéo Lebrun
USB on AM64 is the same peripheral as on J721E. It has a specific compatible for potential integration details. Express this relationship, matching what the dt-bindings indicate. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20240726-s2r-cdns-v5-12-8664bfb032ac@bootlin.com Signed-off-by: Nishanth Menon <nm@ti.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 02:04:16 +0000