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2024-04-21arm64: dts: qcom: msm8996: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-14-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sc8180x: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-13-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: qcs404: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-12-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sc7280: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-11-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: msm8998: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-10-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sc8280xp: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, let's remove the bridge properties from board dts as they are now redundant. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-9-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sa8775p: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-8-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8650: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-7-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8550: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-6-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8450: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-5-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8350: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8150: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-3-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sdm845: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-2-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8250: Add PCIe bridge nodeManivannan Sadhasivam
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-1-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sdm845-db845c: make pcie0_3p3v_dual always-onCaleb Connolly
This regulator is responsible not just for the PCIe 3.3v rail, but also for 5v VBUS on the left USB port. There is currently no way to correctly model this dependency on the USB controller, as a result when the PCIe driver is not available (for example when in the initramfs) USB is non-functional. Until support is added for modelling this property (likely by referencing it as a supply under a usb-connector node), let's just make it always on. We don't target any power constrained usecases and this regulator is required for USB to function correctly. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Suggested-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240320122515.3243711-1-caleb.connolly@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8450: Update SNPS Phy parameters for QRD platformUdipto Goswami
Update SNPS Phy tuning parameters for sm8450 QRD platform to fix electrical compliance failures. Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321062834.21510-1-quic_ugoswami@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sc8280xp: Fill in EAS propertiesKonrad Dybcio
Replace the bogus capacity-dmips-mhz values and add the measured dynamic-power-coefficient values. The power numbers were measured by matters much more precise than the laggy and cache-y pmic_glink battery data, though the reported values were only accurate to 10mA. But that shouldn't be an issue, especially for the fat and power-hungry X1Cs and given that *each SoC unit* has somewhat different frequency-voltage maps. X1C cluster: 940 kHz, 596 mV, 434 mW, 663 Cx 1056 kHz, 612 mV, 463 mW, 565 Cx 1171 kHz, 628 mV, 502 mW, 574 Cx 1286 kHz, 644 mV, 534 mW, 540 Cx 1401 kHz, 660 mV, 580 mW, 550 Cx 1516 kHz, 688 mV, 630 mW, 529 Cx 1632 kHz, 712 mV, 690 mW, 533 Cx 1747 kHz, 728 mV, 722 mW, 503 Cx 1862 kHz, 752 mV, 787 mW, 504 Cx 1977 kHz, 776 mV, 855 mW, 503 Cx 2073 kHz, 792 mV, 913 mW, 504 Cx 2169 kHz, 812 mV, 989 mW, 514 Cx 2284 kHz, 856 mV, 1250 mW, 611 Cx 2400 kHz, 900 mV, 1441 mW, 626 Cx 2496 kHz, 932 mV, 1600 mW, 636 Cx 2592 kHz, 964 mV, 1790 mW, 653 Cx 2688 kHz, 1000 mV, 2020 mW, 673 Cx 2803 kHz, 1040 mV, 2292 mW, 687 Cx 2899 kHz, 1076 mV, 2572 mW, 706 Cx 2995 kHz, 1108 mV, 2850 mW, 721 Cx A78C cluster: 403 kHz, 576 mV, 180 mW, 584 Cx 499 kHz, 576 mV, 200 mW, 605 Cx 595 kHz, 576 mV, 220 mW, 612 Cx 691 kHz, 576 mV, 230 mW, 541 Cx 806 kHz, 600 mV, 250 mW, 471 Cx 902 kHz, 620 mV, 270 mW, 444 Cx 1017 kHz, 640 mV, 290 mW, 409 Cx 1113 kHz, 652 mV, 310 mW, 401 Cx 1209 kHz, 668 mV, 320 mW, 363 Cx 1324 kHz, 700 mV, 490 mW, 600 Cx 1440 kHz, 724 mV, 523 mW, 554 Cx 1555 kHz, 800 mV, 660 mW, 558 Cx 1670 kHz, 800 mV, 780 mW, 639 Cx 1785 kHz, 804 mV, 910 mW, 711 Cx 1881 kHz, 824 mV, 941 mW, 663 Cx 1996 kHz, 856 mV, 980 mW, 601 Cx 2112 kHz, 880 mV, 1020 mW, 559 Cx 2227 kHz, 908 mV, 1090 mW, 535 Cx 2342 kHz, 932 mV, 1230 mW, 552 Cx 2438 kHz, 956 mV, 1351 mW, 559 Cx Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240319-topic-8280_eas-v1-1-c605b4ea063d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodesLing Xu
Add three missing cDSP fastrpc compute-cb nodes for the SM8650 SoC. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Link: https://lore.kernel.org/r/20240319032816.27070-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8650-qrd: enable GPUNeil Armstrong
Add path of the GPU firmware for the SM8650-QRD board Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-2-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8650: add GPU nodesNeil Armstrong
Add GPU nodes for the SM8650 platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Jun Nie <jun.nie@linaro.org> Link: https://lore.kernel.org/r/20240318-topic-sm8650-gpu-v4-1-206eb0d31694@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: pm6150l: add Light Pulse Generator device nodeDanila Tikhonov
Add device node defining LPG/PWM block on PM6150L PMIC chip. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240306172710.59780-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: msm8916/39-samsung-a2015: Add connector for MUICRaymond Hackley
Add subnode usb_con: extcon for SM5502 / SM5504 MUIC, which will be used for RT5033 charger. Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240215122605.3817-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8250-xiaomi-elish: set pm8150b_vbus ↵Jianhua Lu
regulator-min-microamp and regulator-max-microamp Fix the dtb check warnings: sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-min-microamp' is a required property sm8250-xiaomi-elish-boe.dtb: usb-vbus-regulator@1100: 'regulator-max-microamp' is a required property Fixes: 69652787279d ("arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8150b type-c node and enable usb otg") Signed-off-by: Jianhua Lu <lujianhua000@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240323100443.2478-1-lujianhua000@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdpNeil Armstrong
The MDP/DPU device is not disabled by default, so there is not point in enabling it in the board DTS file. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240325-topic-sm8x50-upstream-leave-mdss-enabled-by-default-v1-1-f1b380132075@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sdx75: add unit address to soc nodeKrzysztof Kozlowski
Soc node has ranges, thus it must have an unit address. This fixes W=1 dtc warning: sdx75.dtsi:399.11-736.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240325102924.26820-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: sm6350: Add DisplayPort controllerLuca Weiss
Add the node for the DisplayPort controller found on the SM6350 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240329-sm6350-dp-v2-3-e46dceb32ef5@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: qcs6490-rb3gen2: Enable various remoteprocsKomal Bajaj
Enable the ADSP, CDSP and WPSS that are found on qcs6490-rb3gen2. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240417120928.32344-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-21arm64: dts: qcom: qcm6490-idp: Enable various remoteprocsKomal Bajaj
Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Link: https://lore.kernel.org/r/20240417120928.32344-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: sc8180x-lenovo-flex-5g: add USB-C orientation GPIOsDmitry Baryshkov
Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-5-658efd993987@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: add USB-C orientation GPIOsDmitry Baryshkov
Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-4-658efd993987@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: sm8450-hdk: add USB-C orientation GPIODmitry Baryshkov
Define the USB-C orientation GPIO so that the USB-C port orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-3-658efd993987@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: sm8350-hdk: add USB-C orientation GPIODmitry Baryshkov
Define the USB-C orientation GPIO so that the USB-C port orientation is known without having to resort to the altmode notifications. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-2-658efd993987@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20dt-bindings: soc: qcom: pmic-glink: allow orientation-gpiosDmitry Baryshkov
The orientation GPIOs are not limited to sm8450/sm8550/x1e8000 platforms. Allow corresponding property to be used on all Qualcom platforms. Fixes: 65682407f8f4 ("dt-bindings: soc: qcom: qcom,pmic-glink: add a gpio used to determine the Type-C port plug orientation") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240409-hdk-orientation-gpios-v2-1-658efd993987@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: qcm6490-fairphone-fp5: Add USB-C orientation GPIOLuca Weiss
Define the USB-C orientation GPIOs so that the USB-C ports orientation is known without having to resort to the altmode notifications. On PCB level this is the signal from PM7250B (pin CC_OUT) which is called USB_PHY_PS. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240411-fp5-usb-c-gpio-v1-1-78f11deb940a@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: qcm6490-idp: Name the regulatorsUmang Chheda
Without explicitly specifying names for the regulators they are named based on the DeviceTree node name. This results in multiple regulators with the same name, making it impossible to reason debug prints and regulator_summary. Signed-off-by: Umang Chheda <quic_uchheda@quicinc.com> Link: https://lore.kernel.org/r/20240412123237.2633000-1-quic_uchheda@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: sa8155p-adp: lower min volt for L13C regulatorVolodymyr Babchuk
Voltage regulator L13C is used by SD card IO interface. In order to support UHS modes, IO interface voltage needs to be set to 1.8V. This patch extends minimum voltage range of L13C regulator to allow this. Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Fixes: 0deb2624e2d0 ("arm64: dts: qcom: sa8155p-adp: Add support for uSD card") Suggested-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20240412190310.1647893-2-volodymyr_babchuk@epam.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: x1e80100-qcp: Add data-lanes and link-frequencies to DP3Abel Vesa
The data-lanes are a property of the out remote endpoint, so move them from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to mdss_dp3_out and make sure to include all frequencies. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-3-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: x1e80100-crd: Add data-lanes and link-frequencies to DP3Abel Vesa
The data-lanes are a property of the out remote endpoint, so move them from mdss_dp3 to the mdss_dp3_out. Also add the link-frequencies to mdss_dp3_out and make sure to include all frequencies. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-2-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-20arm64: dts: qcom: x1e80100: Drop the link-frequencies from mdss_dp3_inAbel Vesa
The link-frequencies belong in mdss_dp3_out. Drop them from mdss_dp3_in. Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240419-x1e80100-dts-fix-mdss-dp3-v2-1-10f4ed7a09b4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-15arm64: dts: qcom: Add SM8550 Xperia 1 VKonrad Dybcio
Add support for Sony Xperia 1 V, a.k.a PDX234. This device is a part of the SoMC SM8550 Yodo platform. This commit brings support for: * Remoteprocs (sans modem for now) * Flash LED (the notification LED is gone :((((() * SD Card * USB (*including SuperSpeed*) + PMIC_GLINK (it's funky, requires a replug with an cable flip sometimes..) * Most regulators * Part of I2C-connected peripherals (notably no touch due to a driver bug) * PCIe0 (PCIe1 is unused) Do note display via simplefb is not supported, as the display is blanked upon exiting XBL. To create a working boot image, you need to run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/sm8550-sony-xperia-\ yodo-pdx234.dtb > .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd.img \ --pagesize 4096 \ --base 0x0 \ --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 \ --tags_offset 0x100 \ --cmdline "SOME_CMDLINE" \ --dtb_offset 0x1f00000 \ --header_version 2 \ -o boot.img-sony-xperia-pdx234 Then, you need to flash it on the device and get rid of all the vendor_boot/dtbo mess: // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system \ vbmeta_system.img fastboot flash boot boot.img-sony-xperia-pdx234 fastboot erase vendor_boot fastboot erase recovery fastboot flash dtbo emptydtbo.img fastboot erase init_boot // ? I don't remember if it's necessary, sorry fastboot continue Where emptydtbo.img is a tiny file that consists of 2 bytes (all zeroes), doing a "fastboot erase" won't cut it, the bootloader will go crazy and things will fall apart when it tries to overlay random bytes from an empty partition onto a perfectly good appended DTB. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240210-topic-1v-v1-7-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-15arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherentKonrad Dybcio
In a fairly new development, Qualcomm somehow made the DWC3 block cache-coherent. Annotate that. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240210-topic-1v-v1-6-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-15arm64: dts: qcom: sm8550: Add missing DWC3 quirksKonrad Dybcio
As expected, Qualcomm DWC3 implementation come with a sizable number of quirks. Make sure to account for all of them. Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240210-topic-1v-v1-5-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-15arm64: dts: qcom: sm8550: Mark APPS SMMU as dma-coherentKonrad Dybcio
Like on earlier flagship Qualcomm SoCs, the SMMU is dma-coherent. Mark it as such. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240210-topic-1v-v1-4-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-15arm64: dts: qcom: sm8550: Mark QUPs and GPI dma-coherentKonrad Dybcio
These peripherals are DMA-coherent on 8550. Mark them as such. Interestingly enough, the I2C master hubs are not. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240210-topic-1v-v1-3-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-15dt-bindings: arm: qcom: Add Xperia 1 VKonrad Dybcio
Document the SM8550 SONY Xperia 1 V (PDX234) board. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240210-topic-1v-v1-2-fda0db38e29b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-11arm64: dts: qcom: sc7180: Fix UFS PHY clocksDanila Tikhonov
QMP PHY used in SC7180 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20240401182240.55282-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-04arm64: dts: qcom: qcs6490-rb3gen2: Enable UFSBjorn Andersson
The rb3gen2 has UFS memory, adjust the necessary supply voltage and add the controller and phy nodes to enable this. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240327-rb3gen2-ufs-v2-1-3de6b5dd78dd@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-04arm64: dts: qcom: sm8150-hdk: enable WiFI supportDmitry Baryshkov
Enable modem DSP and WiFI devices on the SM8150 HDK device. The HDK is manufactured by Lantronix, but it attributed to Qualcomm, so the calibration string uses Qualcomm as manufacturer. For reference: ath10k_snoc 18800000.wifi: qmi chip_id 0x30224 chip_family 0x4001 board_id 0x55 soc_id 0x40060000 ath10k_snoc 18800000.wifi: qmi fw_version 0x32040163 fw_build_timestamp 2019-10-08 05:42 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.3.2.0-00355-QCAHLSWMTPLZ-1 ath10k_snoc 18800000.wifi: wcn3990 hw1.0 target 0x00000008 chip_id 0x00000000 sub 0000:0000 ath10k_snoc 18800000.wifi: kconfig debug 1 debugfs 0 tracing 0 dfs 0 testmode 0 ath10k_snoc 18800000.wifi: firmware ver api 5 features wowlan,mgmt-tx-by-reference,non-bmi crc32 b3d4b790 ath10k_snoc 18800000.wifi: htt-ver 3.73 wmi-op 4 htt-op 3 cal file max-sta 32 raw 0 hwcrypto 1 ath10k_snoc 18800000.wifi: invalid MAC address; choosing random Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240403-sm8150-hdk-wifi-v1-1-8da3063829c2@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-04arm64: dts: qcom: msm8916-samsung-fortuna: Add PWM backlightSiddharth Manthan
Most of the Galaxy Grand Prime use backlight drivers controlled with PWM signal. To simplify the description, add the backlight with the necessary clk-pwm to the common dtsi. Signed-off-by: Siddharth Manthan <siddharth.manthan@gmail.com> [Stephan: Move to fortuna-common and disable on rossa-common] Signed-off-by: Stephan Gerhold <stephan@gerhold.net> [Raymond: Add the commit message] Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Link: https://lore.kernel.org/r/20240404121703.17086-3-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-04-04arm64: dts: qcom: msm8916-samsung-fortuna: Add touchscreenJoe Mason
Like msm8916-samsung-a3u-eur, the Grand Prime uses a Zinitix BT541 touchscreen. Add it together with the necessary fixed-regulator to the device tree. Signed-off-by: Joe Mason <buddyjojo06@outlook.com> [Raymond: Move to fortuna-common. Use interrupts-extended] Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240404121703.17086-2-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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