summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-02-02drm/amd/display: Revert "Fix EDID parsing after resume from suspend"Stylon Wang
This reverts commit b24bdc37d03a0478189e20a50286092840f414fa. It caused memory leak after S3 on 4K HDMI displays. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: fix calculation for the pwl backlight curveAnthony Koo
[Why] The PWL backlight curve is used by the firmware to convert between brightness and linear PWM value. Driver has a backlight LUT, but the firmware holds a PWL curve and interpolates between points. The calculations are incorrect leading to slightly off backlight values being programmed. [How] Fix the PWL backlight curve threshold/offset calculations Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Josip Pavic <Josip.Pavic@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: 3.2.120Aric Cyr
This DC update brings improvements in multiple areas. In summary, we highlight: - Fix display detection on HDMI ComboPHY - Drop SOC bounding box hookup - Fix DPCD values Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: [FW Promotion] Release 0.0.49Anthony Koo
- Add field for passing line time for a frame Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Add more Clock Sources to DCN2.1Sung Lee
[WHY] When enabling HDMI on ComboPHY, there are not enough clock sources to complete display detection. [HOW] Initialize more clock sources. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: correct some hdcp variable namingWenjing Liu
[why] In HDCP update stream config interface, some variables are named as xxx_supported, but in fact the variable indicates whether or not xxx_enabled. Correct the naming so it is less confusing to read the code. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Set power_gated to true for seamless boot pipe initLewis Huang
[Why] In seamless boot without a flip case, the flag power_gated didn't get cleared when resetting path mode because the plane_state is null. The following sequence will cause this issue: 1. OS call set mode to clone/extended 2. Reset path mode to remove edp [How] Set power gated default to true in seamless boot pipe Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: reuse current context instead of recreating oneBhawanpreet Lakha
[Why] Currently we discard the current context and recreate it. The current context is what is applied to the HW so we should be re-using this rather than creating a new context. Recreating the context can lead to mismatch between new context and the current context For example: gsl groups get changed when we create a new context this can cause issues in a multi display config (with flip immediate) because we don't align the existing gsl groups in the new and current context. If we reuse the current context the gsl group assignment stays the same. [How] Instead of discarding the current context, we instead just copy the current state and add/remove planes and streams. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Add null pointer check to is_dig_enabled funcMichael Strauss
[WHY] Safeguarding as pointer may be null in diagnostic environment Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: initialize i2c speed if not initialized in dcnxxx__resource.cBrendan Steve Leder
Some dcnxxx__resource.c do not initialize the i2c speed; this patch adds the required initialization at dc_construct(). Signed-off-by: Brendan Steve Leder <brendanSteve.Leder@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVALGeorge Shen
[Why] The translation between the DPCD value and the specified AUX_RD_INTERVAL in the DP spec do not match. [How] Update values to match the spec. Signed-off-by: George Shen <george.shen@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Drop SOC bounding box hookup in DM/DCNicholas Kazlauskas
[Why] There aren't any ASIC where we use these binaries and they aren't useful for future use since it's inconvenient to extend and maintain these structures. [How] Drop the support from DM and DC for now. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu: enable freesync for A+A configsChristian König
Some newer APUs can scanout directly from GTT, that saves us from allocating another bounce buffer in VRAM and enables freesync in such configurations. Without this patch creating a framebuffer from the imported BO will fail and userspace will fall back to a copy. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/pm: remove some useless code for vangoghXiaojian Du
This patch is to remove some useless code for vangogh. In the earlier code, vangogh can't finish all the sequence of smu late init. But now vangogh has one stable work state,so remove the useless code. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Acked-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/pm: fill in the data member of v2 gpu metrics table for vangoghXiaojian Du
This patch is to fill in the data member of v2 gpu metrics table for vangogh. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register ↵chen gong
offsets for VGH For Vangogh: The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation. The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation. Signed-off-by: chen gong <curry.gong@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu: Fix a false positive when pin non-VRAM memoryxinhui pan
Flag TTM_PL_FLAG_CONTIGUOUS is only valid for VRAM domain. So fix the false positive by checking memory type too. Suggested-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: xinhui pan <xinhui.pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu: Limit the maximum size of contiguous VRAM that can be ↵Ramesh Errabolu
encapsulated by an instance of DRM memory node [Why] Enable 1:1 mapping between VRAM of a DRM node and a scatterlist node [How] Ensure construction of DRM node to not exceed specified limit Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ramesh Errabolu <Ramesh.Errabolu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdkfd: fix null pointer panic while free buffer in kfdHuang Rui
In drm_gem_object_free, it will call funcs of drm buffer obj. So kfd_alloc should use amdgpu_gem_object_create instead of amdgpu_bo_create to initialize the funcs as amdgpu_gem_object_funcs. [ 396.231390] amdgpu: Release VA 0x7f76b4ada000 - 0x7f76b4add000 [ 396.231394] amdgpu: remove VA 0x7f76b4ada000 - 0x7f76b4add000 in entry 0000000085c24a47 [ 396.231408] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 396.231445] #PF: supervisor read access in kernel mode [ 396.231466] #PF: error_code(0x0000) - not-present page [ 396.231484] PGD 0 P4D 0 [ 396.231495] Oops: 0000 [#1] SMP NOPTI [ 396.231509] CPU: 7 PID: 1352 Comm: clinfo Tainted: G OE 5.11.0-rc2-custom #1 [ 396.231537] Hardware name: AMD Celadon-RN/Celadon-RN, BIOS WCD0401N_Weekly_20_04_0 04/01/2020 [ 396.231563] RIP: 0010:drm_gem_object_free+0xc/0x22 [drm] [ 396.231606] Code: eb ec 48 89 c3 eb e7 0f 1f 44 00 00 55 48 89 e5 48 8b bf 00 06 00 00 e8 72 0d 01 00 5d c3 0f 1f 44 00 00 48 8b 87 40 01 00 00 <48> 8b 00 48 85 c0 74 0b 55 48 89 e5 e8 54 37 7c db 5d c3 0f 0b c3 [ 396.231666] RSP: 0018:ffffb4704177fcf8 EFLAGS: 00010246 [ 396.231686] RAX: 0000000000000000 RBX: ffff993a0d0cc400 RCX: 0000000000003113 [ 396.231711] RDX: 0000000000000001 RSI: e9cda7a5d0791c6d RDI: ffff993a333a9058 [ 396.231736] RBP: ffffb4704177fdd0 R08: ffff993a03855858 R09: 0000000000000000 [ 396.231761] R10: ffff993a0d1f7158 R11: 0000000000000001 R12: 0000000000000000 [ 396.231785] R13: ffff993a0d0cc428 R14: 0000000000003000 R15: ffffb4704177fde0 [ 396.231811] FS: 00007f76b5730740(0000) GS:ffff993b275c0000(0000) knlGS:0000000000000000 [ 396.231840] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 396.231860] CR2: 0000000000000000 CR3: 000000016d2e2000 CR4: 0000000000350ee0 [ 396.231885] Call Trace: [ 396.231897] ? amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x24c/0x25f [amdgpu] [ 396.232056] ? __dynamic_dev_dbg+0xcd/0x100 [ 396.232076] kfd_ioctl_free_memory_of_gpu+0x91/0x102 [amdgpu] [ 396.232214] kfd_ioctl+0x211/0x35b [amdgpu] [ 396.232341] ? kfd_ioctl_get_queue_wave_state+0x52/0x52 [amdgpu] Fixes: 246cb7e49a70 ("drm/amdgpu: Introduce GEM object functions") Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Tested-by: Changfeng <changzhu@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu: fix the issue that retry constantly once the buffer is oversizeHuang Rui
We cannot modify initial_domain every time while the retry starts. That will cause the busy waiting that unable to switch to GTT while the vram is not enough. Fixes: f8aab60422c3 ("drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs") Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01drm/amdgpu/swsmu: use percent rather than rpm for manual fan control (v2)Alex Deucher
On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Both interfaces work properly on the boards I have. Let's try and use the percent interface instead. v2: rebase on revert Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408 Reviewed-by: Evan Quan <evan.quan@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01Revert "drm/amdgpu/swsmu: drop set_fan_speed_percent (v2)"Alex Deucher
On some boards the rpm interface apparently does not work at all leading to the fan not spinning or spinning at strange speeds. Revert this for now to fix 5.10, 5.11. The follow on patch fixes this properly for 5.12. This reverts commit 8d6e65adc25e23fabbc5293b6cd320195c708dca. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1408 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01drm/amd/display: Simplify bool conversionAbaci Team
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c:3137:35-40: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <abaci@linux.alibaba.com> Suggested-by: Yang Li <oswb@linux.alibaba.com> Signed-off-by: Abaci Team <abaci-bugfix@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01amdgpu: Add Missing Sienna Cichlid DIDOri Messinger
The purpose of this patch is to add a missing device ID for Sienna Cichlid. The missing ID "0x73A1" is now added to the "amdgpu_drv.c" file. Signed-off-by: Ori Messinger <Ori.Messinger@amd.com> Reviewed-by: Kent Russell <kent.russell@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01drm/amd/pm: correct string parsing for extra separator characters caseEvan Quan
Supplement of previous fix. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01drm/amdgpu/pm: Account for extra separator characters in sysfs interfaceMatt Coffin
Currently, the the input to the pp_od_clk_voltage sysfs interface has two adjacent separator characters, i.e. "\n\0", then we try to parse an argument out of the empty string, whereas we really should just ignore this case, and treat any number of adjacent separators as one separator for arguments. We do this here by simply skipping the argument parsing for all empy-string arguments. An example test case would be `echo 's 1 900' > pp_od_clk_voltage` (note the two spaces after the 's'. This also solves the issue where the written string ends with both a newline, and a nul-terminator, '\n\0', as is the case for `echo 's 1 900' > pp_od_clk_voltage` since the recent rebase. Got lost during code rebase/merge. No need to port this to other branches. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Matt Coffin <mcoffin13@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01Revert "Revert "drm/amdgpu: Fix NULL dereference in dpm sysfs handlers""Evan Quan
This reverts commit 2456c290a7889be492cb96092b62d16c11176f72. Got lost during code rebase/merge. No need to port this to other branches. Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-01Merge branch 'linux-5.12' of git://github.com/skeggsb/linux into drm-nextDave Airlie
Nothing too major here, I actually thought I'd sent most of these right before the new year, but that apparently got lost in the bustle: - Turing MMU fault recovery fixes - Fix mDP connectors being reported as eDP to userspace - Fixes for audio locking, and other bit-rot from DRM changes since atomic support was written - Misc other minor fixes. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Ben Skeggs <skeggsb@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv7yLfhuVbYa-4g0vxVt93OaC7Sodiz2R-TDHu-MoofEdw@mail.gmail.com
2021-01-29drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detectedImre Deak
Atm, the driver programs explicitly the default transparent link training mode (0x55) to DP_PHY_REPEATER_MODE even if no LTTPRs are detected. This conforms to the spec (3.6.6.1): "DP upstream devices that do not enable the Non-transparent mode of LTTPRs shall program the PHY_REPEATER_MODE register (DPCD Address F0003h) to 55h (default) prior to link training" however writing the default value to this DPCD register seems to cause occasional link training errors at least for a DELL WD19TB TBT dock, when no LTTPRs are detected. Writing to DP_PHY_REPEATER_MODE will also cause an unnecessary timeout on systems without any LTTPR. To fix the above two issues let's assume that setting the default mode is redundant when no LTTPRs are detected. Keep the existing behavior and program the default mode if more than 8 LTTPRs are detected or in case the read from DP_PHY_REPEATER_CNT returns an invalid value. References: https://gitlab.freedesktop.org/drm/intel/-/issues/2801 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210118183143.1145707-1-imre.deak@intel.com
2021-01-29drm/i915: Implement async flips for vlv/chvVille Syrjälä
Add support for async flips on vlv/chv. Unlike all the other platforms vlv/chv do not use the async flip bit in DSPCNTR and instead we select between async vs. sync flips based on the surface address register. The normal DSPSURF generates sync flips DSPADDR_VLV generates async flips. And as usual the interrupt bits are different from the other platforms. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-12-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-29drm/i915: Implement async flip for ilk/snbVille Syrjälä
Add support for async flips on ivb/hsw. Again no need for any workarounds and just have to deal with the interrupt bits being shuffled around a bit. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-11-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-29drm/i915: Implement async flip for ivb/hswVille Syrjälä
Add support for async flips on ivb/hsw. Unlike bdw+ we don't need any workarounds to disable async flips. Apart from that the only real difference from the bdw implementation is the location of the flip_done interrupt bits. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-10-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-29drm/i915: Implement async flips for bdwVille Syrjälä
Implement async flip support for BDW. The implementation is similar to the skl+ code. And just like skl/bxt/glk bdw also needs the disable w/a, thus we need to plumb the desired state of the async flip all the way down to i9xx_plane_ctl_crtc(). According to the spec we do need to bump the surface alignment to 256KiB for this. Async flips require an X-tiled buffer so we don't have to worry about linear. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-9-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-29drm/i915: Limit plane stride to below TILEOFF.x limitVille Syrjälä
Limit pre-skl plane stride to below 4k or 8k pixels (depending on the platform). We do this in order guarantee that TILEOFF/OFFSET.x does not get too big. Currently this is not a problem as we align SURF to 4k, and so TILEOFF/OFFSET only have to deal with a single tile's worth of pixels. But for async flips we're going to have to bump SURF alignment to 256k, and thus we can no longer guarantee TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid this by borrowing a trick from the skl+ code and limit the max plane stride to whatever value we can fit into TILEOFF/OFFSET.x. The slight downside is that we may end up doing GTT remapping in a few more cases where previously we did not have to. But since that will only happen with huge buffers I'm not really concerned about it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-3-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-29drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_neededJosé Roberto de Souza
As it now it is always required for GEN12+ the is_16gb_dimm name do not make sense for GEN12+. v2: - Updated comment on top of "dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);" Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-3-jose.souza@intel.com
2021-01-29drm/i915/gen11+: Only load DRAM information from pcodeJosé Roberto de Souza
Up to now we were reading some DRAM information from MCHBAR register and from pcode what is already not good but some GEN12(TGL-H and ADL-S) platforms have MCHBAR DRAM information in different offsets. This was notified to HW team that decided that the best alternative is always apply the 16gb_dimm watermark adjustment for GEN12+ platforms and read the remaning DRAM information needed to other display programming from pcode. So here moving the DRAM pcode function to intel_dram.c, removing the duplicated fields from intel_qgv_info, setting and using information from dram_info. v2: - bring back num_points to intel_qgv_info as num_qgv_point can be overwritten in icl_get_qgv_points() - add gen12_get_dram_info() and simplify gen11_get_dram_info() Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-2-jose.souza@intel.com
2021-01-29drm/i915: Nuke not needed members of dram_infoJosé Roberto de Souza
Valid, ranks and bandwidth_kbps are set into dram_info but are not used anywhere else so nuking it. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-1-jose.souza@intel.com
2021-01-29Merge tag 'drm-intel-next-2021-01-27' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-next - HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (Anshuman) - Fix DP vswing settings and handling (Imre, Ville) - Various display code clean-up (Jani, Ville) - Various display refactoring, including split out of pps, aux, and fdi (Ja\ ni, Dave) - Add DG1 missing workarounds (Jose) - Fix display color conversion (Chris, Ville) - Try to guess PCH type even without ISA bridge (Zhenyu) - More backlight refactor (Lyude) - Support two CSC module on gen11 and later (Lee) - Async flips for all ilk+ platforms (Ville) - Clear color support for TGL (RK) - Add a helper to read data from a GEM object page (Imre) - VRR/Adaptive Sync Enabling on DP/eDP for TGL+ (Manasi, Ville Aditya) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210127140822.GA711686@intel.com
2021-01-29drm/nouveau/kms: handle mDP connectorsKarol Herbst
In some cases we have the handle those explicitly as the fallback connector type detection fails and marks those as eDP connectors. Attempting to use such a connector with mutter leads to a crash of mutter as it ends up with two eDP displays. Information is taken from the official DCB documentation. Cc: stable@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: Ben Skeggs <bskeggs@redhat.com> Reported-by: Mark Pearson <markpearson@lenovo.com> Tested-by: Mark Pearson <markpearson@lenovo.com> Signed-off-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau: bail out of nouveau_channel_new if channel init failsFrantisek Hrbata
Unprivileged user can crash kernel by using DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC ioctl. This was reported by trinity[1] fuzzer. [ 71.073906] nouveau 0000:01:00.0: crashme[1329]: channel failed to initialise, -17 [ 71.081730] BUG: kernel NULL pointer dereference, address: 00000000000000a0 [ 71.088928] #PF: supervisor read access in kernel mode [ 71.094059] #PF: error_code(0x0000) - not-present page [ 71.099189] PGD 119590067 P4D 119590067 PUD 1054f5067 PMD 0 [ 71.104842] Oops: 0000 [#1] SMP NOPTI [ 71.108498] CPU: 2 PID: 1329 Comm: crashme Not tainted 5.8.0-rc6+ #2 [ 71.114993] Hardware name: AMD Pike/Pike, BIOS RPK1506A 09/03/2014 [ 71.121213] RIP: 0010:nouveau_abi16_ioctl_channel_alloc+0x108/0x380 [nouveau] [ 71.128339] Code: 48 89 9d f0 00 00 00 41 8b 4c 24 04 41 8b 14 24 45 31 c0 4c 8d 4b 10 48 89 ee 4c 89 f7 e8 10 11 00 00 85 c0 75 78 48 8b 43 10 <8b> 90 a0 00 00 00 41 89 54 24 08 80 7d 3d 05 0f 86 bb 01 00 00 41 [ 71.147074] RSP: 0018:ffffb4a1809cfd38 EFLAGS: 00010246 [ 71.152526] RAX: 0000000000000000 RBX: ffff98cedbaa1d20 RCX: 00000000000003bf [ 71.159651] RDX: 00000000000003be RSI: 0000000000000000 RDI: 0000000000030160 [ 71.166774] RBP: ffff98cee776de00 R08: ffffdc0144198a08 R09: ffff98ceeefd4000 [ 71.173901] R10: ffff98cee7e81780 R11: 0000000000000001 R12: ffffb4a1809cfe08 [ 71.181214] R13: ffff98cee776d000 R14: ffff98cec519e000 R15: ffff98cee776def0 [ 71.188339] FS: 00007fd926250500(0000) GS:ffff98ceeac80000(0000) knlGS:0000000000000000 [ 71.196418] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 71.202155] CR2: 00000000000000a0 CR3: 0000000106622000 CR4: 00000000000406e0 [ 71.209297] Call Trace: [ 71.211777] ? nouveau_abi16_ioctl_getparam+0x1f0/0x1f0 [nouveau] [ 71.218053] drm_ioctl_kernel+0xac/0xf0 [drm] [ 71.222421] drm_ioctl+0x211/0x3c0 [drm] [ 71.226379] ? nouveau_abi16_ioctl_getparam+0x1f0/0x1f0 [nouveau] [ 71.232500] nouveau_drm_ioctl+0x57/0xb0 [nouveau] [ 71.237285] ksys_ioctl+0x86/0xc0 [ 71.240595] __x64_sys_ioctl+0x16/0x20 [ 71.244340] do_syscall_64+0x4c/0x90 [ 71.248110] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 71.253162] RIP: 0033:0x7fd925d4b88b [ 71.256731] Code: Bad RIP value. [ 71.259955] RSP: 002b:00007ffc743592d8 EFLAGS: 00000206 ORIG_RAX: 0000000000000010 [ 71.267514] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007fd925d4b88b [ 71.274637] RDX: 0000000000601080 RSI: 00000000c0586442 RDI: 0000000000000003 [ 71.281986] RBP: 00007ffc74359340 R08: 00007fd926016ce0 R09: 00007fd926016ce0 [ 71.289111] R10: 0000000000000003 R11: 0000000000000206 R12: 0000000000400620 [ 71.296235] R13: 00007ffc74359420 R14: 0000000000000000 R15: 0000000000000000 [ 71.303361] Modules linked in: rfkill sunrpc snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio snd_hda_intel snd_intel_dspcfg snd_hda_codec snd_hda_core edac_mce_amd snd_hwdep kvm_amd snd_seq ccp snd_seq_device snd_pcm kvm snd_timer snd irqbypass soundcore sp5100_tco pcspkr crct10dif_pclmul crc32_pclmul ghash_clmulni_intel wmi_bmof joydev i2c_piix4 fam15h_power k10temp acpi_cpufreq ip_tables xfs libcrc32c sd_mod t10_pi sg nouveau video mxm_wmi i2c_algo_bit drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops ttm broadcom bcm_phy_lib ata_generic ahci drm e1000 crc32c_intel libahci serio_raw tg3 libata firewire_ohci firewire_core wmi crc_itu_t dm_mirror dm_region_hash dm_log dm_mod [ 71.365269] CR2: 00000000000000a0 simplified reproducer ---------------------------------8<---------------------------------------- /* * gcc -o crashme crashme.c * ./crashme /dev/dri/renderD128 */ struct drm_nouveau_channel_alloc { uint32_t fb_ctxdma_handle; uint32_t tt_ctxdma_handle; int channel; uint32_t pushbuf_domains; /* Notifier memory */ uint32_t notifier_handle; /* DRM-enforced subchannel assignments */ struct { uint32_t handle; uint32_t grclass; } subchan[8]; uint32_t nr_subchan; }; static struct drm_nouveau_channel_alloc channel; int main(int argc, char *argv[]) { int fd; int rv; if (argc != 2) die("usage: %s <dev>", 0, argv[0]); if ((fd = open(argv[1], O_RDONLY)) == -1) die("open %s", errno, argv[1]); if (ioctl(fd, DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC, &channel) == -1 && errno == EACCES) die("ioctl %s", errno, argv[1]); close(fd); printf("PASS\n"); return 0; } ---------------------------------8<---------------------------------------- [1] https://github.com/kernelslacker/trinity Fixes: eeaf06ac1a55 ("drm/nouveau/svm: initial support for shared virtual memory") Signed-off-by: Frantisek Hrbata <frantisek@hrbata.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: Fix locking for audio callbacksLyude Paul
Noticed that I wasn't paying close enough attention the last time I looked at our audio callbacks, as I completely missed the fact that we were figuring out which audio-enabled connector goes to each encoder by checking it's state, but without grabbing any of the appropriate modesetting locks to do so. That being said however: trying to grab modesetting locks in our audio callbacks would be very painful due to the potential for locking inversion between HDA and DRM. So, let's instead just copy what i915 does again - add our own audio lock to protect audio related state, and store each audio enabled connector in each nouveau_encoder struct so that we don't need to check any atomic states. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: Use nouveau_encoder->crtc in get_eld callbackLyude Paul
drm_encoder->crtc is deprecated for atomic drivers, but nouveau_encoder->crtc is safe. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: Lookup current encoder/crtc from atomic stateLyude Paul
Despite being an atomic driver, nouveau has a lot of leftover code that relies on retrieving information regarding the new atomic state from members of drm_encoder and drm_crtc. The first field being used, drm_encoder.crtc, is deprecated for atomic drivers. The second field being used is drm_crtc.state, which is only really sensible to use outside of an atomic modeset. So, add some helpers to lookup the current crtc for a given outp from the atomic state. Then, convert most of the code in dispnv50/disp.c to use said new helper, along with the relevant DRM atomic helpers for retrieving the new encoder/crtc combinations for a new atomic state. Note that we don't get rid of the nouveau_encoder.crtc field entirely for three reasons: - Legacy modesetting for pre-nv50 still uses it - It doesn't cause any locking issues - We need it for the HDA callbacks, as grabbing atomic modesetting locks in those would be a mess. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: Reverse args for nv50_outp_get_(old|new)_connector()Lyude Paul
Just to be more consistent with the order of args that DRM helpers like drm_atomic_get_new_crtc_state() use. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: s/armh/asyh/ in nv50_msto_atomic_enable()Lyude Paul
I have a strange dejavu feeling that I tried to submit a patch for this in the past, but that it was rejected. I can't remember though, but I'm further convinced this patch is the right thing to do anyway. We label the to-be-committed head state in nv50_msto_atomic_enable() as armh. Normally armh implies a state which is currently armed in hardware. nv50_msto_atomic_enable() is called _after_ drm_atomic_swap_state() however, but before the commit tail ends, which means that said state is not actually armed on hardware. As well - take note that this is the same convention followed in all of the other atomic_enable() callbacks. So, let's correct this to asyh. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: Rename encoder->atomic_(enable|disable) callbacksLyude Paul
No functional changes, just change the function names to match the callbacks they provide. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/kms/nv50-: Remove (nv_encoder->crtc) checks in ->disable callbacksLyude Paul
Noticed these in both the disable (which we'll be getting rid of in a moment) and the atomic disable callbacks: both callback types check whether or not there's actually a CRTC assigned to the given encoder. However, as ->atomic_disable and ->disable will never be called without a CRTC assigned to the given encoder there's no point in this check. So just remove it. Signed-off-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/fifo/tu102: Turing channel preemption fixAlistair Popple
Previous hardware allowed a MMU fault to be generated by software to trigger a context switch for engine recovery. Turing has the capability to preempt all work from a specific runlist processor and removed the registers currently used for triggering MMU faults. Attempting to access these non-existent registers results in further errors, so use the runlist preemption register instead. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/fifo/tu102: FIFO interrupt fixes for TuringAlistair Popple
Some of the low level FIFO interrupt status bits have changed for Turing. Update the handling of these to match the hardware. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2021-01-29drm/nouveau/fifo/tu102: Move Turing specific FIFO functionsAlistair Popple
Turing requires some changes to FIFO interrupt handling due to changes in HW register layout. It also requires some changes to implement robust channel (RC) recovery. This preparatory patch moves the functions requiring changes into nvkm/engine/fifo/tu102.c so they can be altered without affecting gk104 and other users. It should not introduce any functional changes. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 18:55:56 +0000