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Configures the megachips-stdpxxxx-ge-b850v3-fw bridges on the GE
B850v3 dts file.
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Martyn Welch <martyn.welch@collabora.co.uk>
Cc: Martin Donnelly <martin.donnelly@ge.com>
Cc: Javier Martinez Canillas <javier@dowhile0.org>
Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Peter Senna Tschudin <peter.senna@collabora.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The imx7d-sdb has a mickro bus connector that can be connected to a
Sensirion SHT11 click board (temperature and humidity sensor):
https://shop.mikroe.com/click/sensors/sht1x
Add a new device tree file to describe such hardware.
Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The PHYs embedded in the switch direct there interrupts through the
switch interrupt controllers. Now that devel C has its switch
interrupts connected to the SoC, the PHY interrupts can be used by
phylib. Explicitly include MDIO nodes in the switch device tree nodes,
and link the PHY interrupts back to the switch interrupt
controller. Also, link the ports to the PHYs on the MDIO bus.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The devel B and devel C board use the same GPIO lines for interrupts
from the two switches. Move the pinmux nodes from devel B into the
shared .dtsi file, and wire up the interrupts on devel C.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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UART on i.MX6SX (like all other i.MX6 SoC variants) has the same
programming model as the 'imx6q-uart' type, so add it to the compatible
UART string.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Change the maxium spi clock frequency from 20MHz to 10MHz to meet the
operation voltage range requirement recommended in AT25 datasheet.
Signed-off-by: Ken Lin <yungching0725@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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According to the reference manuals, both imx50/imx53 SOC seem to share
the same eSDHC controller, especially the section on "Multi-block Read"
mentioned in commit 361b8482026c ("mmc: sdhci-esdhc-imx: fix multiblock
reads on i.MX53") is identical for both SOC.
Hence, let imx50 use imx53-esdhc.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Enable ocotp for i.mx7D/S.
Correct the clock entry and compatible string.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Reference them by handle and remove the changed clocks that are copied
from the downstream DT and are not part of the mainline binding.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Referencing the node by handle make the QP DT more resilent against
changes of the base DT. Also remove the duplicated reg property, it's
not needed as it the same as in the base DT, just the compatible is
actually different.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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By using the handle, we can avoid some duplication of the base DT
and so avoid any maintenance overhead in the QP DT if the referenced
node changes.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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All currently supported i.MX25-based machines use phy_type = "utmi" and
dr_mode = "otg". So this seems to be a sensible default.
This also doesn't hurt out-of-tree machines because up to now they had
to specify these two properties in the machine.dts which still takes
precedence by just overwriting the defaults added here.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This machine is based on I2SE's Duckbill 2 board and is sold as part
of I2SE's PLC Bundle for IoT. This is a development kit for Homeplug
Green PHY based powerline products based on Qualcomms QCA7000 chip.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This machine is based on I2SE's Duckbill 2 board and features a
EnOcean daugther board based on the popular TCM310 chipset.
This product is intended to be used for e.g. home automation purposes.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This machine is based on I2SE's Duckbill 2 board and features a
RS-485 daugther board. This device is intended to be used for
e.g. home automation purposes.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This machine is an USB pen drive sized development board,
based on NXP's i.MX28 CPU. In contrast to the previous
model "Duckbill", the "Duckbill 2" series has internal
eMMC storage.
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add CPCAP PMIC OTG PHY configuration.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Reviewed-by: Sebastian Reichel <sre@kernel.org>
Tested-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add CPCAP PMIC battery charger configuration.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Reviewed-by: Sebastian Reichel <sre@kernel.org>
Tested-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add CPCAP PMIC ADC configuration.
Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Reviewed-by: Sebastian Reichel <sre@kernel.org>
Tested-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Rick Altherr <raltherr@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Romulus has a RS-232 connection on the back of chassis, add UART1 to use
this connection.
Signed-off-by: Lei YU <mine260309@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The string was changed when upstreaming the driver. Put the correct
string for generation 4 and 5 systems, as well as fix the reg length for
ast2500 systems.
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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All chips on OpenPOWER platforms support the fastread SPI command.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Romulus systems have one MX25L25635 (32768 Kbytes) flash module for
the BMC firmware and other MT25QL512A (65536 Kbytes) for the host.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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We do not yet have a clk driver upstream. So that users can boot the
unmodified upstream kernel, add fixed-clock and clock-frequency
properties to all of the clocks.
The values are taken from the Palmetto system. This is the only upstream
dts. It also happens to match all of the systems seen so far.
Acked-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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We do not yet have a clk driver upstream. So that users can boot the
unmodified upstream kernel, add fixed-clock and clock-frequency
properties to all of the clocks.
The values are taken from the ast2500evb. This is the only upstream dts.
It also happens to match all of the systems I have seen so far.
Acked-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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This reverts commit 769907ae6e6c2871c2ba4f578814d86fbfbe8d91.
This change caused issues with people using USB gadget for serial
consoles. In addition, with the other USB changes coming in, it
makes sense to revert this patch and apply the new set as it
becomes ready.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add basic support for the PCM-947 carrier board, a RK3288 based development
board made by PHYTEC. This board works in a combination with
the phyCORE-RK3288 System on Module.
Following interfaces and devices are available on the PCM-947 carrier board:
- 2x UART
- micro SDMMC
- USB host and USB otg
- USB 3503 HSIC hub
- Ethernet
- 2nd alternative KSZ9031 ethernet phy
- Display connectors: PHYTEC LVDS, DDG LVDS, parallel signals, HDMI
- Parallel Camera CIF
- SGTL5000-32QFN audio codec
- 4x LEDs connected via PCA9533
- 2 user buttons
- Expansion connectors for WiFi and other modules
- RTC RV-4162-C7
- Resistive touch STMPE811
- EEPROM M24C32
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add documentation for the PCM-947 carrier board, a RK3288 based
development board made by PHYTEC.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The phyCORE-RK3288 is a SoM (System on Module) containing a RK3288 SoC.
The module can be connected to different carrier boards.
It can be also equipped with different RAM, SPI flash and eMMC variants.
The Rapid Development Kit option is using the following setup:
- 1 GB DDR3 RAM (2 Banks)
- 1x 4 KB EEPROM
- DP83867 Gigabit Ethernet PHY
- 16 MB SPI Flash
- 4 GB eMMC Flash
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The current practice is to not add _clk suffixes to clock node names in
DT, as these names are used as the actual clock names.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero and enable the realtime clock.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Commit a4ee7e18d808 ("ARM: dts: armada: Add default trigger for sata
led") adds the default trigger to individual boards, move it to
armada-385-linksys.dtsi which effectively enables the definition for
the WRT1900ACS (Shelby) as well as for future boards.
Signed-off-by: Ralph Sennhauser <ralph.sennhauser@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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The A33 supports 1.1GHz and 1.2GHz frequencies at 1.32V and the Sinlinx
SinA33 has its cpu-supply property set in the cpu DT node.
Therefore, CPUfreq knows how to handle the regulator in charge of the
CPU and can adjust its voltage to match the OPP.
Add these two CPU frequencies to the CPU OPP table of the Sinlinx
SinA33.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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This adds GPU thermal throttling for the Allwinner A33.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
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This adds CPU thermal throttling for the Allwinner A33. It uses the
thermal sensor present in the SoC's GPADC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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This adds the DT node for the thermal sensor present in the Allwinner
A33 GPADC.
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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This patch changes the device node position of ps20 and ps21 to fix
ordering by rising physical address.
From
uart7: serial@01c29c00
i2c0: i2c@01c2ac00
i2c1: i2c@01c2b000
i2c2: i2c@01c2b400
i2c3: i2c@01c2b800
i2c4: i2c@01c2c000
gmac: ethernet@01c50000
hstimer@01c60000
gic: interrupt-controller@01c81000
ps20: ps2@01c2a000
ps21: ps2@01c2a400
to
uart7: serial@01c29c00
ps20: ps2@01c2a000
ps21: ps2@01c2a400
i2c0: i2c@01c2ac00
i2c1: i2c@01c2b000
i2c2: i2c@01c2b400
i2c3: i2c@01c2b800
i2c4: i2c@01c2c000
gmac: ethernet@01c50000
hstimer@01c60000
gic: interrupt-controller@01c81000
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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This patch changes the device node position of ps20 and ps21 to fix
ordering by rising physical address.
From
uart7: serial@01c29c00
i2c0: i2c@01c2ac00
i2c1: i2c@01c2b000
i2c2: i2c@01c2b400
ps20: ps2@01c2a000
ps21: ps2@01c2a400
to
uart7: serial@01c29c00
ps20: ps2@01c2a000
ps21: ps2@01c2a400
i2c0: i2c@01c2ac00
i2c1: i2c@01c2b000
i2c2: i2c@01c2b400
Signed-off-by: Patrick Menschel <menschel.p@posteo.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Enable the realtime clock.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Enable the 32.768 kHz RTC_X1 clock by setting the frequency value to
non-zero.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the realtime clock device node.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the RTC clocks to device tree. The frequencies must be fixed values
according to the hardware manual.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add the realtime clock functional clock source.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The X2 crystal oscillator on the Koelsch development board provides a
74.25 MHz clock, not a 148.5 MHz clock.
Fixes: cd21cb46e14aae3a ("ARM: shmobile: koelsch: Add DU external pixel clocks to DT")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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I disabled SRAM and GPMC originally when seeing errors with
omap_barriers_init(). But that is no longer happening probably
because the memory range is now properly configured to 1021 MB
instead of 1024 MB. So let's enable SRAM and GPMC so we get
omap_barriers_init() working and can idle the GPMC.
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The CPCAP PMIC interrupt is level high sensitive despite it being
requested as edge high triggered in the Motorola Linux kernel.
Note that also the related driver change is needed posted as
"mfd: cpcap: Fix interrupt to use level interrupt".
Fixes: 56e1d40d3bea ("mfd: cpcap: Add minimal support")
Cc: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Enable the 2 ethernet ports as CPSW ports in dual-mac mode
Signed-off-by: Roger Quadros <rogerq@ti.com>
[nsekhar@ti.com: use AM33XX_IOPAD()]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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