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2024-12-24dt-bindings: dma: atmel: Convert to json schemaCharan Pedumuru
Convert old text based binding to json schema. Changes during conversion: - Add the required properties `clock` and `clock-names`, which were missing in the original binding. - Add a fallback for `microchip,sam9x7-dma` and `microchip,sam9x60-dma` as they are compatible with the dma IP core on `atmel,sama5d4-dma`. - Update examples and include appropriate file directives to resolve errors identified by `dt_binding_check` and `dtbs_check`. Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241205-xdma-v1-1-76a4a44670b5@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dt-bindings: dma: st-stm32-dmamux: Add description for dma-cell valuesKen Sloat
The dma-cell values for the stm32-dmamux are used to craft the DMA spec for the actual controller. These values are currently undocumented leaving the user to reverse engineer the driver in order to determine their meaning. Add a basic description, while avoiding duplicating information by pointing the user to the associated DMA docs that describe the fields in depth. Signed-off-by: Ken Sloat <ksloat@cornersoftsolutions.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20241206115018.1155149-1-ksloat@cornersoftsolutions.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: qcom: gpi: Add GPI immediate DMA support for SPI protocolJyothi Kumar Seerapu
The DMA TRE(Transfer ring element) buffer contains the DMA buffer address. Accessing data from this address can cause significant delays in SPI transfers, which can be mitigated to some extent by utilizing immediate DMA support. QCOM GPI DMA hardware supports an immediate DMA feature for data up to 8 bytes, storing the data directly in the DMA TRE buffer instead of the DMA buffer address. This enhancement enables faster SPI data transfers. This optimization reduces the average transfer time from 25 us to 16 us for a single SPI transfer of 8 bytes length, with a clock frequency of 50 MHz. Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241209075033.16860-1-quic_jseerapu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dt-bindings: dma: adi,axi-dmac: deprecate adi,channels nodeDavid Lechner
Deprecate the adi,channels node in the adi,axi-dmac binding. Prior to IP version 4.3.a, this information was required. Since then, there are memory-mapped registers that can be read to get the same information. Acked-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-2-7b994710c43f@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dt-bindings: dma: adi,axi-dmac: convert to yaml schemaDavid Lechner
Convert the AXI DMAC bindings from .txt to .yaml. Acked-by: Nuno Sa <nuno.sa@analog.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-1-7b994710c43f@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: mv_xor: switch to for_each_child_of_node_scoped()Javier Carrasco
Introduce the scoped variant of the loop to automatically release the child node when it goes out of scope, which is more robust than the non-scoped variant, and accounts for new early exits that could be added in the future. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20241011-dma_mv_xor_of_node_put-v1-2-3c2de819f463@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24Merge branch 'fixes' into nextVinod Koul
2024-12-24dmaengine: mv_xor: fix child node refcount handling in early exitJavier Carrasco
The for_each_child_of_node() loop requires explicit calls to of_node_put() to decrement the child's refcount upon early exits (break, goto, return). Add the missing calls in the two early exits before the goto instructions. Cc: stable@vger.kernel.org Fixes: f7d12ef53ddf ("dma: mv_xor: add Device Tree binding") Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Link: https://lore.kernel.org/r/20241011-dma_mv_xor_of_node_put-v1-1-3c2de819f463@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: bcm2835-dma: Prevent suspend if DMA channel is busyStefan Wahren
bcm2835-dma provides the service to others, so it should suspend late and resume early. Suspend should be prevented in case a DMA channel is still busy. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20241204165546.77941-1-wahrenst@gmx.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: tegra210-adma: Support channel pageMohan Kumar D
Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. - Add support in the tegra adma driver to handle selective channel page usage - Make global register programming optional Signed-off-by: Mohan Kumar D <mkumard@nvidia.com> Link: https://lore.kernel.org/r/20241217074358.340180-3-mkumard@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dt-bindings: dma: Support channel page to nvidia,tegra210-admaMohan Kumar D
Multiple ADMA Channel page hardware support has been added from TEGRA186 and onwards. Update the DT binding to use any of the ADMA channel page address space region. Signed-off-by: Mohan Kumar D <mkumard@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241217074358.340180-2-mkumard@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: ti: k3-udma: Add support for J722S CSI BCDMAVaishnav Achath
J722S CSI BCDMA is similar to J721S2 CSI BCDMA but there are slight integration differences like different PSIL thread base ID which is currently handled in the driver based on udma_of_match data. Add an entry to support J722S CSIRX. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20241127101627.617537-3-vaishnav.a@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dt-bindings: dma: ti: k3-bcdma: Add J722S CSI BCDMAVaishnav Achath
J722S CSI BCDMA is similar to J721S2 CSI BCDMA and supports both RX and TX channels but has a different PSIL thread base ID which is currently handled in k3-udma driver. Add an entry for J722S CSIRX BCDMA. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241127101627.617537-2-vaishnav.a@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: ti: edma: fix OF node reference leaks in edma_driverJoe Hattori
The .probe() of edma_driver calls of_parse_phandle_with_fixed_args() but does not release the obtained OF nodes. Thus add a of_node_put() call. This bug was found by an experimental verification tool that I am developing. Fixes: 1be5336bc7ba ("dmaengine: edma: New device tree binding") Signed-off-by: Joe Hattori <joe@pf.is.s.u-tokyo.ac.jp> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://lore.kernel.org/r/20241219020507.1983124-3-joe@pf.is.s.u-tokyo.ac.jp Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: ti: edma: make the loop condition simpler in edma_probe()Joe Hattori
When i == ecc->num_tc, the edma_probe() calls of_parse_phandle_with_fixed_args() and breaks from the loop regardless of the return value. Since neither the returned value nor the output argument tc_args is used, set i < ecc->num_tc as the loop condition. Signed-off-by: Joe Hattori <joe@pf.is.s.u-tokyo.ac.jp> Link: https://lore.kernel.org/r/20241219020507.1983124-2-joe@pf.is.s.u-tokyo.ac.jp Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: fsl-edma: read/write multiple registers in cyclic transactionsLarisa Grigore
Add support for reading multiple registers in DEV_TO_MEM transactions and for writing multiple registers in MEM_TO_DEV transactions. Signed-off-by: Frank Li <Frank.Li@nxp.com> Co-developed-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com> Signed-off-by: Alexandru-Catalin Ionita <alexandru-catalin.ionita@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> Link: https://lore.kernel.org/r/20241219102415.1208328-6-larisa.grigore@oss.nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: fsl-edma: add support for S32G based platformsLarisa Grigore
S32G2/S32G3 includes two system eDMA instances based on v3 version, each of them integrated with two DMAMUX blocks. Another particularity of these SoCs is that the interrupts are shared between channels as follows: - DMA Channels 0-15 share the 'tx-0-15' interrupt - DMA Channels 16-31 share the 'tx-16-31' interrupt - all channels share the 'err' interrupt Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> Co-developed-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20241219102415.1208328-5-larisa.grigore@oss.nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible stringLarisa Grigore
Introduce the compatible strings 'nxp,s32g2-edma' and 'nxp,s32g3-edma' to enable the support for the eDMAv3 present on S32G2/S32G3 platforms. The S32G2/S32G3 eDMA architecture features 32 DMA channels. Each of the two eDMA instances is integrated with two DMAMUX blocks. Another particularity of these SoCs is that the interrupts are shared between channels in the following way: - DMA Channels 0-15 share the 'tx-0-15' interrupt - DMA Channels 16-31 share the 'tx-16-31' interrupt - all channels share the 'err' interrupt Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241219102415.1208328-4-larisa.grigore@oss.nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: fsl-edma: remove FSL_EDMA_DRV_SPLIT_REG check when parsing muxbaseLarisa Grigore
Clean up dead code. dmamuxs is always 0 when FSL_EDMA_DRV_SPLIT_REG set. So it is redundant to check FSL_EDMA_DRV_SPLIT_REG again in the for loop because it will never enter for loop. Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20241219102415.1208328-3-larisa.grigore@oss.nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: fsl-edma: select of_dma_xlate based on the dmamuxs presenceLarisa Grigore
Select the of_dma_xlate function based on the dmamuxs definition rather than the FSL_EDMA_DRV_SPLIT_REG flag, which pertains to the eDMA3 layout. This change is a prerequisite for the S32G platforms, which integrate both eDMAv3 and DMAMUX. Existing platforms with FSL_EDMA_DRV_SPLIT_REG will not be impacted, as they all have dmamuxs set to zero. Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20241219102415.1208328-2-larisa.grigore@oss.nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: qcom: bam_dma: Avoid writing unavailable registerMd Sadre Alam
Avoid writing unavailable register in BAM-Lite mode. BAM_DESC_CNT_TRSHLD register is unavailable in BAM-Lite mode. Its only available in BAM-NDP mode. So only write this register for clients who is using BAM-NDP. Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20241220094203.3510335-1-quic_mdalam@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: fsl-edma: implement the cleanup path of fsl_edma3_attach_pd()Joe Hattori
Current implementation of fsl_edma3_attach_pd() does not provide a cleanup path, resulting in a memory leak. For example, dev_pm_domain_detach() is not called after dev_pm_domain_attach_by_id(), and the device link created with the DL_FLAG_STATELESS is not released explicitly. Therefore, provide a cleanup function fsl_edma3_detach_pd() and call it upon failure. Also add a devm_add_action_or_reset() call with this function after a successful fsl_edma3_attach_pd(). Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support") Signed-off-by: Joe Hattori <joe@pf.is.s.u-tokyo.ac.jp> Link: https://lore.kernel.org/r/20241221075712.3297200-1-joe@pf.is.s.u-tokyo.ac.jp Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24dmaengine: idxd: Remove unused idxd_(un)register_bus_typeDr. David Alan Gilbert
idxd_register_bus_type() and idxd_unregister_bus_type() have been unused since 2021's commit d9e5481fca74 ("dmaengine: dsa: move dsa_bus_type out of idxd driver to standalone") Remove them. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20241221141635.69412-1-linux@treblig.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dmaengine: amd: qdma: make read-only arrays h2c_types and c2h_types static constColin Ian King
Don't populate the read-only arrays h2c_types and c2h_types on the stack at run time, instead make them static const. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20240912131017.588141-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dt-bindings: dma: qcom,gpi: Document the sm8750 GPI DMA engineMelody Olvera
Document the GPI DMA engine on the sm8750 platform. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241021230500.2632527-1-quic_molvera@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dmaengine: idxd: Add a new IAA device ID on Panther Lake family platformsFenghua Yu
A new IAA device ID, 0xb02d, is introduced across all Panther Lake family platforms. Add the device ID to the IDXD driver. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Link: https://lore.kernel.org/r/20241024183500.281268-1-fenghua.yu@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dma-engine: sun4i: Add support for Allwinner suniv F1C100sMesih Kilinc
DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4 DDMA channels and endpoints are different. Also F1C100s has reset bit for DMA in CCU. Add support for it. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> [ csokas.bence: Rebased on current master ] Signed-off-by: Csókás Bence <csokas.bence@prolan.hu> Link: https://lore.kernel.org/r/20241122161128.2619172-5-csokas.bence@prolan.hu Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dt-bindings: dmaengine: Add Allwinner suniv F1C100s DMACsókás, Bence
Add compatible string for Allwinner suniv F1C100s DMA. Acked-by: Conor Dooley <conor.dooley@microchip.com> [ csokas.bence: Reimplemented Mesih Kilinc's binding in YAML ] Signed-off-by: Csókás Bence <csokas.bence@prolan.hu> Link: https://lore.kernel.org/r/20241122161128.2619172-4-csokas.bence@prolan.hu Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dma-engine: sun4i: Add has_reset option to quirkMesih Kilinc
Allwinner suniv F1C100s has a reset bit for DMA in CCU. Sun4i do not has this bit but in order to support suniv we need to add it. So add support for reset bit. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> [ csokas.bence: Rebased and addressed comments ] Signed-off-by: Csókás Bence <csokas.bence@prolan.hu> Link: https://lore.kernel.org/r/20241122161128.2619172-3-csokas.bence@prolan.hu Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-11dma-engine: sun4i: Add a quirk to support different chipsMesih Kilinc
Allwinner suniv F1C100s has similar DMA engine to sun4i. Several registers has different addresses. Total dma channels, endpoint counts and max burst counts are also different. In order to support F1C100s add a quirk structure to hold IC specific data. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> [ csokas.bence: Resolve conflict in `sun4i_dma_prep_dma_cyclic()`, fix whitespace ] Signed-off-by: Csókás Bence <csokas.bence@prolan.hu> Link: https://lore.kernel.org/r/20241122161128.2619172-2-csokas.bence@prolan.hu Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04dmaengine: amd: qdma: Remove using the private get and set dma_ops APIsLizhi Hou
The get_dma_ops and set_dma_ops APIs were never for driver to use. Remove these calls from QDMA driver. Instead, pass the DMA device pointer from the qdma_platdata structure. Fixes: 73d5fc92a11c ("dmaengine: amd: qdma: Add AMD QDMA driver") Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20240918181022.2155715-1-lizhi.hou@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04dmaengine: sh: rcar-dmac: add comment for r8a779a0 compatibleKuninori Morimoto
Add the reason why we need r8a779a0 compatible. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://lore.kernel.org/r/87a5dlwlr0.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04dmaengine: apple-admac: Avoid accessing registers in probeSasha Finkelstein
The ADMAC attached to the AOP has complex power sequencing, and is power gated when the probe callback runs. Move the register reads to other functions, where we can guarantee that the hardware is switched on. Fixes: 568aa6dd641f ("dmaengine: apple-admac: Allocate cache SRAM to channels") Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Link: https://lore.kernel.org/r/20241124-admac-power-v1-1-58f2165a4d55@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04linux/dmaengine.h: fix a few kernel-doc warningsRandy Dunlap
The comment block for "Interleaved Transfer Request" should not begin with "/**" since it is not in kernel-doc format. Fix doc name for enum sum_check_flags. Fix all (4) missing struct member warnings. Use "Warning:" for one "Note:" in enum dma_desc_metadata_mode since scripts/kernel-doc does not allow more than one Note: per function or identifier description. This leaves around 49 kernel-doc warnings like: include/linux/dmaengine.h:43: warning: Enum value 'DMA_OUT_OF_ORDER' not described in enum 'dma_status' and another scripts/kernel-doc problem with it not being able to parse some typedefs. Fixes: b14dab792dee ("DMAEngine: Define interleaved transfer request api") Fixes: ad283ea4a3ce ("async_tx: add sum check flags") Fixes: 272420214d26 ("dmaengine: Add DMA_CTRL_REUSE") Fixes: f067025bc676 ("dmaengine: add support to provide error result from a DMA transation") Fixes: d38a8c622a1b ("dmaengine: prepare for generic 'unmap' data") Fixes: 5878853fc938 ("dmaengine: Add API function dmaengine_prep_peripheral_dma_vec()") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Nuno Sa <nuno.sa@analog.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: dmaengine@vger.kernel.org Link: https://lore.kernel.org/r/20241202172004.76020-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: ae4dma: Register debugfs using ptdma_debugfs_setupBasavaraj Natikar
Use the ptdma_debugfs_setup function to register debugfs for AE4DMA DMA engine. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-7-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: ptdma: Extend ptdma-debugfs to support multi-queueBasavaraj Natikar
To support multi-channel functionality with AE4DMA engine, extend the ptdma-debugfs with reusable components. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-6-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: ae4dma: Register AE4DMA using pt_dmaengine_registerBasavaraj Natikar
Use the pt_dmaengine_register function to register a AE4DMA DMA engine. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Reviewed-by: Philipp Stanner <pstanner@redhat.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-5-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: ptdma: Extend ptdma to support multi-channel and versionBasavaraj Natikar
To support multi-channel functionality with AE4DMA engine, extend the PTDMA code with reusable components. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-4-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: ae4dma: Add AMD ae4dma controller driverBasavaraj Natikar
Add support for AMD AE4DMA controller. It performs high-bandwidth memory to memory and IO copy operation. Device commands are managed via a circular queue of 'descriptors', each of which specifies source and destination addresses for copying a single buffer of data. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Reviewed-by: Philipp Stanner <pstanner@redhat.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-3-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: Move AMD PTDMA driver to amd directoryBasavaraj Natikar
PTDMA driver is the AMD DMA driver, and newer AMD platforms support newer DMA engines. Hence, move the current drivers to the AMD directory. This would also mean that future driver submissions to the AMD DMA driver will also land in the AMD-specific directory. Reviewed-by: Raju Rangoju <Raju.Rangoju@amd.com> Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com> Link: https://lore.kernel.org/r/20241025095931.726018-2-Basavaraj.Natikar@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: loongson2-apb: Change GENMASK to GENMASK_ULLBinbin Zhou
Fix the following smatch static checker warning: drivers/dma/loongson2-apb-dma.c:189 ls2x_dma_write_cmd() warn: was expecting a 64 bit value instead of '~(((0)) + (((~((0))) - (((1)) << (0)) + 1) & (~((0)) >> ((8 * 4) - 1 - (4)))))' The GENMASK macro used "unsigned long", which caused build issues when using a 32-bit toolchain because it would try to access bits > 31. This patch switches GENMASK to GENMASK_ULL, which uses "unsigned long long". Fixes: 71e7d3cb6e55 ("dmaengine: ls2x-apb: New driver for the Loongson LS2X APB DMA controller") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/all/87cdc025-7246-4548-85ca-3d36fdc2be2d@stanley.mountain/ Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/20241028093413.1145820-1-zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: dw: Select only supported masters for ACPI devicesAndy Shevchenko
The recently submitted fix-commit revealed a problem in the iDMA 32-bit platform code. Even though the controller supported only a single master the dw_dma_acpi_filter() method hard-coded two master interfaces with IDs 0 and 1. As a result the sanity check implemented in the commit b336268dde75 ("dmaengine: dw: Add peripheral bus width verification") got incorrect interface data width and thus prevented the client drivers from configuring the DMA-channel with the EINVAL error returned. E.g., the next error was printed for the PXA2xx SPI controller driver trying to configure the requested channels: > [ 164.525604] pxa2xx_spi_pci 0000:00:07.1: DMA slave config failed > [ 164.536105] pxa2xx_spi_pci 0000:00:07.1: failed to get DMA TX descriptor > [ 164.543213] spidev spi-SPT0001:00: SPI transfer failed: -16 The problem would have been spotted much earlier if the iDMA 32-bit controller supported more than one master interfaces. But since it supports just a single master and the iDMA 32-bit specific code just ignores the master IDs in the CTLLO preparation method, the issue has been gone unnoticed so far. Fix the problem by specifying the default master ID for both memory and peripheral devices in the driver data. Thus the issue noticed for the iDMA 32-bit controllers will be eliminated and the ACPI-probed DW DMA controllers will be configured with the correct master ID by default. Cc: stable@vger.kernel.org Fixes: b336268dde75 ("dmaengine: dw: Add peripheral bus width verification") Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware") Reported-by: Ferry Toth <fntoth@gmail.com> Closes: https://lore.kernel.org/dmaengine/ZuXbCKUs1iOqFu51@black.fi.intel.com/ Reported-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Closes: https://lore.kernel.org/dmaengine/ZuXgI-VcHpMgbZ91@black.fi.intel.com/ Tested-by: Ferry Toth <fntoth@gmail.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20241104095142.157925-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: idxd: Remove a useless mutexChristophe JAILLET
ida_alloc()/ida_free() don't need any mutex, so remove this one. It was introduced by commit e6fd6d7e5f0f ("dmaengine: idxd: add a device to represent the file opened"). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/e08df764e7046178ada4ec066852c0ce65410373.1730547933.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: xilinx_dma: Configure parking registers only if parking enabledMarek Vasut
The VDMA can work in two modes, parking or circular. Do not program the parking mode registers in case circular mode is used, it is useless. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://lore.kernel.org/r/20241031171132.56861-1-marex@denx.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: xilinx: xdma: remove redundant check on retColin Ian King
The variable ret is being checked for an error and returning ret and the following statement returns ret too. The if check is redundant, and remove it. Just return the value returned from the call to regmap_write. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20241107114656.17611-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dt-bindings: dma: qcom,gpi: Add SA8775P compatibleKonrad Dybcio
Add a compatible for the GPI DMA controller on SA8775P. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241108-topic-sa8775_dma2-v1-1-1d3b0d08d153@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dt-bindings: dma: qcom,gpi: Add QCS8300 compatibleViken Dadhaniya
Document compatible for GPI DMA controller on QCS8300 platform. Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241112041252.351266-1-quic_vdadhani@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dmaengine: at_xdmac: avoid null_prt_deref in at_xdmac_prep_dma_memsetChen Ridong
The at_xdmac_memset_create_desc may return NULL, which will lead to a null pointer dereference. For example, the len input is error, or the atchan->free_descs_list is empty and memory is exhausted. Therefore, add check to avoid this. Fixes: b206d9a23ac7 ("dmaengine: xdmac: Add memset support") Signed-off-by: Chen Ridong <chenridong@huawei.com> Link: https://lore.kernel.org/r/20241029082845.1185380-1-chenridong@huaweicloud.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-02dt-bindings: dma: qcom,gpi: Add QCS615 compatibleViken Dadhaniya
Document compatible for GPI DMA controller on QCS615 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> Link: https://lore.kernel.org/r/20241115092854.1877369-1-quic_vdadhani@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-01Linux 6.13-rc1v6.13-rc1Linus Torvalds
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