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2019-08-21drm/amd/display: remove duplicated include from dc_link.cYueHaibing
Remove duplicated include. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: remove duplicated include from gfx_v9_0.cYueHaibing
Remove duplicated include. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: remove set but not used variable 'psp_enabled'YueHaibing
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_common_early_init': drivers/gpu/drm/amd/amdgpu/nv.c:471:7: warning: variable 'psp_enabled' set but not used [-Wunused-but-set-variable] It's not used since inroduction in commit c6b6a42175f5 ("drm/amdgpu: add navi10 common ip block (v3)") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Fix 32-bit divide error in wait_for_alt_modeNathan Chancellor
When building arm32 allyesconfig: ld.lld: error: undefined symbol: __aeabi_uldivmod >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a time_taken_in_ns is of type unsigned long long so we need to use div_u64 to avoid this error. Fixes: b5b1f4554904 ("drm/amd/display: Enable type C hotplug") Reported-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: prevent memory leaks in AMDGPU_CS ioctlNicolai Hähnle
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the allocated array as well as the reference counts of sync objects are leaked. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Lock the CRTC when setting CRC sourceNicholas Kazlauskas
[Why] We need to ensure that we're holding the lock on the CRTC when setting the CRC source since we're modifying the CRTC state directly. We also need to wait for any outstanding non-blocking commits to finish so they aren't reading state that's potentially being modified - non-blocking commits don't hold the CRTC lock while doing commit tail work. [How] Lock the CRTC using its mutex. While holding the lock check if there's any commit active on the CRTC - if there is, it's non-blocking and we should wait until it's finished by waiting for hw_done to be signaled since that's the last point where we touch CRTC state. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Split out DC programming for CRC captureNicholas Kazlauskas
[Why] Calling amdgpu_dm_crtc_set_crc_source in amdgpu_dm directly has the consequence of adding additional vblank references or starting DPRX CRC capture more than once without calling stop first. Vblank references for CRC capture should be managed entirely by opening and closing the CRC file from userspace. Stream state also shouldn't be required on the CRC so we can close the file after the CRTC has been disabled. [How] Do DC programming required for configuring CRC capture separately from setting the source. Whenever we re-enable or reset a CRC this programming should be reapplied. CRC vblank reference handling in amdgpu_dm can be entirely dropped after this. Stream state also no longer needs to be required since we can just defer the programming to when the stream is actually enabled. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Use connector list for finding DPRX CRC auxNicholas Kazlauskas
[Why] This change is a refactor in preparation for adding locking and removing the requirement for a stream state on the CRTC for enabling CRC capture to fix igt@kms_plane_multiple@* warnings. [How] We can get the aux by finding the matching connector for the CRTC with the assumption that we're not doing cloning. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Check return code for CRC drm_crtc_vblank_getNicholas Kazlauskas
[Why] The call to drm_crtc_vblank_get can fail if vblank is disabled and we try to increment the reference. Since drm_crtc_vblank_get internally drops the reference when it fails it means the subsequent drm_crtc_vblank_put(...) when closing the file drops a zero reference. This was found via igt@kms_plane@pixel-format-pipe-A-planes. [How] Check the return code and return it on failure. We wouldn't have been able to enable CRC reading anyway since vblank wasn't enabled. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/amdgpu: disable MMHUB PG for navi10Kenneth Feng
Disable MMHUB PG for navi10 according to the production requirement. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: correct typoEvan Quan
"COMPUTE" was wrongly spelled as "CUSTOM". Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: correct SW smu11 thermal range settingsEvan Quan
Problems with current settings: 1. The min value was overrided to 0 on Vega20 & Navi10. While the expected should be -273.15 C. 2. The thermal min/max threshold was output in wrong unit on Navi10 & Arcturus. As TEMP_RANGE_MIN/MAX is already in millicelsius. And "*1000" in smu_v11_0_start_thermal_control makes the output wrongly. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: set Arcturus default fclk as bootup value on dpm disabledEvan Quan
On fclk dpm disabled, the default dpm table will be setup with only one level and clock frequency as bootup value. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: get bootup fclk valueEvan Quan
This is available with firmwareinfo table v3.2 or later. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: expose supported clock domains only through sysfsEvan Quan
Do not expose those unsupported clock domains through sysfs on Arcturus. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: update Arcturus smc fw and driver interface headerEvan Quan
Update smc fw and driver interface header. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: remove duplicate macro smu_get_uclk_dpm_states in ↵Kevin Wang
amdgpu_smu.h remove duplicate macro smu_get_uclk_dpm_states in amdgpu_smu.h " #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \ ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0) #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \ ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0) #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \ ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0) " Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: fix variable type errors in smu_v11_0_setup_pptableKevin Wang
fix size type errors, from uint32_t to uint16_t. it will cause only initializes the highest 16 bits in smu_get_atom_data_table function. bug report: This fixes the following static checker warning. drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:390 smu_v11_0_setup_pptable() warn: passing casted pointer '&size' to 'smu_get_atom_data_table()' 32 vs 16. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/powerplay: add smu_smc_read_sensor support for arcturusKevin Wang
the bellow patch refine the sensor read sequence, but missed to add arcuturs support. (arcuturs_ppt.c) it will cause some sensor is not supported in arcturus. drm/amd/powerplay: change smu_read_sensor sequence in smu Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'Christophe JAILLET
'_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use '_navi12_ip_offset_HEADER' instead here. Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu/psp: move TMR to cpu invisible vram regionTianci.Yin
so that more visible vram can be available for umd. Reviewed-by: Christian König <christian.koenig@amd.com>. Signed-off-by: Tianci.Yin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: remove redundant argument for psp_funcs::cmd_submit callbackXiaojie Yuan
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdkfd: Fill the name field in node topology with asic name v2Yong Zhao
The name field in node topology has not been used. We re-purpose it to hold the asic name, which can be queried by user space applications through sysfs. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: Set no-retry as default.Feifei Xu
This is to improve performance. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Tested-by: Candice Li <candice.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: add firmware header printing for psp fw loading (v2)Xiaojie Yuan
firmware header information is printed for direct fw loading but not added for psp fw loading yet v2: squash in warning fix (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: fix debug level for ppt offset/sizeXiaojie Yuan
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu: remove special autoload handling for navi12Xiaojie Yuan
s/r list in rlc firmware is ready, so remove the special autoload handling Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Calculate bpc based on max_requested_bpcNicholas Kazlauskas
[Why] The only place where state->max_bpc is updated on the connector is at the start of atomic check during drm_atomic_connector_check. It isn't updated when adding the connectors to the atomic state after the fact. It also doesn't necessarily reflect the right value when called in amdgpu during mode validation outside of atomic check. This can cause the wrong bpc to be used even if the max_requested_bpc is the correct value. [How] Don't rely on state->max_bpc reflecting the real bpc value and just do the min(...) based on display info bpc and max_requested_bpc. Fixes: 01933ba42d3d ("drm/amd/display: Use current connector state if NULL when checking bpc") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amdgpu/gfx9: update pg_flags after determining if gfx off is possibleAlex Deucher
We need to set certain power gating flags after we determine if the firmware version is sufficient to support gfxoff. Previously we set the pg flags in early init, but we later we might have disabled gfxoff if the firmware versions didn't support it. Move adding the additional pg flags after we determine whether or not to support gfxoff. Fixes: 005440066f92 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Tested-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com>
2019-08-15drm/amdgpu: Use new mode2 reset interface for RV.Andrey Grodzovsky
Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/poweplay: Add amd_pm_funcs callback for mode 2Andrey Grodzovsky
Add callback to call the new mode2 reset interface. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/powerpay: Implement mode2 reset callback for SMU10Andrey Grodzovsky
Add implmenetion. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/powerplay: add mode2 reset callback for pp_smu_mgrAndrey Grodzovsky
Also define reset modes (0, 1 and 2) Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSGAndrey Grodzovsky
By comparing to windows it means ASIC reset. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15dmr/amdgpu: Fix compile error with CONFIG_DRM_AMDGPU_GART_DEBUGFSAndrey Grodzovsky
Double defintion of 'i' Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/powerplay/smu7: enforce minimal VBITimeout (v2)Ahzo
This fixes screen corruption/flickering on 75 Hz displays. v2: make print statement debug only (Alex) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102646 Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Ahzo <Ahzo@tutanota.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/amdgpu: Update VM function pointerGang Ba
When VM state changed and system in large bar mode, make sure to use CPU update function, otherwise use SDMA function. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Gang Ba <gaba@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdkfd: Fill amdgpu_task_info for KFD VMsYong Zhao
The amdgpu_task_info will be used when printing VM page fault for KFD processes. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Harish Kasiviswanathan <harish.kasiviswanatha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Set VM_L2_CNTL.PDE_FAULT_CLASSIFICATION to 0 for GFX10Yong Zhao
We have done this for pre-GFX10 asics, but GFX10 did not pick up the new change. The below is the commit message for that change. This is recommended by HW designers. Previously when it was set to 1, the PDE walk error in VM fault will be treated as PERMISSION_OR_INVALID_PAGE_FAULT rather than usually expected OTHER_FAULT. As a result, the retry control in VM_CONTEXT*_CNTL will change accordingly. The above behavior is kind of abnormal. Furthermore, the PDE_FAULT_CLASSIFICATION == 1 feature was targeted for very old ASICs and it never made it way to production. Therefore, we should set it to 0. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Add more page fault info printing for GFX10Yong Zhao
The printing we did for GFX9 was not propogated to GFX10 somehow, so fix it now. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Add printing for RW extracted from VM_L2_PROTECTION_FAULT_STATUSYong Zhao
RW is also useful in most cases. Signed-off-by: Yong Zhao <Yong.Zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdkfd/gfx10: Calling amdgpu functions to invalidate TLBOak Zeng
Calling amdgpu function to invalidate TLB, instead of using a kfd implementation. Delete the kfd local TLB invalidation implementation. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amdgpu: Export function to flush TLB of specific vm hubOak Zeng
This is for kfd to reuse amdgpu TLB invalidation function. On gfx10, kfd only needs to flush TLB on gfx hub but not on mm hub. So export a function for KFD flush TLB only on specific hub. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Load NV12 SOC BB from firmwareLeo Li
[Why] Previous SOC bounding box firmware loading logic was for NV10, when we still had it in firmware. Now that it's brought into driver code, and NV12 BB is in firmware, this logic needs to be repurposed for NV12. [How] Set SOC_BOUNDING_BOX_VALID to false, and add the dcn_2_0_nv12_soc BB struct. In init_soc_bounding_box, load firmware to nv12 BB instead. In addition, conditionally update and patch the BB, depending on ASIC REV. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Enable MPO with pre-blend color processing (RGB)Michael Strauss
[Why] DCN10 performs color processing before MPC combination, causes color shift in RGB colorspaces when positive brightness offset is applied However, YCbCr is still unfixed and remains disabled [How] Add layerIndex to dc_plane_state and dc_plane_info structs Re-enable MPO when brightness is adjusted and colorspace is not YCbCr Set rear plane's brightness offset to 0 when front plane visible Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: audio cannot switch to internal when display turns offyanyan kang
[why] disable_az_endpoint has been skipped because dc->debug.az_endpoint_mute_only = true. [how] set dc->debug.az_endpoint_mute_only false when PPLIB’s PME notification function pointer is not NULL at the dcn10_resource construct function,because right now SMU/PPLIB and DAL all have the AZ D3 force PME notification implemented. AZ D3 should work. Signed-off-by: yanyan kang <Yanyan.Kang@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: check hpd before retry verify link capWenjing Liu
[why] During detection link training if a display is disconnected, the current code will retry 3 times of link training on disconnected link before giving up. [how] Before each retry check for HPD status, only retry verify link cap when HPD is still high. Also put a 10ms delay between each retry to improve the chance of success. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: enable dcn_mem_pwr as golden setting updatesCharlene Liu
Enable dcn_mem_pwr as golden setting updates Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: 3.2.46Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: fix dcn20 global sync dml param extractionDmytro Laktyushkin
Currently the paremeters are extracted as if dml is calculating using pipes as we pass them in. in reality, dml internally merges pipes into planes if pipe split is detected. This change adds reverse logic to dcn20_calculate_dlg_params so that the global sync parameters can be correctly extracted for all the pipes when pipe split is enabled. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 15:51:30 +0000