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This adds the USB controllers to the DT template of the
AST24xx and AST25xx SoCs.
This patch doesn't enable them by default on any board specific
.dts yet. This will be done when we have the necessary clock/reset
and pinmux support. In the meantime though, this will work if
u-boot configures things properly.
For the AST2400 I only added pinmux definition for port 1
which is dual USB1/USB2. There are additional USB1 only ports
that might require more work but I don't have HW to test at
hand so I'm leaving that to whoever cares.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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S2600WF is a Intel platform family with an ASPEED AST2500 BMC.
Signed-off-by: James Feist <james.feist@linux.intel.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The Inventec Lanyang is Power 9 platform with ast2500 BMC.
Signed-off-by: Brian Yang <yang.brianc.w@inventec.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Initial introduction of Portwell Neptune family equipped with
Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a
ASPEED ast2500 BMC manufactured by Portwell. Specifically, This
adds the neptune platform device tree file including the flash
layout used by the neptune machines.
Signed-off-by: Amithash Prasad <amithash@fb.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Set watchdog 2 to boot from the alternate flash chip when the watchdog
timer expires and the system is reset. This enables "brick protection."
Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Enable gpio-keys events for the checkstop and water/air cooled
gpios for use by applications on the Witherspoon system.
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Add GPIO key to check presence of PCIE E2B.
Signed-off-by: Lei YU <mine260309@gmail.com>
Acked-by: Xo Wang <xow@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Signed-off-by: Lei YU <mine260309@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Fix "make dtbs W=1" warns about missing reg or ranges property.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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fix below warning about PPI interrupts configuration:
"GIC: PPI13 is secure or misconfigured"
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Without this property, we get this boot warning:
"L2C: device tree omits to specify unified cache"
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Add interrupt-affinity property to fix below warning:
[ 0.429642] CPU PMU: Failed to parse /soc/pmu/interrupt-affinity[0]
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Control the Chromecast's two LEDs using PWM instead of GPIO pins. This
allows for variable brightness.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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On the Chromecast, the bootloader provides us with an ATAG_MEM of
start=0x01000000 and size=0x3eff8000. This is clearly incorrect, as the
range given encompasses nearly a GiB but the Chromecast only has 512MiB
of RAM! Additionally, this causes the kernel to be decompressed at
0x00008000, below the claimed beginning of RAM, and so the boot fails.
Since the existing ATAG parsing code runs before the kernel is even
decompressed and irrevocably patches the device tree, don't even try
to bypass it. Instead, use the "linux,usable-memory" property instead
of the "reg" property to define the real range. The ATAG code only
overwrites reg, but linux,usable-memory is checked first in the OF
driver, so the fact that reg gets changed makes no difference.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Valve Steam Link is a consumer device built around the Marvell BG2CD SoC.
This board file enables the UART, USB and Ethernet interfaces as well as
internal I2C and SDIO, and adds SoC voltage regulator and board-specific
GPIO restart method info.
Cc: Sam Lantinga <saml@valvesoftware.com>
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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This is useful if the board file needs to reference it.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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This adds most of the remaining Designware IP cores under APB trees in
the interest of documenting assignment of interrupts and memory ranges.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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This adds DT nodes for the Cortex-A9 MPCore SCU, local watchdog and
most importantly the global timer.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Cortex-A9 PMU has no associated memory ranges and "make dtbs W=1" warns
about missing reg or ranges property. To avoid the warning, move the PMU
node out of soc subtree to the root.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Use the correct trigger type for Cortex-A9. This was fixed for several
other SoCs since the kernel started issuing a boot-time warning.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Move device tree files as part of transition from Marvell berlin to
Synaptics berlin.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
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>From the hardware perspective, the actual pclk of the AO uarts
is the corresponding clkc_ao uart gate, not the main clock controller clk81.
This was not problem so far, because the uart_gate had
the CLK_IGNORE_UNUSED flag, which kept the gate open.
We plan to remove the CLK_IGNORE_UNUSED flag in another patch,
but before doing that, we need to fix the clock in the DTS file.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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This add the AO (Always-On part) clock DT info for Meson-AXG SoC
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[khilman: cleanup subject]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add all '1x' clocks to decon and decontv devices. Enabling those clocks
is needed to get proper display on hardware windows no 4 and 5.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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https://github.com/BayLibre/clk-meson into v4.18/dt64
First round of binding update for meson clocks targeted at v4.18
# gpg: Signature made Wed May 16 01:23:15 2018 PDT
# gpg: using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Can't check signature: No public key
* tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson:
dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
dt-bindings: clock: meson8b: export the NAND clock
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Currently there are no differences between the MACH_MESON8 and
MACH_MESON8B Kconfig symbols (except the help text). Since both
platforms are very similar (Meson8b being a slightly updated,
cost-reduced version of Meson8 which even shares some peripherals with
Meson8m2) no notable differences are expected in the future either.
Suggested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Currently there are two identical Kconfig options where only differences
are the Kconfig help text and the list of .dtbs that are built:
- MACH_MESON8
- MACH_MESON8B
Build the Meson8b .dtbs when MACH_MESON8 is selected to get rid of the
latter Kconfig symbol later.
Suggested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The i2c AO is used for the MIC daughter card of the S400 board
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add the pins related to the i2c AO controller of the meson-axg platform
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The clock specified for the i2c AO controller is the one for the EE
domain, which is incorrect as this controller needs the clock for AO
i2c controller.
Fixes: dc6f858e2690 ("ARM64: dts: meson-axg: add I2C DT info for Meson-AXG SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Remove undocumented and unused "clk_i2c" clock name and the second
interrupt from i2c nodes of meson-axg platform. Those seems to have
been copy/pasted from the vendor kernel
Fixes: dc6f858e2690 ("ARM64: dts: meson-axg: add I2C DT info for Meson-AXG SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add the UFS QMP phy node and the UFS host controller node, now that we
have working UFS and the necessary clocks in place.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b56b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This is pure-churn and should be a no-op. I'm doing it in the hopes
of reducing merge conflicts. When things are sorted in a sane way
(and by base address seems sane) then it's less likely that future
patches will cause merge conflicts.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Let's keep the reserved-memory node tidy and neat and keep it sorted
by address. This should have no functional change.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add command DB node based on the bindings example.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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The RPMh clock driver assumes that the xo_board clock is named
"xo_board", not "xo-board". Add a "clock-output-names" property to
the device tree to get the right name.
Also add the proper speed for the xo-clock as 38400000. This is
internally divided in RPMh clock driver to get "bi_tcxo" at 19200000.
After this change the clock tree in /sys/kernel/debug/clk/clk_summary
looks much better.
NOTES:
- Technically you could argue that this clock could belong in board
.dts files, not in the SoC one. However at the moment it's believed
that 100% of sdm845 boards will have an external clock at 38.4. It
can always be moved later if necessary.
- We could rename the "xo-board" device tree node to "xo_board" to
achieve the same effect as this patch. Presumably device-tree folks
would rather keep node names using dashes though.
- We could change the RPMh clock driver to use a dash to achieve the
same effect as this patch, but all other clocks in the clock tree
use underscores. It seems silly to change just this one.
Fixes: 7bafa643647f ("arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add all the necessary dt nodes to support SMEM driver
on SDM845. It also adds the required memory carveouts
so that the kernel does not access memory that is in
use.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch add the node to support APSS shared
mailbox on SDM845
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b56b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Thierry Escande <thierry.escande@linaro.org>
Tested-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Command DB provides information on shared resources like clocks,
regulators etc., probed at boot by the remote subsytem and made
available in shared memory.
Cc: devicetree@vger.kernel.org
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Lina Iyer <ilina@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch adds missing microSD card supplies, without this uSD
card will not be detected.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add device tree binding support for the QCOM GENI SE driver.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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