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AgeCommit message (Expand)Author
2022-02-17cxl/port: Fix endpoint refcount leakDan Williams
2022-02-11cxl/core: Fix cxl_device_lock() class detectionDan Williams
2022-02-11cxl/core/port: Fix unregister_port() lock assertionDan Williams
2022-02-08cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron
2022-02-08cxl/core/port: Handle invalid decodersDan Williams
2022-02-08cxl/core/port: Fix / relax decoder target enumerationDan Williams
2022-02-08tools/testing/cxl: Add a physical_node linkDan Williams
2022-02-08tools/testing/cxl: Enumerate mock decodersDan Williams
2022-02-08tools/testing/cxl: Mock one level of switchesDan Williams
2022-02-08tools/testing/cxl: Fix root port to host bridge assignmentDan Williams
2022-02-08tools/testing/cxl: Mock dvsec_ranges()Dan Williams
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky
2022-02-08cxl/core: Move target_list out of base decoder attributesDan Williams
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky
2022-02-08cxl/core/port: Add switch port enumerationDan Williams
2022-02-08cxl/memdev: Add numa_node attributeDan Williams
2022-02-08cxl/pci: Emit device serial numberDan Williams
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky
2022-02-08cxl/pci: Cache device DVSEC offsetBen Widawsky
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams
2022-02-08cxl: Prove CXL lockingDan Williams
2022-02-08cxl/core: Track port depthBen Widawsky
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky
2022-02-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky
2022-02-08cxl/decoder: Hide physical address information from non-rootDan Williams
2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky
2022-02-08cxl/pci: Add new DVSEC definitionsBen Widawsky
2022-02-08cxl: Flesh out register namesBen Widawsky
2022-02-08cxl/pci: Defer mailbox status checks to command timeoutsDan Williams
2022-02-08cxl/pci: Implement Interface Ready TimeoutBen Widawsky
2022-02-08cxl: Rename CXL_MEM to CXL_PCIBen Widawsky
2022-01-30Linux 5.17-rc2v5.17-rc2Linus Torvalds
2022-01-30Merge tag 'irq_urgent_for_v5.17_rc2_p2' of git://git.kernel.org/pub/scm/linux...Linus Torvalds
2022-01-30Merge tag 'perf_urgent_for_v5.17_rc2_p2' of git://git.kernel.org/pub/scm/linu...Linus Torvalds
2022-01-30Merge tag 'sched_urgent_for_v5.17_rc2_p2' of git://git.kernel.org/pub/scm/lin...Linus Torvalds
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