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https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V cache drivers for v6.8
The SiFive composable cache driver moves to the cache driver
subdirectory from the drivers/soc and grows support for non-coherent
cache operations. The immediate user for these is the jh7100 SoC, that
a rake of people have on VisionFive v1 or Beagle-V Starlight boards.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP
riscv: errata: Add StarFive JH7100 errata
soc: sifive: ccache: Add StarFive JH7100 support
dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
soc: sifive: shunt ccache driver to drivers/cache
Link: https://lore.kernel.org/r/20231221-catatonic-monday-d4c61283b136@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V SoC drivers for v6.8
There's only one set of changes here, the addition of "Auto Update"
support for PolarFire SoC. Auto Update is one of the ways that the FPGA
bitstream can be updated, and the only one suitable for use from Linux
as it does not immediately initiate a reboot when started.
The driver was not accepted in the FPGA manager subsystem as the update
only occurs after a reboot and makes no use of the FPGA manager
framework.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: add auto-update driver to mpfs entry
firmware: microchip: Replace of_device.h with explicit include
firmware: microchip: add PolarFire SoC Auto Update support
soc: microchip: mpfs: add auto-update subdev to system controller
soc: microchip: mpfs: print service status in warning message
soc: microchip: mpfs: enable access to the system controller's flash
dt-bindings: soc: microchip: add a property for system controller flash
firmware_loader: Expand Firmware upload error codes with firmware invalid error
Link: https://lore.kernel.org/r/20231221-droop-unblock-81e4fe14acee@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers
Amlogic drivers changes for v6.8:
- meson-sm: unmap out_base shmem in error path
- meson-sm: use dev_groups attrs for sysfs entries
* tag 'amlogic-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux:
firmware: meson-sm: unmap out_base shmem in error path
firmware: meson_sm: refactor serial sysfs entry via dev_groups attrs
Link: https://lore.kernel.org/r/a987f881-1c23-4528-9cb1-e5a875b7e7a8@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/drivers
mvebu drivers for 6.8 (part 1)
moxtet bus fixes
* tag 'mvebu-drivers-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
bus: moxtet: Add spi device table
bus: moxtet: Mark the irq as shared
Link: https://lore.kernel.org/r/87il4sbym0.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
Samsung SoC driver changes for v6.8
1. Add support for Google GS101 SoC to different drivers: clock
controller, serial and watchdog.
The clock driver changes depend on few bindings headers, which I put
in a topic branch with the bindings refactoring and GS101 support,
therefore this this pull request includes that bindings topic branch.
The rest of the bindings topic branch is not necessary here, however
keeping everything together makes it easier to share between
branches. The bindings topic branch is mostly refactoring all the
compatibles to add SoC-specific compatible followed by fallback.
2. Exynos ChipID: recognize ExynosAutov920.
* tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (40 commits)
dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
watchdog: s3c2410_wdt: Add support for Google gs101 SoC
watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro
watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit
tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data
clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support
clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix
dt-bindings: soc: samsung: usi: add google,gs101-usi compatible
dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property
dt-bindings: serial: samsung: Add google-gs101-uart compatible
dt-bindings: watchdog: Document Google gs101 watchdog bindings
dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum
dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
dt-bindings: clock: Add Google gs101 clock management unit bindings
dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD
dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD
dt-bindings: serial: samsung: add specific compatible for Tesla FSD
dt-bindings: pwm: samsung: add specific compatible for Tesla FSD
...
Link: https://lore.kernel.org/r/20231220084722.22149-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for v6.8
Support for SM8650 and X1E is added to the LLCC driver, the
LLCC_TRP_ATTR2_CFGn register stride is corrected, and a bug where for
each iteration looping over slices previous settings for dis_cap_alloc
and retain_on_pc are overwritten.
A quirk is introduced in UCSI, for implementations that does not handle
UCSI_GET_PDOS for non-PD partners. With this, USCI support is enabled by
default in pmic_glink. It is later reverted for SC8280XP due reported
errors.
A few memory leaks in error paths of qseecom are taken care of.
A small driver to expose the ADSP PDCharger ULOG debug log is
introduced, to aid debugging issues with pmic_glink.
The identiy of SM8650, PM8937 and a few DSPs are added to the Qualcomm
socinfo driver.
The Qualcomm sleep stats driver is extended to allow getting detailed
statistics about usage of various DDR states. Unfortunately this ABI
does not seem to be stable across platforms, so this addition is dropped
again while the reported problems are investigated further.
Andy is moved from MAINTAINERS to CREDITS. Thank you, Andy.
* tag 'qcom-drivers-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (34 commits)
soc: qcom: llcc: Fix LLCC_TRP_ATTR2_CFGn offset
firmware: qcom: qseecom: fix memory leaks in error paths
soc: qcom: llcc: Fix typo in kernel-doc
dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel
MAINTAINERS: qcom: move Andy Gross to credits
soc: qcom: pmic_glink: drop stray semicolons
soc: qcom: pmic_glink: disable UCSI on sc8280xp
soc: qcom: llcc: Fix dis_cap_alloc and retain_on_pc configuration
soc: qcom: pmic_pdcharger_ulog: Fix hypothetical ulog request message endianess
soc: qcom: pmic_pdcharger_ulog: Move TRACE_SYSTEM out of #if protection
soc: qcom: pmic_pdcharger_ulog: Search current directory for headers
soc: qcom: socinfo: Add few DSPs to get their image details
soc: qcom: llcc: Add missing description for members in slice config
Revert "soc: qcom: stats: Add DDR sleep stats"
dt-bindings: firmware: qcom,scm: Allow interconnect for everyone
dt-bindings: firmware: qcom,scm: document SCM on X1E80100 SoCs
soc: qcom: socinfo: Add PM8937 Power IC
soc: qcom: llcc: Add configuration data for X1E80100
dt-bindings: cache: qcom,llcc: Add X1E80100 compatible
soc: qcom: pmic_glink_altmode: fix port sanity check
...
Link: https://lore.kernel.org/r/20231219041855.732578-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers
TI SoC driver updates for v6.8
- ti_sci: Minor fixup for off by one error in debugfs_create
- k3-socinfo: Refactoring and add j721e detection, j722s
* tag 'ti-driver-soc-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
soc: ti: k3-socinfo: Add JTAG ID for J722S
soc: ti: k3-socinfo: Revamp driver to accommodate different rev structs
firmware: ti_sci: Fix an off-by-one in ti_sci_debugfs_create()
Link: https://lore.kernel.org/r/20231218153043.r5psxbjjpccusjg4@september
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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soc/drivers
arm64: ZynqMP SoC changes for 6.8
power driver:
- Move to remove_new hook
- Report error around unsupported callback
- Fix long messages
event driver:
- Fix cpu_id handling
- Fix warning message
* tag 'zynqmp-soc-for-6.8' of https://github.com/Xilinx/linux-xlnx:
soc: xilinx: Add error message for invalid payload received from IPI callback.
soc: xilinx: fix unhandled SGI warning message
soc: xilinx: fix quoted string split across lines
soc: xilinx: Fix for call trace due to the usage of smp_processor_id()
soc/xilinx: zynqmp_power: Convert to platform remove callback returning void
Link: https://lore.kernel.org/r/CAHTX3dJ=6y=vEgmH7Qqe=6TJZT=D-egKDmLLER4fS0=OHJRGZA@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers
i.MX drivers change for 6.8:
- Change imx-weim bus driver to use device_get_match_data()
* tag 'imx-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
bus: imx-weim: Use device_get_match_data()
Link: https://lore.kernel.org/r/20231216064605.876196-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers
Renesas driver updates for v6.8
- Remove duplicate setup of soc_device_attribute.family,
- Make RZ/Five depend on !DMA_DIRECT_REMAP.
* tag 'renesas-drivers-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Make RZ/Five depend on !DMA_DIRECT_REMAP
soc: renesas: Remove duplicate setup of soc_device_attribute.family
Link: https://lore.kernel.org/r/cover.1702642340.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
MediaTek soc driver updates for v6.8
This adds a refactoring of the MediaTek Smart Voltage Scaling (SVS)
driver and the addition of support for MT8186 and MT8195 in it, and
adds support for the MT8188 VDOSYS and resets in the MMSYS driver.
* tag 'mtk-soc-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (24 commits)
soc: mediatek: mtk-svs: Constify runtime-immutable members of svs_bank
soc: mediatek: mtk-svs: Use ULONG_MAX to compare floor frequency
soc: mediatek: mtk-svs: Check if SVS mode is available in the beginning
soc: mediatek: mtk-svs: Cleanup of svs_probe() function
soc: mediatek: mtk-svs: Compress of_device_id entries
soc: mediatek: mtk-svs: Remove redundant print in svs_get_efuse_data
soc: mediatek: mtk-svs: Commonize MT8192 probe function for MT8186
soc: mediatek: mtk-svs: Drop supplementary svs per-bank pointer
soc: mediatek: mtk-svs: Commonize efuse parse function for most SoCs
soc: mediatek: mtk-svs: Move t-calibration-data retrieval to svs_probe()
soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform data
soc: mediatek: mtk-svs: Add a map to retrieve fused values
soc: mediatek: mtk-svs: Change the thermal sensor device name
soc: mediatek: mtk-svs: Reduce memory footprint of struct svs_bank
soc: mediatek: mtk-svs: Build bank name string dynamically
soc: mediatek: mtk-svs: Convert sw_id and type to enumerations
soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict
soc: mediatek: Add MT8188 VDOSYS reset bit map
soc: mediatek: Support reset bit mapping in mmsys driver
soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys
...
Link: https://lore.kernel.org/r/20231212114515.121695-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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soc/drivers
PowerQUICC QMC and TSA drivers updates for v6.8
This pull request contains updates to prepare the support for the QMC
HDLC driver.
- Perform some fixes
- Add support for child devices
- Add QMC dynamic timeslot support
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.linaro.org/people/jens.wiklander/linux-tee into soc/drivers
OP-TEE kernel private shared memory optimizations
Optimize OP-TEE driver private shared memory allocated as dynamic shared
memory. Both to handle larger than one page allocations and for more
efficient memory usage.
* tag 'kern-priv-shm-for-v6.8' of https://git.linaro.org/people/jens.wiklander/linux-tee:
optee: allocate shared memory with alloc_pages_exact()
optee: add page list to kernel private shared memory
Link: https://lore.kernel.org/r/20231211115815.GA616539@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.linaro.org/people/jens.wiklander/linux-tee into soc/drivers
OP-TEE: asynchronous notifications with FF-A
Add support for asynchronous notifications in the OP-TEE FF-A driver. This
is the FF-A counterpart to the asynchronous notifications already
available in the OP-TEE SMC ABI.
* tag 'ffa-notif-for-v6.8' of https://git.linaro.org/people/jens.wiklander/linux-tee:
optee: ffa_abi: add asynchronous notifications
optee: provide optee_do_bottom_half() as a common function
Link: https://lore.kernel.org/r/20231211105249.GA587253@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.linaro.org/people/jens.wiklander/linux-tee into soc/drivers
OP-TEE add reserved system thread
Add support for a reserved system thread in the SMC-ABI of the OP-TEE driver.
SCMI with OP-TEE transport uses this to guarantee that it will always have
a thread available in the secure world.
* tag 'system-thread-for-v6.8' of https://git.linaro.org/people/jens.wiklander/linux-tee:
firmware: arm_scmi: optee: use optee system invocation
tee: optee: support tracking system threads
tee: system session
tee: optee: system thread call property
Link: https://lore.kernel.org/r/20231211102600.GA571787@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into soc/drivers
HiSilicon driver updates for v6.8
- Add support for the platform with PCC type3 and interrupt ack
- Few cleanups and improvements: correct the format of some strings and domain typo,
add failure log
* tag 'hisi-drivers-for-6.8' of https://github.com/hisilicon/linux-hisi:
soc: hisilicon: kunpeng_hccs: Support the platform with PCC type3 and interrupt ack
doc: kunpeng_hccs: Fix incorrect email domain name
soc: hisilicon: kunpeng_hccs: Remove an unused blank line
soc: hisilicon: kunpeng_hccs: Add failure log for no _CRS method
soc: hisilicon: kunpeng_hccs: Fix some incorrect format strings
Link: https://lore.kernel.org/r/6572C41B.6050703@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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According to documentation, it has increments of 4, not 8.
Fixes: c72ca343f911 ("soc: qcom: llcc: Add v4.1 HW version support")
Reported-by: Unnathi Chalicheemala <quic_uchalich@quicinc.com>
Reviewed-by: Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231012160509.184891-1-abel.vesa@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Fix instances of returning error codes directly instead of jumping to
the relevant labels where memory allocated for the SCM calls would be
freed.
Fixes: 759e7a2b62eb ("firmware: Add support for Qualcomm UEFI Secure Application")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Closes: https://lore.kernel.org/r/202311270828.k4HGcjiL-lkp@intel.com/
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Maximilian Luz <luzmaximilian@gmail.com>
Tested-by: Deepti Jaggi <quic_djaggi@quicinc.com> #sa8775p-ride
Link: https://lore.kernel.org/r/20231127141600.20929-2-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The gs101 clock defines from the bindings header are derived from the
clock register names found in the datasheet under some certain rules.
The CMU TOP gate clock defines missed to include the required "CMU"
differentiator which will cause collisions with the gate clock defines
of other clock units. Rename the TOP gate clock defines to include "CMU".
Update the clock driver to use the new defines in order to not break
compilation and bisect-ability. There are no device trees that use the
previous defines.
Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings")
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231218064333.479885-1-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Fixed spelling of "descriptor".
Signed-off-by: Ghanshyam Agrawal <ghanshyam1898@gmail.com>
Link: https://lore.kernel.org/r/20231215070707.560350-1-ghanshyam1898@gmail.com
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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side channel
Document the Always-On Subsystem side channel on the X1E80100 Platform.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231214-x1e80100-soc-qcom-aoss-v1-1-94c46c5182fd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Andy's last emails related to Qualcomm SoC ARM subarchitecture are from
November 2019, so move him to credits. Stale maintainer entries hide
information whether subsystem needs help, has a bus-factor or is even
orphaned.
Link: https://lore.kernel.org/all/?q=f%3A%22Andy+Gross%22
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231211155533.106003-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Similar to the Renesas RZ/Five[1] the JH7100 SoC needs the non-portable
CONFIG_DMA_GLOBAL_POOL enabled which is incompatible with DMA_DIRECT_REMAP
selected by RISCV_ISA_ZICBOM.
[1]: commit 31b2daea0764 ("soc: renesas: Make RZ/Five depend on !DMA_DIRECT_REMAP")
Link: https://lore.kernel.org/all/24942b4d-d16a-463f-b39a-f9dfcb89d742@infradead.org/
Fixes: 64fc984a8a54 ("riscv: errata: Add StarFive JH7100 errata")
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Drop stray semicolons after function definitions to avoid having this be
reproduced elsewhere.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20231208125827.10363-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enabling UCSI on sc8280xp and the Lenovo ThinkPad X13s in particular
results in a number of errors and timeouts during boot:
[ 9.012421] ucsi_glink.pmic_glink_ucsi pmic_glink.ucsi.0: GET_CONNECTOR_STATUS failed (-95)
[ 14.047379] ucsi_glink.pmic_glink_ucsi pmic_glink.ucsi.0: timeout waiting for UCSI sync write response
[ 14.050708] ucsi_glink.pmic_glink_ucsi pmic_glink.ucsi.0: GET_CONNECTOR_STATUS failed (-110)
[ 20.192382] ucsi_glink.pmic_glink_ucsi pmic_glink.ucsi.0: timeout waiting for UCSI sync write response
[ 20.192542] ucsi_glink.pmic_glink_ucsi pmic_glink.ucsi.0: GET_CONNECTOR_STATUS failed (-110)
Disable UCSI on sc8280xp until this has been resolved.
Fixes: 4db09e7b967b ("soc: qcom: pmic_glink: enable UCSI by default)
Link: https://lore.kernel.org/r/ZXL5jvDHr-MuxMoz@hovoldconsulting.com
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231208125730.10323-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Commit c14e64b46944 ("soc: qcom: llcc: Support chipsets that can
write to llcc") add the support for chipset where capacity based
allocation and retention through power collapse can be programmed
based on content of SCT table mentioned in the llcc driver where
the target like sdm845 where the entire programming related to it
is controlled in firmware. However, the commit introduces a bug
where capacity/retention register get overwritten each time it
gets programmed for each slice and that results in misconfiguration
of the register based on SCT table and that is not expected
behaviour instead it should be read modify write to retain the
configuration of other slices.
This issue is totally caught from code review and programming test
and not through any power/perf numbers so, it is not known what
impact this could make if we don't have this change however,
this feature are for these targets and they should have been
programmed accordingly as per their configuration mentioned in
SCT table like others bits information.
This change brings one difference where it keeps capacity/retention
bits of the slices that are not mentioned in SCT table in unknown
state where as earlier it was initialized to zero.
Fixes: c14e64b46944 ("soc: qcom: llcc: Support chipsets that can write to llcc")
Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1701876771-10695-1-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Sparse reports the following:
% ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make C=2 W=1 drivers/soc/qcom/pmic_pdcharger_ulog.o
...
CC drivers/soc/qcom/pmic_pdcharger_ulog.o
CHECK drivers/soc/qcom/pmic_pdcharger_ulog.c
drivers/soc/qcom/pmic_pdcharger_ulog.c:57:34: warning: incorrect type in initializer (different base types)
drivers/soc/qcom/pmic_pdcharger_ulog.c:57:34: expected restricted __le32 [usertype] owner
drivers/soc/qcom/pmic_pdcharger_ulog.c:57:34: got int
drivers/soc/qcom/pmic_pdcharger_ulog.c:58:33: warning: incorrect type in initializer (different base types)
drivers/soc/qcom/pmic_pdcharger_ulog.c:58:33: expected restricted __le32 [usertype] type
drivers/soc/qcom/pmic_pdcharger_ulog.c:58:33: got int
drivers/soc/qcom/pmic_pdcharger_ulog.c:59:35: warning: incorrect type in initializer (different base types)
drivers/soc/qcom/pmic_pdcharger_ulog.c:59:35: expected restricted __le32 [usertype] opcode
drivers/soc/qcom/pmic_pdcharger_ulog.c:59:35: got int
Let's deal with endianness conversion in the rare case this ever runs
on a big-endian machine (and to quiet down sparse for this file).
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202312060355.M0eJtq4X-lkp@intel.com/
Fixes: 086fdb48bc65 ("soc: qcom: add ADSP PDCharger ULOG driver")
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231205-pmicpdcharger-ulog-fixups-v1-3-71c95162cb84@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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As specified in samples/trace_events/trace-events-sample.h:
* Notice that TRACE_SYSTEM should be defined outside of #if
* protection, just like TRACE_INCLUDE_FILE.
Fixes: 086fdb48bc65 ("soc: qcom: add ADSP PDCharger ULOG driver")
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231205-pmicpdcharger-ulog-fixups-v1-2-71c95162cb84@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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As specified in samples/trace_events/Makefile:
If you include a trace header outside of include/trace/events
then the file that does the #define CREATE_TRACE_POINTS must
have that tracer file in its main search path. This is because
define_trace.h will include it, and must be able to find it from
the include/trace directory.
Without this the following compilation error is seen:
CC drivers/soc/qcom/pmic_pdcharger_ulog.o
In file included from drivers/soc/qcom/pmic_pdcharger_ulog.h:36,
from drivers/soc/qcom/pmic_pdcharger_ulog.c:15:
./include/trace/define_trace.h:95:42: fatal error: ./pmic_pdcharger_ulog.h: No such file or directory
95 | #include TRACE_INCLUDE(TRACE_INCLUDE_FILE)
| ^
compilation terminated.
Fixes: 086fdb48bc65 ("soc: qcom: add ADSP PDCharger ULOG driver")
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231205-pmicpdcharger-ulog-fixups-v1-1-71c95162cb84@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add support to get image details from SMEM for DSPs like
DSPS (Sensors DSP), CDSP (Compute DSP), GPDSP (General purpose DSP)
while also supporting this for more than one DSP of certain types.
Signed-off-by: Naman Jain <quic_namajain@quicinc.com>
Link: https://lore.kernel.org/r/20231205101018.6079-1-quic_namajain@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Fix all warnings thrown due to missing description for some of the
members in llcc_slice_config.
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202312050519.mup4Q8mD-lkp@intel.com/
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20231205-llcc-fix-slice-config-warnings-v1-1-d6331d601dd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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After recent reports ([1], [2]) of older platforms (particularly 8150 and
7180) breaking after DDR sleep stats introduction, revert the following:
Commit 73380e2573c3 ("soc: qcom: stats: fix 64-bit division")
Commit e84e61bdb97c ("soc: qcom: stats: Add DDR sleep stats")
The feature itself is rather useful for debugging DRAM power management,
however it looks like the shared RPMh stats data structures differ on
previous SoCs.
Revert its addition for now to un-break booting on these earlier SoCs,
while I try to come up with a better way to enable it conditionally.
[1] https://lore.kernel.org/linux-arm-msm/20231209215601.3543895-2-dmitry.baryshkov@linaro.org/
[2] https://lore.kernel.org/linux-arm-msm/CAD=FV=XX4wLg1NNVL15RK4D4tLvuSzZyUv=k_tS4bSb3=7QJzQ@mail.gmail.com/
Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20231214-topic-undo_ddr_stats-v1-1-1fe32c258e56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The moxtet module fails to auto-load on. Add a SPI id table to
allow it to do so.
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Cc: <stable@vger.kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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The Turris Mox shares the moxtet IRQ with various devices on the board,
so mark the IRQ as shared in the driver as well.
Without this loading the module will fail with:
genirq: Flags mismatch irq 40. 00002002 (moxtet) vs. 00002080 (mcp7940x)
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Cc: <stable@vger.kernel.org> # v6.2+
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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This patch adds the compatibles and drvdata for the Google
gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones.
Similar to Exynos850 it has two watchdog instances, one for
each cluster and has some control bits in PMU registers.
gs101 also has the dbgack_mask bit in wtcon register, so
we also enable QUIRK_HAS_DBGACK_BIT.
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20231211162331.435900-13-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Update the remaining QUIRK macros to use the BIT macro.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-12-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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The WDT uses the CPU core signal DBGACK to determine whether the SoC
is running in debug mode or not. If the DBGACK signal is asserted and
DBGACK_MASK bit is enabled, then WDT output and interrupt is masked
(disabled).
Presence of the DBGACK_MASK bit is determined by adding a new
QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid
checkpatch --strict warnings.
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-11-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Randy reported yet another build issue with randconfigs on rv32:
WARNING: unmet direct dependencies detected for DMA_GLOBAL_POOL
Depends on [n]: !ARCH_HAS_DMA_SET_UNCACHED [=n] && !DMA_DIRECT_REMAP [=y]
Selected by [y]:
- ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && RISCV_ALTERNATIVE [=y] && !RISCV_ISA_ZICBOM [=n] && RISCV_SBI [=y]
This happens when DMA_DIRECT_REMAP is selected by the T-Head CMO erratum
option and DMA_GLOBAL_POOL is selected by the Andes CMO erratum. Block
selecting the RZ/Five config option, and by extension DMA_GLOBAL_POOL,
if DMA_DIRECT_REMAP has already been enabled.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Closes: https://lore.kernel.org/all/24942b4d-d16a-463f-b39a-f9dfcb89d742@infradead.org/
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231211-primate-arbitrate-fbcd307a0b00@spud
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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As of commit 3f84aa5ec052dba9 ("base: soc: populate machine name in
soc_device_register if empty") in v6.4, soc_device_register() fills in
soc_device_attribute.family when it is still empty. Hence the identical
code in renesas_soc_init() doing the same can be removed.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4c5e4d0d1819028466748ed684254fec41aae816.1701696627.git.geert+renesas@glider.be
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payload[0] of response buffer of zynqmp_pm_get_callback_data()
contains valid payload or error code in case of error.
Added error message to inform user about the error code received in
payload[0].
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/85749bde3e71148533d31ea2092f4514ec347768.1701962639.git.michal.simek@amd.com
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This not really an errata, but since the JH7100 was made before
the standard Zicbom extension it needs the DMA_GLOBAL_POOL and
RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add JTAG ID info for the J722S SoC family to enable SoC detection.
More details about this SoC can be found in the TRM:
https://www.ti.com/lit/zip/sprujb3
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20231211132600.25289-1-vaishnav.a@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
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Add serial driver data for Google Tensor gs101 SoC and a common
fifoszdt_serial_drv_data that can be used by platforms that specify the
samsung,uart-fifosize DT property.
A corresponding dt-bindings patch updates the yaml to ensure
samsung,uart-fifosize is a required property.
Tested-by: Will McVicker <willmcvicker@google.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-14-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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cmu_top is the top level clock management unit which contains PLLs, muxes,
dividers and gates that feed the other clock management units.
cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the
APM module.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-9-peter.griffin@linaro.org
[krzysztof: drop not needed linux/of_device.h include]
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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These plls are found in the Tensor gs101 SoC found in the Pixel 6.
pll0516x: Integer PLL with high frequency
pll0517x: Integer PLL with middle frequency
pll0518x: Integer PLL with low frequency
PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)
The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.
Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
When defining the PLL the "con" parameter should be set to CON3
register, like this
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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next/drivers
Samsung Devicetree bindings topic branch for v6.8
Topic branch collecting several changes to Samsung SoC Devicetree
bindings:
1. Add specific compatibles to all Samsung Exynos and Tesla FSD blocks,
because that's what guidelines expect [1] and is generally
recommended practice. Existing compatibles are left untouched, thus
no driver changes are needed. The work only cleans things up, so any
future contributions will use recommended style: specific and
fallback compatibles.
2. Add bindings for new devices: Samsung ExynosAutov920 and Google
GS101.
These bindings are needed for both DTS and drivers, e.g. clock drivers.
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166 was skipped by mistake and two clocks:
* CLK_MOUT_CMU_HSI0_USBDPDGB
* CLK_GOUT_HSI0_USBDPDGB
Have an incorrect DGB ending instead of DBG.
This is an ABI break, but as the patch was only applied yesterday this
header has never been in an actual release so it seems better to fix
this early than ignore it.
Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings")
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-7-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add google,gs101-usi dedicated compatible for representing USI of Google
GS101 SoC.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-6-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Specifying samsung,uart-fifosize in both DT and driver static data is error
prone and relies on driver probe order and dt aliases to be correct.
Additionally on many Exynos platforms these are (USI) universal serial
interfaces which can be uart, spi or i2c, so it can change per board.
For google,gs101-uart make samsung,uart-fifosize a required property.
For this platform fifosize now *only* comes from DT.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-5-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add dedicated google-gs101-uart compatible to the dt-schema for
representing uart of the Google Tensor gs101 SoC.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-4-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
