summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-08-11spi: dt-bindings: Drop Pratyush YadavKrzysztof Kozlowski
Emails to Pratyush Yadav bounce ("550 Invalid recipient"). Generic SPI properties should be maintained by subsystem maintainer (Mark). Add recent contributor Vaishnav Achath to the Cadence SPI bindings. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220811063826.7620-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-11spi: meson-spicc: add local pow2 clock ops to preserve rate between messagesNeil Armstrong
At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(), this resets the SPICC_CONREG register and notably the value set by the Common Clock Framework. This is problematic because: - the register value CCF can be different from the corresponding CCF cached rate - CCF is allowed to change the clock rate whenever the HW state This introduces: - local pow2 clock ops checking the HW state before allowing a clock operation - separation of legacy pow2 clock patch and new enhanced clock path - SPICC_CONREG datarate value is now value kepts across messages It has been checked that: - SPICC_CONREG datarate value is kept across messages - CCF is only allowed to change the SPICC_CONREG datarate value when busy - SPICC_CONREG datarate value is correct for each transfer This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") because we recalculated and wrote the rate for each xfer. Fixes: 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220811134445.678446-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-05MAINTAINERS: rectify entry for ARM/HPE GXP ARCHITECTURELukas Bulwahn
Commit 8cc35b86546d ("spi: dt-bindings: add documentation for hpe,gxp-spifi") adds the spi dt-binding file hpe,gxp-spifi.yaml and commit a1848b0fa251 ("MAINTAINERS: add spi support to GXP") adds a file entry hpe,gxp-spi.yaml in ARM/HPE GXP ARCHITECTURE. Note the different file name. Hence, ./scripts/get_maintainer.pl --self-test=patterns complains about a broken reference. Repair this file reference in ARM/HPE GXP ARCHITECTURE. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220804161823.20912-1-lukas.bulwahn@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-05spi: spi.c: Add missing __percpu annotations in users of spi_statisticsDavid Jander
Fixes sparse warnings of this kind: drivers/spi/spi.c:117:16: sparse: expected struct spi_statistics * drivers/spi/spi.c:117:16: sparse: got struct spi_statistics [noderef] __percpu *[assigned] pcpu_stats Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220805084458.1602277-1-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-29Add SPI Driver to HPE GXP ArchitectureMark Brown
Merge series from nick.hawkins@hpe.com <nick.hawkins@hpe.com>: The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part.
2022-07-29MAINTAINERS: add spi support to GXPNick Hawkins
Add the spi driver and dt-binding documentation Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-6-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-29spi: dt-bindings: add documentation for hpe,gxp-spifiNick Hawkins
Create documentation for the hpe,gxp-spifi binding to support access to the SPI parts Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220728161459.7738-3-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-29spi: spi-gxp: Add support for HPE GXP SoCsNick Hawkins
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-26spi: a3700: support BE for AC5 SPI driverNoam
Signed-off-by: Noam <lnoam@marvell.com> Tested-by: Raz Adashi <raza@marvell.com> Reviewed-by: Raz Adashi <raza@marvell.com> Signed-off-by: Vadym Kochan <vadym.kochan@plvision.eu> Link: https://lore.kernel.org/r/20220726130038.20995-1-vadym.kochan@plvision.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-26spi/panel: dt-bindings: drop CPHA and CPOL from common propertiesKrzysztof Kozlowski
The spi-cpha and spi-cpol properties are device specific and should be accepted only if device really needs them. Drop them from common spi-peripheral-props.yaml schema, mention in few panel drivers which use them and include instead in the SPI controller bindings. The controller bindings will provide CPHA/CPOL type validation and one place for description. Each device schema must list the properties if they are applicable. Suggested-by: Jonathan Cameron <jic23@kernel.org> Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220722191539.90641-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-25spi: bcm2835: enable shared interrupt supportMartin Sperl
BCM2711 shares an interrupt betweem 5 SPI interfaces (0, 3, 4, 5 & 6). Another interrupt is shared between SPI1, SPI2 and UART1, which also affects BCM2835/6/7. Acting on an interrupt intended for another interface ought to be harmless (although potentially inefficient), but it can cause this driver to crash - presumably because some critical state is not ready. Add a test to the spi-bcm2835 interrupt service routine that interrupts are enabled on this interface to avoid the crash and improve efficiency. Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Link: https://github.com/raspberrypi/linux/issues/5048 Suggested-by: https://github.com/boe-pi Co-developed-by: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Phil Elwell <phil@raspberrypi.com> Cc: Mark Brown <broonie@kernel.org> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20220719105305.3076354-1-mkl@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-22spi: dt-bindings: spi-controller: correct example indentationKrzysztof Kozlowski
Example DTS mixed two with four-space indentation. Preferred is four spaces, for readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220722190910.76865-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: add Arbel NPCM8XX supportMark Brown
Merge series from Tomer Maimon <tmaimon77@gmail.com>: This patch set adds Arbel NPCM8XX Flash Interface Unit (FIU) support to FIU NPCM driver and modify direct read dummy configuration. NPCM8XX FIU supports four controllers. The NPCM FIU driver tested on NPCM845 evaluation board.
2022-07-20spi: dt-bindings: qcom,spi-geni-qcom: allow three interconnectsKrzysztof Kozlowski
Recent Qualcomm Geni SPI nodes, e.g. on SM8450, come also with three interconnects. This fixes dtbs_check warnings like: sm8450-qrd.dtb: spi@a98000: interconnects: [[46, 1, 0, 46, 4, 0], [47, 2, 0, 48, 12, 0], [49, 1, 0, 50, 1, 0]] is too long sm8450-qrd.dtb: spi@a98000: interconnect-names: ['qup-core', 'qup-config', 'qup-memory'] is too long Fixes: 5bdcae1fe1c5 ("spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220720163841.7283-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: Add NPCM8XX supportTomer Maimon
Adding FIU NPCM8XX support to NPCM FIU driver. NPCM8XX FIU supports four controllers. As part of adding NPCM8XX support: - Add NPCM8XX specific compatible string. - Using an internal burst configuration register instead of a GCR register. - Support FIU1 controller. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-4-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20dt-binding: spi: Add npcm845 compatible to npcm-fiu documentTomer Maimon
Add a compatible string and description for Nuvoton BMC NPCM845 FIU. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-20spi: npcm-fiu: Modify direct read dummy configurationTomer Maimon
Modify NPCM BMC FIU direct read dummy configuration that according spi-mem direct read function. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220718081146.256070-2-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: atmel: remove #ifdef CONFIG_{PM, SLEEP}Claudiu Beznea
Remove #ifdef CONFIG_PM, #ifdef CONFIG_PM_SLEEP and use SYSTEM_SLEEP_PM_OPS() and RUNTIME_PM_OPS() macros instead which allows getting also rid of __maybe_unused in the code. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220718071052.1707858-1-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: dt-bindings: Add compatible for MediaTek MT8188Johnson Wang
This commit adds dt-binding documentation of spi bus for MediaTek MT8188 SoC platform. Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Link: https://lore.kernel.org/r/20220715120114.4243-1-johnson.wang@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-18spi: dt-bindings: mediatek,spi-mtk-nor: Update bindings for nor flashAllen-KH Cheng
The spi-mtk-nor controller of mt8173, mt8186 and mt8192 have their DT data. They don't use mt8173 as fallback. Using the fallback of mt8186 to enables the controllers to support mt8188. Not all of spi-mtk-nor controller need interrupt property, so we don't mark interrupt as required. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Link: https://lore.kernel.org/r/20220715115443.4154-1-allen-kh.cheng@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-14spi: dt-bindings: atmel,at91rm9200-spi: convert to json-schemaSergiu Moga
Convert SPI DT binding for Atmel/Microchip SoCs to json-schema. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220713132908.175026-1-sergiu.moga@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13Add support for Intel Thunder Bay SPI controllerMark Brown
Merge series from nandhini.srikandan@intel.com <nandhini.srikandan@intel.com>: This patch enables support for DW SPI on Intel Thunder Bay. This patch set also enables master mode for latest Designware SPI versions. The driver is tested on Keem Bay and Thunder Bay evaluation board.
2022-07-13spi: microchip-core: fix and cleanupsMark Brown
Merge series from Yang Yingliang <yangyingliang@huawei.com>: Patch #1 fix a UAF in mchp_corespi_remove(). Patch #2 and #3 some cleanups to simpify code.
2022-07-13spi: tegra20-slink: fix UAF in tegra_slink_remove()Yang Yingliang
After calling spi_unregister_master(), the refcount of master will be decrease to 0, and it will be freed in spi_controller_release(), the device data also will be freed, so it will lead a UAF when using 'tspi'. To fix this, get the master before unregister and put it when finish using it. Fixes: 26c863418221 ("spi: tegra20-slink: Don't use resource-managed spi_register helper") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220713094024.1508869-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: Fix simplification of devm_spi_register_controllerYang Yingliang
This reverts commit 59ebbe40fb51 ("spi: simplify devm_spi_register_controller"). If devm_add_action() fails in devm_add_action_or_reset(), devm_spi_unregister() will be called, it decreases the refcount of 'ctlr->dev' to 0, then it will cause uaf in the drivers that calling spi_put_controller() in error path. Fixes: 59ebbe40fb51 ("spi: simplify devm_spi_register_controller") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220712135504.1055688-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: switch to use dev_err_probe()Yang Yingliang
Switch to use dev_err_probe() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-4-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: switch to use devm_spi_alloc_master()Yang Yingliang
Switch to use devm_spi_alloc_master() to simpify error path. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-3-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: microchip-core: fix UAF in mchp_corespi_remove()Yang Yingliang
When using devm_spi_register_master(), the unregister function will be called in devres_release_all() which is called after ->remove(), so remove spi_unregister_master() andspi_master_put(). Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220713025657.3524506-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Add support for Intel Thunder Bay SPI controllerNandhini Srikandan
Add support for Intel Thunder Bay SPI controller, which uses DesignWare DWC_ssi core and also add common init function for both Keem Bay and Thunder Bay. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-5-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Add support for master mode selection for DWC SSI controllerNandhini Srikandan
Add support to select the controller mode as master mode by setting Bit 31 of CTRLR0 register. This feature is supported for controller versions above v1.02. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: Add bindings for Intel Thunder Bay SOCNandhini Srikandan
Add documentation for SPI controller in Intel Thunder Bay SoC. Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-3-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-13spi: dw: Fix IP-core versions macroNandhini Srikandan
Add the missing underscore in IP version macro to avoid compilation issue. The macro is used for IP version comparison in the current patchset. Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface") Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com> Acked-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20220713042223.1458-2-nandhini.srikandan@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-11spi: remove duplicate parameters check in acpi_spi_add_resource()Andy Shevchenko
The acpi_spi_add_resource() is never called with ctrl == NULL and index == -1. The only caller already performs the check. Hence remove the duplication from the acpi_spi_add_resource(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709000709.35622-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-11spi: propagate error code to the caller of acpi_spi_device_alloc()Andy Shevchenko
Since acpi_spi_device_alloc() has been designed to return an error pointer we may now properly propagate error codes to the caller of it. It helps debugging a lot. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709000709.35622-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-11spi: Return deferred probe error when controller isn't yet availableAndy Shevchenko
If the controller is not available, it might be in the future and we would like to re-probe the peripheral again. For that purpose return deferred probe. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=215993 Fixes: 87e59b36e5e2 ("spi: Support selection of the index of the ACPI Spi Resource before alloc") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220709212956.25530-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: AMD SPI controller driver bug fix and cleanupsMark Brown
Merge series from Cristian Ciocaltea <cristian.ciocaltea@collabora.com>: This patch series addresses an issue in the spi-amd driver and, while there, performs some additional cleanups, like simplifying the error handling in the probe function and removing an unused struct member. For improving code readability, it also adds some kernel-doc comments.
2022-07-06spi: amd: Add struct and enum kernel-doc commentsCristian Ciocaltea
Provide documentation comments in the kernel-doc format for enum amd_spi_versions and struct amd_spi. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-6-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Drop io_base_addr member from struct amd_spiCristian Ciocaltea
The io_base_addr member of struct amd_spi is not referenced anywhere in the driver implementation and there is no indication that it could be used in the future, hence drop it. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-5-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Make use of dev_err_probe()Cristian Ciocaltea
Simplify the error handling in probe function by switching from dev_err() to dev_err_probe(). Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-4-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Make use of devm_spi_alloc_master()Cristian Ciocaltea
Make use of the devm variant of spi_alloc_master() in order to cleanup and simplify the error handling in the probe function by getting rid of the goto statements. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-3-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-06spi: amd: Limit max transfer and message sizeCristian Ciocaltea
Enabling the SPI CS35L41 audio codec driver for Steam Deck [1] revealed a problem with the current AMD SPI controller driver implementation, consisting of an unrecoverable system hang. The issue can be prevented if we ensure the max transfer size and the max message size do not exceed the FIFO buffer size. According to the implementation of the downstream driver, the AMD SPI controller is not able to handle more than 70 bytes per transfer, which corresponds to the size of the FIFO buffer. Hence, let's fix this by setting the SPI limits mentioned above. [1] https://lore.kernel.org/r/20220621213819.262537-1-cristian.ciocaltea@collabora.com Reported-by: Anastasios Vacharakis <vacharakis@o2mail.de> Fixes: bbb336f39efc ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220706100626.1234731-2-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-04spi: dt-bindings: zynqmp-qspi: add missing 'required'Krzysztof Kozlowski
During the conversion the bindings lost list of required properties. Fixes: c58db2abb19f ("spi: convert Xilinx Zynq UltraScale+ MPSoC GQSPI bindings to YAML") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20220704130618.199231-2-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-04spi: dt-bindings: cadence: add missing 'required'Krzysztof Kozlowski
During the conversion the bindings lost list of required properties. Fixes: aa7968682a2b ("spi: convert Cadence SPI bindings to YAML") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20220704130618.199231-1-krzysztof.kozlowski@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-01spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-widthConor Dooley
Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the Canaan k210 is wired up for a width of 4. Quoting Serge: The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. /endquote As such, drop the restriction on only supporting a bus width of 1. Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Niklas Cassel <niklas.cassel@wdc.com> Link: https://lore.kernel.org/r/20220629184343.3438856-5-mail@conchuod.ie Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30Fix some coding style issuesMark Brown
Merge series from David Jander <david@protonic.nl>: This series fixes some coding style issues. No functional change.
2022-06-30spi: spi.c: Remove redundant else blockDavid Jander
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-4-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30spi: spi.c: Fix comment styleDavid Jander
Capitalize first word in comment where appropriate and add parentheses to function names. Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-3-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30spi: spi.c: White-space fix in __spi_pump_messages()David Jander
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220629142519.3985486-2-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-30spi: pxa2xx: Add support for Intel Meteor Lake-PJarkko Nikula
Add support for LPSS SPI on Intel Meteor Lake-P. It has three controllers each having two chip selects. This squashes a fix from Ap, Kamal <kamal.ap@intel.com> fixing incorrect PCI ID of 3rd controller. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220630073305.632850-1-jarkko.nikula@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-29spi support for Exynos Auto v9 SoCMark Brown
Merge series from Chanho Park <chanho61.park@samsung.com>: Add to support Exynos Auto v9 SoC's spi. By supporting USI(Universal Serial Interface) mode, the SoC can support up to 12 spi ports. Thus, we need to increase MAX_SPI_PORTS from 6 to 12. The spi of the SoC can support loopback mode unlike previous exynos SoCs. To separate the feature, we need to add .has_loopback to the s3c64xx_spi_port_config. Furthermore, it uses 4 as the default internal clock divider. We also need to clk_div field of the structure and assign "2" as the default value to the existing SoC's port config. Device tree definitions of exynosautov9-spi will be added in separated patchset to include usi(i2c/uart/spi) nodes all together.
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-31 23:17:06 +0000