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2017-04-08drm/mediatek: add non-continuous clock mode and EOT packet controlyt.shen@mediatek.com
This patch will update dsi clock control method. 1. dsi non-continue clock mode will enhance antistatic effect for panel 2. EOT packet control will judge whether dsi send end of packet or not by customize Signed-off-by: shaoming chen <shaoming.chen@mediatek.com> Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add dsi transfer functionshaoming chen
add dsi read/write commands for transfer function Signed-off-by: shaoming chen <shaoming.chen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add dsi interrupt controlshaoming chen
add dsi interrupt control Signed-off-by: shaoming chen <shaoming.chen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: cleaning up and refineyt.shen@mediatek.com
cleaning up unused define and refine function name and variable Signed-off-by: shaoming chen <shaoming.chen@mediatek.com> Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: update display module connectionsyt.shen@mediatek.com
update connections for OVL, RDMA, BLS, DSI Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add BLS componentyt.shen@mediatek.com
Add BLS component for PWM + GAMMA function Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add shadow register supportyt.shen@mediatek.com
We need to acquire mutex before using the resources, and need to release it after finished. So we don't need to write registers in the blanking period. Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add *driver_data for different hardware settingsyt.shen@mediatek.com
There are some hardware settings changed, between MT8173 & MT2701: DISP_OVL address offset changed, color format definition changed. DISP_RDMA fifo size changed. DISP_COLOR offset changed. MIPI_TX pll setting changed. And add prefix for mtk_ddp_main & mtk_ddp_ext & mutex_mod. Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08drm/mediatek: add helpers for coverting from the generic componentsyt.shen@mediatek.com
define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_ovl' define helpers for converting from 'mtk_ddp_comp' to 'mtk_disp_rdma' Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: CK Hu <ck.hu@mediatek.com>
2017-04-08dt-bindings: display: mediatek: update supported chipsyt.shen@mediatek.com
Add decriptions about supported chips, including MT2701 & MT8173 Signed-off-by: YT Shen <yt.shen@mediatek.com> Acked-by: Rob Herring <robh@kernel.org>
2017-04-07Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie
into drm-next A few more things for 4.12: - ttm and amdgpu support for non-contiguous vram CPU mappings - lots of bug fixes and cleanups for vega10 - misc bug fixes and code cleanups [airlied: fix do_div error on 32-bit arm, not sure it's 100% correct] * 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (58 commits) drm/amdgpu: use uintptr_t instead of unsigned long to store pointer drm/amdgpu: Avoid using signed integer to store pointer value drm/amdgpu:invoke new implemented AI MB func drm/amdgpu/vega10:timeout set to equal with VI drm/amdgpu:implement the reset MB func for vega10 drm/amdgpu:fix typo for mxgpu_ai drm/amdgpu:no need to involv HDP in KIQ drm/amdgpu:add PSP block only load_type=PSP (v2) drm/amdgpu/smu9: update to latest driver interface drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init() drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset() drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start() drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable() drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register() drm/amd/amdgpu: Drop gfx_v9_0_print_status() drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state() drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state() drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state() drm/amd/amdgpu: cleanup gfx_v9_0_init_queue() drm/amdgpu: Move function amdgpu_has_atpx near other similar functions ...
2017-04-07Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into ↵Dave Airlie
drm-next Highlights: - Cooling device support from Russell, to allow GPU throttling on system thermal overload. - Explicit fencing support from Philipp, implemented in a similar way to drm/msm. * 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux: drm/etnaviv: submit support for out-fences drm/etnaviv: return GPU fence through the submit structure drm/etnaviv: submit support for in-fences drm/etnaviv: add etnaviv cooling device drm/etnaviv: switch to postclose drm/etnaviv: add lockdep assert to fence allocation
2017-04-07Merge tag 'imx-drm-next-2017-04-04' of ↵Dave Airlie
git://git.pengutronix.de/git/pza/linux into drm-next imx-drm module/dependency changes - The PRE/PRG drivers added an unwanted DRM dependency to the ipu-v3 driver. Remove the dependency by conditionally disabling PRE/PRG support depending on CONFIG_DRM. - Merge the imx-ipuv3-crtc module into the imxdrm module. There is no reason anymore for a separation between core drm driver and crtc/plane drivers, especially since commit eb8c88808c83 ("drm/imx: add deferred plane disabling"), which added a dependency on imx-ipuv3-crtc to the imxdrm module. * tag 'imx-drm-next-2017-04-04' of git://git.pengutronix.de/git/pza/linux: drm/imx: merge imx-drm-core and ipuv3-crtc in one module gpu: ipu-v3: don't depend on DRM being enabled
2017-04-07Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-nextDave Airlie
A bit more for 4.12: - GP10B support - GP107 acceleration support * 'linux-4.12' of git://github.com/skeggsb/linux: (23 commits) drm/nouveau/gpio: enable interrupts on cards with 32 gpio lines drm/nouveau/gr/gp107: initial support drm/nouveau/core: recognise GP10B chipset drm/nouveau/platform: support for probing GP10B drm/nouveau/platform: make VDD regulator optional drm/nouveau/gr: support for GP10B drm/nouveau/ibus: add GP10B support drm/nouveau/mc: add GP10B support drm/nouveau/fb: add GP10B support drm/nouveau/fifo: add GP10B support drm/nouveau/msgqueue: support for GP10B PMU firmware drm/nouveau/secboot: add GP10B support drm/nouveau/secboot/gm20b: specify MC base address as argument drm/nouveau/secboot: start LS firmware in post-run hook drm/nouveau/secboot: let LS post_run hooks return error drm/nouveau/secboot: pass instance to LS firmware loaders drm/nouveau/secboot: allow to boot multiple falcons drm/nouveau/imem/gk20a: Turn instmem lock into mutex drm/nouveau: initial support (display-only) for GP107 drm/nouveau/kms/nv50: fix double dma_fence_put() when destroying plane state ...
2017-04-06drm/amdgpu: use uintptr_t instead of unsigned long to store pointerAlex Xie
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: Avoid using signed integer to store pointer valueAlex Xie
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu:invoke new implemented AI MB funcMonk Liu
Implement the sr-iov mailbox for soc15 asics. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu/vega10:timeout set to equal with VIMonk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu:implement the reset MB func for vega10Monk Liu
they are lack in the bringup stage, we need them for GPU reset feature. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu:fix typo for mxgpu_aiMonk Liu
Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu:no need to involv HDP in KIQMonk Liu
1,KIQ won't touch VRAM so no need to involv HDP flush/invalidate at all. 2,According to CP hw designer KIQ better not use any PM4 package lead to wait behave. Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu:add PSP block only load_type=PSP (v2)Monk Liu
SRIOV currently only can load ucode directly, and PSP block is not supported by VF temporarily. will remove this restrict and use PSP load all ucode even for SRIOV later v2: squash in check against module parameter Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu/smu9: update to latest driver interfaceEvan Quan
Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()Tom St Denis
Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset()Tom St Denis
Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start()Tom St Denis
Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable()Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register()Tom St Denis
Use new WREG32_FIELD macro Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Drop gfx_v9_0_print_status()Tom St Denis
It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state()Tom St Denis
Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state()Tom St Denis
Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state()Tom St Denis
Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()Tom St Denis
Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: Move function amdgpu_has_atpx near other similar functionsAlex Xie
Signed-off-by: Alex Xie <AlexBin.Xie@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: fix over allocating of IRQ sourcesChristian König
We need an array of pointers to IRQ sources, not an array of sources. Signed-off-by: Christian König <christian.koenig@amd.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Clean up psp reload_quirk()Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Fix psp_v3_1 compare sramTom St Denis
Had the wrong sense in the loop Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: cleanup get_invalidate_req v2Christian König
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: fix vm size and block size for VMPT (v5)Zhang, Jerry
Set reasonable defaults per family. v2: set both of them in gmc v3: move vm size and block size in vm manager v4: squash in warning fix from Alex Xie v5: squash in min() warning fix Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Fix srbm_indexing in init/inactive hqd codeTom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init()Tom St Denis
Clean up a toggle with ?:. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: de-numberify HQD_ACTIVE check.Tom St Denis
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register()Tom St Denis
Swap read/write pattern for WREG32_FIELD() Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd()Tom St Denis
Swap read/write pattern for WREG32_FIELD() Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state()Tom St Denis
Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu/gfx8: KIQ is also disabled when MEC is disabledAlex Deucher
Set the ready flag to reflect this. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: cleanup VMHUB bit definitions v2Christian König
The two hubs are just instances of the same hardware, so the register bits are identical. v2: only remove get_vm_protection_bits for now Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: handle CPU access for split VRAM buffers (v2)Christian König
This avoids merging them together on page fault. v2: squash in 64-bit division fix Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/nouveau/gpio: enable interrupts on cards with 32 gpio linesAdam Borowski
The code attempts to enable them, but hits an undefined behaviour by shifting by the entire register's width: int lines = 32; u32 mask = (1 << lines) - 1; // 00000000 on x86 u32 mask = (1 << lines) - 1; // ffffffff on arm (32) u32 mask = (1 << lines) - 1; // 00000000 on arm64 u32 mask = (1ULL << lines) - 1; // ffffffff everywhere Signed-off-by: Adam Borowski <kilobyte@angband.pl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2017-04-06drm/nouveau/gr/gp107: initial supportBen Skeggs
Forked from GP106 implementation. Differences: - 1 PPC/GPC - Slightly different grctx magics Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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