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2024-09-03arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IPNiklas Söderlund
To make it easier to support new R-Car Gen4 SoCs add a family fallback compatible similar to what was done for VIN on R-Car Gen4. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V4H for DTS checks if they are not added. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240826144352.3026980-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03arm64: dts: renesas: r8a779h0: Add family fallback for VIN IPNiklas Söderlund
The usage of the R-Car V4M VIN bindings where merged before the bindings where approved. At that time the family fallback compatible was not part of the bindings, add it. Fixes: 2bb78d9fb7c9 ("arm64: dts: renesas: r8a779h0: Add video capture nodes") Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/20240704161620.1425409-7-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03arm64: dts: renesas: r8a779a0: Add family fallback for VIN IPNiklas Söderlund
To make it easier to support new R-Car Gen4 SoCs a family fallback compatible similar to what is used for R-Car Gen2 has been added to the VIN bindings. Add this fallback to the R-Car V3U DTSI. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V3U for DTS checks if they are not added. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/20240704161620.1425409-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-03arm64: dts: renesas: r8a779g0: Add family fallback for VIN IPNiklas Söderlund
To make it easier to support new R-Car Gen4 SoCs a family fallback compatible similar to what is used for R-Car Gen2 has been added to the VIN bindings. Add this fallback to the R-Car V4H DTSI. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V4H for DTS checks if they are not added. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Link: https://lore.kernel.org/20240704161620.1425409-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdogLad Prabhakar
Enable WDT1 watchdog on RZ/V2H EVK platform. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHILad Prabhakar
Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2 connector) on the RZ/V2H EVK platform. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodesLad Prabhakar
Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodesLad Prabhakar
Add SDHI0-SDHI2 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodesLad Prabhakar
Add RIIC0-RIIC8 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodesLad Prabhakar
Add OSTM0-OSTM7 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: Add initial DTS for RZ/V2H EVK boardLad Prabhakar
Add initial DTS for RZ/V2H EVK board (based on R9A09G057H44), adding the below support: - Memory - Clock inputs - PINCTRL - SCIF Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoCLad Prabhakar
Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are the list of blocks added: - EXT CLKs - 4X CA55 - SCIF - PFC - CPG - SYS - GIC - ARMv8 Timer Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02Merge tag 'renesas-r9a09g057-dt-binding-defs-tag' into renesas-dts-for-v6.12Geert Uytterhoeven
Renesas RZ/V2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/V2H (R9A09G057) SoC, shared by driver and DT source files.
2024-09-02dt-bindings: soc: renesas: Document RZ/V2H EVK boardLad Prabhakar
Add "renesas,rzv2h-evk" which targets the Renesas RZ/V2H ("R9A09G057") EVK board. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828124134.188864-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPGLad Prabhakar
Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-29arm64: dts: renesas: r9a07g043u11-smarc: Enable DUBiju Das
Enable the Display Unit and link with the HDMI add-on board connected to the parallel connector on the RZ/G2UL SMARC EVK by using a Device Tree overlay. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240826101648.176647-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-29arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audioBiju Das
Enable HDMI audio on the RZ/G2LC SMARC EVK. Set SW 1.5 on the SoM module to the OFF position to turn on HDMI audio. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240826090803.56176-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-29arm64: dts: renesas: rzg2l-smarc: Enable HDMI audioBiju Das
Enable HDMI audio on the RZ/{G2L,V2L} SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240826090803.56176-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g043u: Add DU nodeBiju Das
Add DU node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822162320.5084-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0Yoshihiro Shimoda
Enable PCIe Host controller channel 0 on R-Car V4H White Hawk boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822004454.1087582-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodesYoshihiro Shimoda
Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822004454.1087582-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: rzg3s-smarc-som: Enable I2C1 nodeClaudiu Beznea
Enable I2C1 node. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240820101918.2384635-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: rzg3s-smarc: Enable I2C0 nodeClaudiu Beznea
Enable I2C0 node. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240820101918.2384635-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a08g045: Add I2C nodesClaudiu Beznea
The Renesas RZ/G3S SoC has 4 I2C channels. Add DT nodes for them. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240820101918.2384635-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g043u: Add VSPD nodeBiju Das
Add VSPD node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240805131709.101679-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g043u: Add FCPVD nodeBiju Das
Add FCPVD node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240805131709.101679-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizesLad Prabhakar
The RZ/G2L(C) SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20240730122436.350013-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizesLad Prabhakar
The RZ/V2L SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20240730122436.350013-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizesLad Prabhakar
The RZ/G2UL SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Despite the RZ/G2UL SoC being single-core, it has two instances of GICR. Fixes: cf40c9689e510 ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20240730122436.350013-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizesLad Prabhakar
The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Despite the RZ/G3S SoC being single-core, it has two instances of GICR. Fixes: e20396d65b959 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20240730122436.350013-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r9a07g0{43,44,54}: Move regulator-vbus device nodeBiju Das
Move regulator-vbus device node from common to the usbphy-ctrl device node of the individual SoC dtsi's as it embeds the vbus regulator. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240715140705.334183-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: white-hawk-single: Wire-up Ethernet TSNNiklas Söderlund
On the V4H White Hawk Single board as opposed to the Quad board the Ethernet TSN is wired up to a PHY (Marvel 88Q2110/QFN40). Wire up the connection and enable the TSN0. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240701145012.2342868-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-23arm64: dts: renesas: r8a779g0: R-Car Ethernet TSN supportNiklas Söderlund
Add Ethernet TSN support for R-Car V4H. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240701145012.2342868-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-20arm64: dts: renesas: gray-hawk-single: Add CAN-FD supportGeert Uytterhoeven
Enable confirmed-working CAN-FD channels 0 and 1 on the Gray Hawk Single development board: - Channel 0 uses an NXP TJR1443AT CAN transceiver, which must be enabled through a GPIO, - Channels 1-3 use Microchip MCP2558FD-H/SN CAN transceivers, which do not need explicit description, but channels 2-3 do not seem to work. Inspired by a patch for Gray Hawk in the BSP by Duy Nguyen. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/7c2a06b7abec4ce1025761003ccdbce559789708.1722519717.git.geert+renesas@glider.be
2024-08-20arm64: dts: renesas: r8a779h0: Add CAN-FD nodeDuy Nguyen
Add device nodes for the CAN-FD interface and the related external CAN clock on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/43b786db932f5c53103d34fd530365c445c0425e.1722519717.git.geert+renesas@glider.be
2024-08-02arm64: dts: renesas: r9a08g045: Add DMAC nodeClaudiu Beznea
Add DMAC node. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240711123405.2966302-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02arm64: dts: renesas: rzg2ul: Set Ethernet PVDD to 1.8VPaul Barker
On the RZ/G2UL & RZ/Five SMARC SOMs, the RGMII interface between the SoC and the Ethernet PHY operates at 1.8V. The power supply for this interface may be correctly configured in u-boot, but the kernel should not be relying on this. Now that the RZ/G2L pinctrl driver supports configuring the Ethernet power supply voltage, we can simply specify the desired voltage in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240625200316.4282-10-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02arm64: dts: renesas: rzg2lc: Set Ethernet PVDD to 1.8VPaul Barker
On the RZ/G2LC SMARC SOM, the RGMII interface between the SoC and the Ethernet PHY operates at 1.8V. The power supply for this interface may be correctly configured in u-boot, but the kernel should not be relying on this. Now that the RZ/G2L pinctrl driver supports configuring the Ethernet power supply voltage, we can simply specify the desired voltage in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240625200316.4282-9-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02arm64: dts: renesas: rzg2l: Set Ethernet PVDD to 1.8VPaul Barker
On the RZ/G2L & RZ/V2L SMARC SOMs, the RGMII interface between the SoC and the Ethernet PHY operates at 1.8V. The power supply for this interface may be correctly configured in u-boot, but the kernel should not be relying on this. Now that the RZ/G2L pinctrl driver supports configuring the Ethernet power supply voltage, we can simply specify the desired voltage in the device tree. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240625200316.4282-8-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02arm64: dts: renesas: rzg2ul: Enable Ethernet TXC outputPaul Barker
Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/G2UL and RZ/Five SMARC SoMs, as per RGMII specification. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240625200316.4282-7-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02arm64: dts: renesas: rzg2lc: Enable Ethernet TXC outputPaul Barker
Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/G2LC SMARC SoM, as per RGMII specification. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240625200316.4282-6-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02arm64: dts: renesas: rzg2l: Enable Ethernet TXC outputPaul Barker
Configure ET0_TXC and ET1_TXC as outputs on the Renesas RZ/[GV]2L SMARC SoMs, as per RGMII specification. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/20240625200316.4282-5-paul.barker.ct@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-30arm64: dts: renesas: r8a779h0: Add PWM device nodesKhanh Le
Add device nodes for the PWM timers on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Khanh Le <khanh.le.xr@renesas.com> [wsa: rebased, dropped TPU part to be upstreamed seperately] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240725194906.14644-11-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-29arm64: dts: renesas: gray-hawk-single: Add GP LEDsGeert Uytterhoeven
Describe the three General Purpose LEDs on the Gray Hawk Single board, so they can be used as indicator LEDs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/408eac88ec61cf4c56c96397fbb93b4b8c2c8f5b.1721649057.git.geert+renesas@glider.be
2024-07-29arm64: dts: renesas: gray-hawk-single: Add push switchesGeert Uytterhoeven
Describe the three Push Switches on the Gray Hawk Single board, so they can be used for user input. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/41b8277d4b630e0c296375888d9b958448d02cde.1721649057.git.geert+renesas@glider.be
2024-07-29arm64: dts: renesas: r8a779h0: Add missing iommus propertiesGeert Uytterhoeven
Add missing iommus properties to all EthernetAVB device nodes that still lack them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/1ed05b12961662e8fed2f1a6790f5ae3b595f509.1720430758.git.geert+renesas@glider.be
2024-07-29arm64: dts: renesas: r8a779g0: Add missing iommus propertiesGeert Uytterhoeven
Add missing iommus properties to all EthernetAVB and Frame Compression Processor device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/bd394a7e330610d76d98cd5d230c0b3fcbf5c3e4.1720430758.git.geert+renesas@glider.be
2024-07-29arm64: dts: renesas: r8a779a0: Add missing iommus propertiesGeert Uytterhoeven
Add missing iommus properties to all EthernetAVB, DMAC, and Frame Compression Processor device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/39da0dddf7e7f1fde2b2d83444af7bb5ae73b922.1720430758.git.geert+renesas@glider.be
2024-07-29arm64: dts: renesas: r8a77980: Add missing iommus propertiesGeert Uytterhoeven
Add missing iommus properties to the Gigabit Ethernet and Frame Compression Processor device nodes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/3259f4906e20ea626dcd45b7dd310155570b399c.1720430758.git.geert+renesas@glider.be
2024-07-29arm64: dts: renesas: r8a77970: Add missing iommus propertyGeert Uytterhoeven
Add the missing iommus property to the Frame Compression Processor device node. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/41445bdf72a40c9deb36b88e8360b50eb2836919.1720430758.git.geert+renesas@glider.be
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-29 07:58:02 +0000