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GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This adds support for turning off the main power supply via the TWL6030 on the
Kindle Fire (first generation).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This adds support for the Kindle Fire (first generation) power button LEDs, that
are wired to the TWL6030 PWM outputs.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This adds support for USB OTG on the Kindle Fire (first generation).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011. It is using an OMAP4430 SoC GP version.
This adds devicetree support for the device, with only a few basic features
supported, such as debug uart, i2c and internal emmc.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This adds the amazon vendor prefix for Amazon.com, Inc.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Before "tty: Add software emulated RS485 support for 8250" patch Baltos devices
relied on MCTRL_GPIO framework to handle both modem signals and RS485 mode.
With emulated RS485 support for 8250 we can now use these pins as dedicated
RTS/CTS signals taking advantage of hardware flow control etc. when operating
in RS232 mode.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The AM572x-IDK board is a board based on TI's AM5728 SOC
which has a dual core 1.5GHz A15 processor. This board is a
development platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5728
This patch creates a common dtsi file that will provide a common board
dtsi file to define the nodes that are common to AM57xx (including the
upcoming AM5718) IDK boards.
Initial support is only for basic peripherals
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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TI's Industrial Communication Engine EVM is a low cost hardware mainly
developed for industrial communication type applications using serial
or Ethernet based interfaces. This platform features TI's AM3359 with
800MHz single core Cortex-A8 processor, 256MB DDR3, 64MB SPI flash,
8MB NOR Flash, mmc, usb, can, dual Ethernet ports.
For more information, look at HW user guide[1], Data manual[2].
Just add basic support for the moment.
[1] http://processors.wiki.ti.com/index.php/AM335x_Industrial_Communication_Engine_EVM_Rev2_1_HW_User_Guide
[2] http://www.ti.com/lit/ds/symlink/am3359.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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When possible generic node names should be used. So change the node name
from ehrpwm to pwm.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The binding definition for the PCF857x GPIO expanders doesn't mention
a "ti,pcf8575" compatible string. This is apparently because TI is
only a second source - there is no functional difference between
PCF8575 chips manufactured by TI and NXP, and the same board might be
populated with either depending on availability.
This is not a problem in practice because the I2C core uses
of_modalias_node() before matching drivers and this strips the
manufacturer name.
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Filip Matijević <filip.matijevic.pz@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Filip Matijević <filip.matijevic.pz@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Like the Nokia N900, the N950 has leds to show
the state of sys_clkreq and sys_off_mode pins.
A detailed description for the LEDs and
OMAP's sleep states can be found in Tony's
commit for the Nokia N900:
c1be2032f66df9e1238bd5bc4ca666de88a62abc
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add keypad matrix information based on data from
Nokia N950 Kernel.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add regulator configuration as found in the
board files of Nokia's kernel.
Signed-off-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The switch configuration for NAND is actually the other way round.
Also mention ON/OFF states as that is more natural to understand
(without the help of schematics) when compared to HIGH/LOW.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Few regulators information were missing from DT. Add those
missing regulators.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The ARM TWD interrupt is a private peripheral interrupt (PPI) and per
the ARM GIC documentation, whether the type for PPIs can be set is
IMPLEMENTATION DEFINED. For Tegra20/30 devices the PPI type cannot be
set and so when we attempt to set the type for the ARM TWD interrupt it
fails. This has gone unnoticed because it fails silently and because we
cannot re-configure the type it has had no impact. Nevertheless fix the
type for the TWD interrupt so that it matches the hardware configuration.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.
This has been tested on boards, tegra20-trimslice, tegra30-beaver,
tegra114-dalmore and tegra124-jetson-tk1.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.
This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Watchdog support was added to the timer block with Tegra30. Tegra20 did
not have this yet. However, the Tegra114 and Tegra124 DTSI files had an
entry in the compatible string list for "nvidia,tegra20-timer", but not
for "nvidia,tegra30-timer", which is why watchdog support isn't enabled
on them.
Fix this by adding an entry for "nvidia,tegra30-timer" to the compatible
string list of the timer block on Tegra114 and Tegra124.
This allows the watchdog to work on Jetson TK1.
Signed-off-by: Maarten Lankhorst <dev@mblankhorst.nl>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This patch enables the APB DMA high speed UARTs of the Jetson TK1. So
far, they were only enabled in NVidia's official BSP.
Those additional UARTs are exposed on the expansion connector J3A2:
UART1:
Pin 41: BR_UART1_TXD
Pin 44: BR_UART1_RXD
UART2:
Pin 65: UART2_RXD
Pin 68: UART2_TXD
Pin 71: UART2_CTS_L
Pin 74: UART2_RTS_L
Signed-off-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933f9 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
Signed-off-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
[treding@nvidia.com: amend subject, add commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
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These two are both ARMv7 SoCs. They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.
Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add the DT node for Timer12 present on DRA7 family of
SoCs. Timer12 is present in PD_WKUPAON power domain, and
has the same capabilities as the other timers, except for
the fact that it serves as a secure timer on HS devices
and is clocked only from the secure 32K clock.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The Timers 13 through 16 have been added previously in
disabled state. These timers are common timers that are
present on all DRA7 family of SoCs, so enable these
devices by default like the rest of the DMTimers.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for the unit offsets]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The assigned-clock* needs to be in the root of the device's node. If it is
in the sub-node the CCF will ignore it.
Since the clkout2 is used by the codec as MCLK, move the clock parent
selection to that node.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead. This
restriction is also applicable for McASP1 and McASP2.
This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.
The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.
Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Move the sDMA xbar nodes under the L4 interconnect node.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add the resets property for the 2 USB controllers.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Add support for the keys and flip-switches on the SoCFPGA SoCkit board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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Add support for the blue LEDs on the SoCFPGA SoCkit board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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The socfpga_cyclone5.dtsi is included by all DTS files which describe boards
using the Cyclone V SoC. The Cyclone V SoC has two ethernet controllers and
different boards use none, one or both of them.
The /soc/ethernet@ff702000/{} node in socfpga_cyclone5.dtsi unconditionaly
enabled gmac0 interface, which is clearly wrong for those boards which use
gmac1 interface instead.
This patch removes the entire /soc/ethernet@ff702000/{} node from the
socfpga_cyclone5.dtsi file. This is correct, since all of the board which
include this file also have correct gmac0 or gmac1 node present in them.
Minor correction had to be done to EBV SoCrates, which didn't define PHY
mode explicitly, but inherited it from the socfpga_cyclone5.dtsi .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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