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2025-05-15cxl: docs/platform/acpi/srat Add generic target documentationDave Jiang
Add description in the SRAT document to describe the Generic Port Affinity sub-table. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-15cxl: docs/platform/cdat reference documentationDave Jiang
Add documentation for CDAT structures for CXL usages. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-15Documentation: Update the CXL Maturity MapAlison Schofield
Changes for extended-linear cache, hetero-interleave, and HPA->DPA address translation. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: Sync up the driver-api/cxl documentationAlison Schofield
pmem.c regs.c mbox.c identifiers were missing. Add them to memory-devices.rst following their respective DOC comment includes. Two acpi.c identifiers were available, but not used in kernel-doc's: 1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx complaint on the ascii art by escaping it. 2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst. core/features.c is new. Add a "DOC: cxl features" comment to the source and identifiers to memory_devices.rst. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13Merge branch 'for-6.16/cxl-docs' into cxl-for-nextDave Jiang
Detailed documentation for the entire CXL sub-system from platform, BIOS, to CXL driver, memory interface, memory hotplug, and others.
2025-05-13cxl: docs - add self-referencing cross-linksGregory Price
Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/hugepagesGregory Price
Add docs on how CXL capacity interacts with CMA and HugeTLB allocation interfaces. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-17-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/reclaimGregory Price
Document a bit about how reclaim interacts with various CXL configurations. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-16-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/page-allocatorGregory Price
Document some interesting interactions that occur when exposing CXL memory capacity to page allocator. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-15-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/allocation/daxGregory Price
Small example of accessing CXL memory capacity via DAX device Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-14-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux/memory-hotplugGregory Price
Add documentation on how the CXL driver surfaces memory through the DAX driver and memory-hotplug. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-13-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux/dax-driver documentationGregory Price
Add documentation on how the CXL driver interacts with the DAX driver. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-12-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux/cxl-driver - add example configurationsGregory Price
Add 4 example configurations: - single device - cross-host-bridge interleave - intra-host-bridge-interleave - multi-level interleave Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-11-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux - add cxl-driver theory of operationGregory Price
Add docs for the CXL driver that explains the base devices, decoder types, region types, mailbox interfaces, and decoder programming. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-10-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux - early boot configurationGregory Price
Document __init time configurations that affect CXL driver probe process and memory region configuration. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-9-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/linux - overviewGregory Price
Add type-3 device configuration overview that explains the probe process for a type-3 device from early-boot through memory-hotplug. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-8-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/platform/example-configs documentationGregory Price
Add example ACPI Table configurations for different sample platforms. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-7-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/platform/acpi reference documentationGregory Price
Add basic ACPI table information needed to understand the CXL driver probe process. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-6-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/platform/bios-and-efi documentationGregory Price
Add some docs on CXL configurations done in bios/efi that affect linux configuration - information vendors may care to consider. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-5-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs/devices - add cxl device and protocol referenceGregory Price
Add a simple device primer sufficient to understand the theory of operation documentation. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-4-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: docs - access-coordinates doc fixupsGregory Price
Place the hierarchy diagram in access-coordinates.rst in a code block. Fix a few grammar issues. Suggested-by: Randy Dunlap <rdunlap@infradead.org> Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-3-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-13cxl: update documentation structure in prep for new docsGregory Price
Restructure the cxl folder to make adding docs per-page cleaner. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-2-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/hdm: Clean up a debug printkDan Carpenter
Smatch complains that %pa is for phys_addr_t types and "size" is a u64. drivers/cxl/core/hdm.c:521 cxl_dpa_alloc() error: '%pa' expects argument of type 'phys_addr_t*', argument 4 has type 'ullong* Looking at this, to me it seems more useful to print the sizes as decimal instead of hex. Let's do that. [dj: Adjusted based on latest code changes. ] Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/3d3d969d-651d-4e9d-a892-900876a60ab5@moroto.mountain Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09Merge branch 'for-6.16/cxl-cleanups' into cxl-for-nextDave Jiang
In preparation for code changes related to AMD Zen5 address translation support, a number of small code refactor and cleanups are send ahead.
2025-05-09cxl: Add a dev_dbg() when a decoder was added to a portRobert Richter
Improve debugging by adding and unifying messages whenever a decoder was added to a port. It is especially useful to get the decoder mapping of the involved CXL host bridge or PCI device. This avoids a complex lookup of the decoder/port/device mappings in sysfs. Example log messages: cxl_acpi ACPI0017:00: decoder0.0 added to root0 cxl_acpi ACPI0017:00: decoder0.1 added to root0 ... pci0000:e0: decoder1.0 added to port1 pci0000:e0: decoder1.1 added to port1 ... cxl_mem mem0: decoder5.0 added to endpoint5 cxl_mem mem0: decoder5.1 added to endpoint5 Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-15-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Add a dev_err() on missing target list entriesRobert Richter
Broken target lists are hard to discover as the driver fails at a later initialization stage. Add an error message for this. Example log messages: cxl_mem mem1: failed to find endpoint6:0000:e0:01.3 in target list of decoder1.1 cxl_port endpoint6: failed to register decoder6.0: -6 cxl_port endpoint6: probe: 0 Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-14-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Add a dev_warn() on registration failureRobert Richter
Esp. in complex system configurations with multiple endpoints and interleaving setups it is hard to detect region setup failures as its registration may silently fail. Add messages to show registration failures. Example log message: cxl region5: region sort successful cxl region5: mem0:endpoint5 decoder5.0 add: mem0:decoder5.0 @ 0 next: none nr_eps: 1 nr_targets: 1 cxl_port endpoint5: decoder5.0: range: 0x22350000000-0x2634fffffff iw: 1 ig: 256 cxl region5: pci0000:e0:port1 decoder1.2 add: mem0:decoder5.0 @ 0 next: mem0 nr_eps: 1 nr_targets: 1 cxl region5: pci0000:e0:port1 iw: 1 ig: 256 cxl region5: pci0000:e0:port1: decoder1.2 expected 0000:e0:01.2 at 0 cxl endpoint5: failed to attach decoder5.0 to region5: -6 cxl_port endpoint5: probe: 0 Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-13-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Add function to find a port's switch decoder by rangeRobert Richter
Factor out code to find the switch decoder of a port for a specific address range. Reuse the code to search a root decoder, create the function cxl_port_find_switch_decoder() and rework match_root_decoder_by_range() to be usable for switch decoders too. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-12-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Factor out code to find a root decoder's regionRobert Richter
In function cxl_add_to_region() there is code to determine a root decoder's region. Factor that code out. This is in preparation to further rework and simplify function cxl_add_to_region(). The reference count must be decremented after using the region. cxl_find_region_by_range() is paired with the put_cxl_region cleanup helper that can be used for this. [dj: Fixed up "obj __free(...) = NULL" pattern] Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-11-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Factor out code to find the root decoderRobert Richter
In function cxl_add_to_region() there is code to determine the root decoder associated to an endpoint decoder. Factor out that code for later reuse. This has the benefit of reducing cxl_add_to_region()'s function complexity. The reference count must be decremented after using the root decoder. cxl_find_root_decoder() is paired with the put_cxl_root_decoder cleanup helper that can be used for this. [dj: Fixed up "obj __free(...) = NULL" pattern] Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-10-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/port: Replace put_cxl_root() by a cleanup helperRobert Richter
Function put_cxl_root() is only used by its cleanup helper. Remove the function entirely and only use the helper. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-9-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Move find_cxl_root() to cxl_add_to_region()Robert Richter
When adding an endpoint to a region, the root port is determined first. Move this directly into cxl_add_to_region(). This is in preparation of the initialization of endpoints that iterates the port hierarchy from the endpoint up to the root port. As a side-effect the root argument is removed from the argument lists of cxl_add_to_region() and related functions. Now, the endpoint is the only parameter to add a region. This simplifies the function interface. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-8-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Avoid duplicate call of cxl_port_pick_region_decoder()Robert Richter
Function cxl_port_pick_region_decoder() is called twice, in alloc_region_ref() and cxl_rr_alloc_decoder(). Both functions are subsequently called from cxl_port_attach_region(). Make the decoder a function argument to both which avoids a duplicate call of cxl_port_pick_region_decoder(). Now, cxl_rr_alloc_decoder() no longer allocates the decoder. Instead, the previously picked decoder is assigned to the region reference. Hence, rename the function to cxl_rr_assign_decoder(). Moving the call out of alloc_region_ref() also moves it out of the xa_for_each() loop in there. Now, cxld is determined no longer only for each auto-generated region, but now once for all regions regardless of auto-generated or not. This is fine as the cxld argument is needed for all regions in cxl_rr_assign_decoder() and an error would be returned otherwise anyway. So it is better to determine the decoder in front of all this and fail early if missing instead of running through all that code with multiple calls of cxl_port_pick_region_decoder(). Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-7-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/region: Rename function to cxl_port_pick_region_decoder()Robert Richter
Current function cxl_region_find_decoder() is used to find a port's decoder during region setup. In the region creation path the function is an allocator to find a free port. In the region assembly path, it is recalling the decoder that platform firmware picked for validation purposes. Rename function to cxl_port_pick_region_decoder() that better describes its use and update the function's description. The result of cxl_port_pick_region_decoder() is recorded in a 'struct cxl_region_ref' in @port for later recall when other endpoints might also be targets of the picked decoder. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-6-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl: Introduce parent_port_of() helperRobert Richter
Often a parent port must be determined. Introduce the parent_port_of() helper function to avoid open coding of determination of a parent port. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-5-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/pci: Add comments to cxl_hdm_decode_init()Robert Richter
There are various configuration cases of HDM decoder registers causing different code paths. Add comments to cxl_hdm_decode_init() to better explain them. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-4-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl/pci: Moving code in cxl_hdm_decode_init()Robert Richter
Commit 3f9e07531778 ("cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init()") changed the code flow in this function. The root port is determined before a check to leave the function. Since the root port is not used by the check it can be moved to run the check first. This improves code readability and avoids unnesessary code execution. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-3-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-09cxl: Remove else after returnRobert Richter
Remove unnecessary 'else' after return. Improves readability of code. It is easier to place comments. Check and fix all occurrences under drivers/cxl/. Signed-off-by: Robert Richter <rrichter@amd.com> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: "Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com> Tested-by: Gregory Price <gourry@gourry.net> Acked-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250509150700.2817697-2-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-06cxl/test: Address missing MODULE_DESCRIPTION warnings for cxl_testDave Jiang
Add MODULE_DESCRIPTION() to address the following warnings: WARNING: modpost: missing MODULE_DESCRIPTION() in test/cxl_test.o WARNING: modpost: missing MODULE_DESCRIPTION() in test/cxl_mock.o WARNING: modpost: missing MODULE_DESCRIPTION() in test/cxl_mock_mem.o [dj: s/CXL test/cxl_test:/ per djbw's comment] Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250429235953.4175408-1-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-04-28cxl: core/region - ignore interleave granularity when ways=1Gregory Price
When validating decoder IW/IG when setting up regions, the granularity is irrelevant when iw=1 - all accesses will always route to the only target anyway - so all ig values are "correct". Loosen the requirement that `ig = (parent_iw * parent_ig)` when iw=1. On some Zen5 platforms, the platform BIOS specifies a 256-byte interleave granularity window for host bridges when there is only one target downstream. This leads to Linux rejecting the configuration of a region with a x2 root with two x1 hostbridges. Decoder Programming: root - iw:2 ig:256 hb1 - iw:1 ig:256 (Linux expects 512) hb2 - iw:1 ig:256 (Linux expects 512) ep1 - iw:2 ig:256 ep2 - iw:2 ig:256 This change allows all decoders downstream of a passthrough decoder to also be configured as passthrough (iw:1 ig:X), but still disallows downstream decoders from applying subsequent interleaves. e.g. in the above example if there was another decoder south of hb1 attempting to interleave 2 endpoints - Linux would enforce hb1.ig=512 because the southern decoder would have iw:2 and require ig=pig*piw. [DJ: Fixed up against 6.15-rc1] Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250402232552.999634-1-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-04-28cxl/acpi: Verify CHBS length for CXL2.0Li Zhijian
Per CXL Spec r3.1 Table 9-21, both CXL1.1 and CXL2.0 have defined their own length, verify it to avoid an invalid CHBS. Additionally, this patch also removes the redundant macro CXL_RCRB_SIZE, favoring the use of `ACPI_CEDT_CHBS_LENGTH_CXL11`, which offers clearer semantic meaning. [DJ: Code edited for readability suggested by djbw] Reviewed-by: Gregory Price <gourry@gourry.net> Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20250410010545.99590-1-lizhijian@fujitsu.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-04-28cxl: Remove always true condition for cxlctl_validate_hw_command()Dave Jiang
smatch warnings: drivers/cxl/core/features.c:441 cxlctl_validate_hw_command() warn: always true condition '(scope >= 0) => (0-u32max >= 0)' Remove the check entirely as it has no effect. Expectation is both of these operations should be allowed for all check levels. They are read only and have no change effects. Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202504041033.2HBboAZR-lkp@intel.com/ Reviewed-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://patch.msgid.link/20250404165418.3032414-1-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-04-27Linux 6.15-rc4v6.15-rc4Linus Torvalds
2025-04-26Merge tag 'pci-v6.15-fixes-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull PCI fixes from Bjorn Helgaas: - When releasing a start-aligned resource, e.g., a bridge window, save start/end/flags for the next assignment attempt; fixes a v6.15-rc1 regression (Ilpo Järvinen) - Move set_pcie_speed.sh from TEST_PROGS to TEST_FILE; fixes a bwctrl selftest v6.15-rc1 regression (Ilpo Järvinen) - Add Manivannan Sadhasivam as maintainer of native host bridge and endpoint drivers (Manivannan Sadhasivam) - In endpoint test driver, defer IRQ allocation from .probe() until ioctl() to fix a regression on platforms where the Vendor/Device ID match doesn't include driver_data (Niklas Cassel) * tag 'pci-v6.15-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: misc: pci_endpoint_test: Defer IRQ allocation until ioctl(PCITEST_SET_IRQTYPE) MAINTAINERS: Move Manivannan Sadhasivam as PCI Native host bridge and endpoint maintainer selftests/pcie_bwctrl: Fix test progs list PCI: Restore assigned resources fully after release
2025-04-26Merge tag 'nfsd-6.15-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux Pull nfsd fix from Chuck Lever: - Revert a v6.15 patch due to a report of SELinux test failures * tag 'nfsd-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux: Revert "sunrpc: clean cache_detail immediately when flush is written frequently"
2025-04-26Merge tag 'x86-urgent-2025-04-26' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull misc x86 fixes from Ingo Molnar: - Fix 32-bit kernel boot crash if passed physical memory with more than 32 address bits - Fix Xen PV crash - Work around build bug in certain limited build environments - Fix CTEST instruction decoding in insn_decoder_test * tag 'x86-urgent-2025-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/insn: Fix CTEST instruction decoding x86/boot: Work around broken busybox 'truncate' tool x86/mm: Fix _pgd_alloc() for Xen PV mode x86/e820: Discard high memory that can't be addressed by 32-bit systems
2025-04-26Merge tag 'sched-urgent-2025-04-26' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler fix from Ingo Molnar: "Fix sporadic crashes in dequeue_entities() due to ... bad math. [ Arguably if pick_eevdf()/pick_next_entity() was less trusting of complex math being correct it could have de-escalated a crash into a warning, but that's for a different patch ]" * tag 'sched-urgent-2025-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/eevdf: Fix se->slice being set to U64_MAX and resulting crash
2025-04-26Merge tag 'perf-urgent-2025-04-26' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull misc perf events fixes from Ingo Molnar: - Use POLLERR for events in error state, instead of the ambiguous POLLHUP error value - Fix non-sampling (counting) events on certain x86 platforms * tag 'perf-urgent-2025-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86: Fix non-sampling (counting) events on certain x86 platforms perf/core: Change to POLLERR for pinned events with error
2025-04-26Merge tag 'irq-urgent-2025-04-26' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fix from Ingo Molnar: "Fix crashes in the gic-v2m irqchip driver, caused by an incorrect __init annotation" * tag 'irq-urgent-2025-04-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v2m: Prevent use after free of gicv2m_get_fwnode()
2025-04-26Merge tag 'loongarch-fixes-6.15-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson Pull LoongArch fixes from Huacai Chen: "Add a missing Kconfig option, fix some bugs in exception handlers, memory management and KVM" * tag 'loongarch-fixes-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: LoongArch: KVM: Fix PMU pass-through issue if VM exits to host finally LoongArch: KVM: Fully clear some CSRs when VM reboot LoongArch: KVM: Fix multiple typos of KVM code LoongArch: Return NULL from huge_pte_offset() for invalid PMD LoongArch: Remove a bogus reference to ZONE_DMA LoongArch: Handle fp, lsx, lasx and lbt assembly symbols LoongArch: Make do_xyz() exception handlers more robust LoongArch: Make regs_irqs_disabled() more clear LoongArch: Select ARCH_USE_MEMTEST
generated by cgit v1.2.3 (git 2.39.1) at 2025-07-30 19:18:50 +0000