summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-06-21drm/amd/powerplay: add function get_workload_type_map for swsmuKevin Wang
1.add new callback function get_workload_byte for smu 2.remove old workload map function Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: remove upload_dpm_level function for vega20Kevin Wang
the function upload_dpm_level is an internal function, so remove public interface. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function get_fan_speed_percent for navi10Kevin Wang
add callback function get_fan_speed_percent for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function set_thermal_fan_table for navi10Kevin Wang
add callback function set_thermal_fan_table for navi10 asic Signed-off-by:Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function is_dpm_running for navi10Kevin Wang
add callback function is_dpm_running for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: move read sensor of UVD[VCE]_POWER to amdgpu_smu fileKevin Wang
This part of code is asic unrelated and moves to top code level. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function get_current_activity_percent for navi10Kevin Wang
add callback function get_current_activity_percent for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function get_gpu_power for navi10Kevin Wang
add callback function get_gpu_power for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function unforce_dpm_levels for navi10Kevin Wang
add callback function unforce_dpm_levels for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add funciton force_dpm_limit for navi10Kevin Wang
add callback function force_dpm_limit for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function display_configuration_changed for navi10Kevin Wang
1.add callback function to support navi10 asic. 2.Remove unnecessary logical code. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function pre_display_config_changed for navi10Kevin Wang
add callback function pre_display_config_changed for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10Kevin Wang
add callback function get_clock_by_type_with_latency for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function populate_umd_state_clk for navi10Kevin Wang
add callback function populate_umd_state_clk for navi10 asic Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function force_clk_levels for navi10Kevin Wang
add sysfs interface of force_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function of smu_set_hard_freq_rangeKevin Wang
add this function to get dpm clock information. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function of smu_set_soft_freq_rangeKevin Wang
add this helper function to get dpm clk information. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function of smu_get_dpm_freq_rangeKevin Wang
add this helper function to get dpm clk information (min, max); Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function print_clk_levels for navi10Kevin Wang
add sysfs interface of print_clk_levels sysfs for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add helper function to get dpm freq informationsKevin Wang
this function can help driver to get ppclk informations Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add function get current clock freq interface for navi10Kevin Wang
add function of get_current_clk_freq_by_table for navi10. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: require to pin/unpin CSIB BO when suspend/resumeJack Xiao
CSIB BO is required to be pinned down to guarantee bo is always valid when resume, and to be unpinned it so that its content can be saved during suspend. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: remove unnecessary waiting on gfx inactiveJack Xiao
The following KIQ ring test could guarantee the previous unmap has been done. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: RLC must be disabled after SMU when S3 on naviJack Xiao
SMU requires to interact with RLC when disable all features, so RLC shouldn't be disabled ahead of SMU. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay/smu11: disable PLL shutdown when gfxoff enabledJack Xiao
MP1 cannot access clock IP during MP1 FW reload, disable PLL shutdown as a workaround. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: disable uclk dpm by defaulttiancyin
[why] The uclk dpm feature is not supported by some certain navi10 board like 18202, while supported by some board like 18201. It causes modprobe failure on 18202 board. [how] Disabled this feature by default, it can be enabled by module parameter uclk_dpm_support=1. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/VCN2.0: remove powergating for UVDW tileLeo Liu
No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21amd/powerplay: enable uclk dpmKenneth Feng
Enable uclk dpm on navi10 as the result of removing fast switch setting. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21amd/powerplay: fix the issue of uclk dpmKenneth Feng
PPSMC_MSG_SetUclkFastSwitch message can be applied on vega20, but can't on navi10. This is the prerequisite of uclk dpm on navi10. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: fix unbalanced MAP/UNMAP_QUEUES when async_gfx_ring is ↵Xiaojie Yuan
disabled gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is enabled, so should gfx_v10_0_kiq_disable_kgq(). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/gfx10: drop redundant se/sh selectionXiaojie Yuan
we already selected se/sh at the beginning of the for loop Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: enable mes FW backdoor loadingJack Xiao
It enables MES FW backdoor loading in ip block functions. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement mes enablement functionJack Xiao
After MES firmware gets loaded, it enables MES engine starting execution. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement MES firmware backdoor loadingJack Xiao
It implements MES firmware backdoor loading. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement ucode buffers destructionJack Xiao
Free ucode GPU buffers. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: upload mes data ucode to gpu bufferJack Xiao
Allocate GPU buffer and upload mes data ucode to the buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: upload mes ucode to gpu bufferJack Xiao
Allocate GPU buffer and upload ucode firmware to the buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: implement ucode CPU buffer destructionJack Xiao
It implements the CPU buffer destruction of ucode. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: load mes firmware file to CPU bufferJack Xiao
It requests MES firmware binary and uploads to CPU buffer. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/mes10.1: add mes firmware info fieldsJack Xiao
The newly added fields is to store mes firmware related information. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/ucode: add mes firmware file supportJack Xiao
The newly added firmware struct is for mes firmware file. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/ucode: add the definitions of MES ucode and ucode dataJack Xiao
MES requires two seperate firmwares: ucode and ucode data. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma5: incorrect variable type for gpu addressJack Xiao
Incorrect programming with 64bit gpu address assignment for 32bit variable. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma5: fix a sdma potential hang in VK_Examples testtiancyin
[why] When page fault happens, it could lead to sdma hang is RESP_MODE = 0 for non-PRT case. [how] Setting SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt. Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: tiancyin <tianci.yin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: remove uvd_gated/vce_gated from smu_power_context (v2)Hawking Zhang
It's not needed for navi. v2: remove unused variable (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/nv: set vcn pg flagJack Xiao
Enable VCN power gating by default. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable vcn dpm scheme for naviJack Xiao
On navi1x, vcn dpm scheme was merged into powergating scheme. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/vcn2: don't access register when power gatedJack Xiao
It will cause bus hang to access register UVD_STATUS when VCN is in the state of power gated. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: add new interface for vcn powergatingKenneth Feng
add new interface for vcn powrergating and vcn dpm as well. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amd/powerplay: enable vcn powergating v2Kenneth Feng
enable vcn powergating in driver for navi10 v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-08-01 22:02:08 +0000