diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 71 |
1 files changed, 56 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 29885febc0b0..264176a01e16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -107,7 +107,6 @@ #include "amdgpu_gfxhub.h" #include "amdgpu_df.h" #include "amdgpu_smuio.h" -#include "amdgpu_hdp.h" #define MAX_GPU_INSTANCE 16 @@ -124,6 +123,16 @@ struct amdgpu_mgpu_info uint32_t num_gpu; uint32_t num_dgpu; uint32_t num_apu; + + /* delayed reset_func for XGMI configuration if necessary */ + struct delayed_work delayed_reset_work; + bool pending_reset; +}; + +struct amdgpu_watchdog_timer +{ + bool timeout_fatal_disable; + uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ }; #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 @@ -177,7 +186,9 @@ extern int amdgpu_compute_multipipe; extern int amdgpu_gpu_recovery; extern int amdgpu_emu_mode; extern uint amdgpu_smu_memory_pool_size; +extern int amdgpu_smu_pptable_id; extern uint amdgpu_dc_feature_mask; +extern uint amdgpu_freesync_vid_mode; extern uint amdgpu_dc_debug_mask; extern uint amdgpu_dm_abm_level; extern int amdgpu_backlight; @@ -185,6 +196,7 @@ extern struct amdgpu_mgpu_info mgpu_info; extern int amdgpu_ras_enable; extern uint amdgpu_ras_mask; extern int amdgpu_bad_page_threshold; +extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; extern int amdgpu_async_gfx_ring; extern int amdgpu_mcbp; extern int amdgpu_discovery; @@ -258,6 +270,8 @@ struct amdgpu_bo_va_mapping; struct amdgpu_atif; struct kfd_vm_fault_info; struct amdgpu_hive_info; +struct amdgpu_reset_context; +struct amdgpu_reset_control; enum amdgpu_cp_irq { AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, @@ -576,6 +590,7 @@ struct amdgpu_allowed_register_entry { }; enum amd_reset_method { + AMD_RESET_METHOD_NONE = -1, AMD_RESET_METHOD_LEGACY = 0, AMD_RESET_METHOD_MODE0, AMD_RESET_METHOD_MODE1, @@ -584,6 +599,19 @@ enum amd_reset_method { AMD_RESET_METHOD_PCI, }; +struct amdgpu_video_codec_info { + u32 codec_type; + u32 max_width; + u32 max_height; + u32 max_pixels_per_frame; + u32 max_level; +}; + +struct amdgpu_video_codecs { + const u32 codec_count; + const struct amdgpu_video_codec_info *codec_array; +}; + /* * ASIC specific functions. */ @@ -628,6 +656,9 @@ struct amdgpu_asic_funcs { void (*pre_asic_init)(struct amdgpu_device *adev); /* enter/exit umd stable pstate */ int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); + /* query video codecs */ + int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs); }; /* @@ -792,12 +823,7 @@ struct amdgpu_device { bool accel_working; struct notifier_block acpi_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; - struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; - unsigned debugfs_count; -#if defined(CONFIG_DEBUG_FS) - struct dentry *debugfs_preempt; - struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; -#endif + struct debugfs_blob_wrapper debugfs_vbios_blob; struct amdgpu_atif *atif; struct amdgpu_atcs atcs; struct mutex srbm_mutex; @@ -853,8 +879,6 @@ struct amdgpu_device { spinlock_t audio_endpt_idx_lock; amdgpu_block_rreg_t audio_endpt_rreg; amdgpu_block_wreg_t audio_endpt_wreg; - void __iomem *rio_mem; - resource_size_t rio_mem_size; struct amdgpu_doorbell doorbell; /* clock/pll info */ @@ -897,6 +921,8 @@ struct amdgpu_device { struct amdgpu_irq_src vupdate_irq; struct amdgpu_irq_src pageflip_irq; struct amdgpu_irq_src hpd_irq; + struct amdgpu_irq_src dmub_trace_irq; + struct amdgpu_irq_src dmub_outbox_irq; /* rings */ u64 fence_context; @@ -980,6 +1006,7 @@ struct amdgpu_device { struct amdgpu_df df; struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; + uint32_t harvest_ip_mask; int num_ip_blocks; struct mutex mn_lock; DECLARE_HASHTABLE(mn_hash, 7); @@ -1020,6 +1047,7 @@ struct amdgpu_device { int asic_reset_res; struct work_struct xgmi_reset_work; + struct list_head reset_list; long gfx_timeout; long sdma_timeout; @@ -1050,6 +1078,8 @@ struct amdgpu_device { bool in_pci_err_recovery; struct pci_saved_state *pci_state; + + struct amdgpu_reset_control *reset_cntl; }; static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) @@ -1062,7 +1092,7 @@ static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) return &adev->ddev; } -static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) +static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) { return container_of(bdev, struct amdgpu_device, mman.bdev); } @@ -1084,9 +1114,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); -u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); -void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); - u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 pcie_index, u32 pcie_data, u32 reg_addr); @@ -1103,6 +1130,12 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); +int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, + struct amdgpu_reset_context *reset_context); + +int amdgpu_do_asic_reset(struct list_head *device_list_handle, + struct amdgpu_reset_context *reset_context); + int emu_soc_asic_init(struct amdgpu_device *adev); /* @@ -1168,8 +1201,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev); } while (0) #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) -#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) -#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK @@ -1223,6 +1254,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) +#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); @@ -1242,7 +1274,9 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size); +int amdgpu_device_mode1_reset(struct amdgpu_device *adev); bool amdgpu_device_supports_atpx(struct drm_device *dev); +bool amdgpu_device_supports_px(struct drm_device *dev); bool amdgpu_device_supports_boco(struct drm_device *dev); bool amdgpu_device_supports_baco(struct drm_device *dev); bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, @@ -1356,6 +1390,13 @@ void amdgpu_pci_resume(struct pci_dev *pdev); bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); bool amdgpu_device_load_pci_state(struct pci_dev *pdev); +bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); + +int amdgpu_device_set_cg_state(struct amdgpu_device *adev, + enum amd_clockgating_state state); +int amdgpu_device_set_pg_state(struct amdgpu_device *adev, + enum amd_powergating_state state); + #include "amdgpu_object.h" static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) |