diff options
121 files changed, 3315 insertions, 1149 deletions
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index fbfc4f99c01e..fcbd77365aef 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1067,6 +1067,18 @@ properties: - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board - const: fsl,imx93 + - description: i.MXRT1050 based Boards + items: + - enum: + - fsl,imxrt1050-evk # i.MXRT1050 EVK Board + - const: fsl,imxrt1050 + + - description: i.MXRT1170 based Boards + items: + - enum: + - fsl,imxrt1170-evk # i.MXRT1170 EVK Board + - const: fsl,imxrt1170 + - description: Freescale Vybrid Platform Device Tree Bindings diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml index 29339d0196ec..0e7833478869 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml @@ -75,6 +75,10 @@ properties: - const: fsl,imx8qxp-usdhc - const: fsl,imx7d-usdhc deprecated: true + - items: + - enum: + - fsl,imxrt1170-usdhc + - const: fsl,imxrt1050-usdhc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml index 1278f7293560..db5fe66ad873 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -35,7 +35,7 @@ patternProperties: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val input_val> are specified using a PIN_FUNC_ID macro, which can - be found in <include/dt-bindings/pinctrl/pins-imxrt1050.h>. The last + be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MXRT1050 Reference Manual for detailed CONFIG settings. $ref: /schemas/types.yaml#/definitions/uint32-matrix diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml index 8c79fcef7c52..a2141eb0854e 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -8,31 +8,22 @@ title: Mediatek MT6779 Pin Controller maintainers: - Andy Teng <andy.teng@mediatek.com> + - Sean Wang <sean.wang@kernel.org> -description: |+ - The pin controller node should be the child of a syscon node with the - required property: - - compatible: "syscon" +description: + The MediaTek pin controller on MT6779 is used to control pin + functions, pull up/down resistance and drive strength options. properties: compatible: - const: mediatek,mt6779-pinctrl + enum: + - mediatek,mt6779-pinctrl + - mediatek,mt6797-pinctrl reg: - minItems: 9 - maxItems: 9 - - reg-names: - items: - - const: "gpio" - - const: "iocfg_rm" - - const: "iocfg_br" - - const: "iocfg_lm" - - const: "iocfg_lb" - - const: "iocfg_rt" - - const: "iocfg_lt" - - const: "iocfg_tl" - - const: "eint" + description: Physical addresses for GPIO base(s) and EINT registers. + + reg-names: true gpio-controller: true @@ -59,19 +50,65 @@ properties: "#interrupt-cells": const: 2 -allOf: - - $ref: "pinctrl.yaml#" - required: - compatible - reg - reg-names - gpio-controller - "#gpio-cells" - - gpio-ranges - - interrupt-controller - - interrupts - - "#interrupt-cells" + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + const: mediatek,mt6779-pinctrl + then: + properties: + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: gpio + - const: iocfg_rm + - const: iocfg_br + - const: iocfg_lm + - const: iocfg_lb + - const: iocfg_rt + - const: iocfg_lt + - const: iocfg_tl + - const: eint + - if: + properties: + compatible: + contains: + const: mediatek,mt6797-pinctrl + then: + properties: + reg: + minItems: 5 + maxItems: 5 + + reg-names: + items: + - const: gpio + - const: iocfgl + - const: iocfgb + - const: iocfgr + - const: iocfgt + - if: + properties: + reg-names: + contains: + const: eint + then: + required: + - interrupts + - interrupt-controller + - "#interrupt-cells" patternProperties: '-[0-9]*$': @@ -113,6 +150,12 @@ patternProperties: input-schmitt-disable: true + drive-strength: + enum: [2, 4, 8, 12, 16] + + slew-rate: + enum: [0, 1] + mediatek,pull-up-adv: description: | Pull up setings for 2 pull resistors, R0 and R1. User can diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml deleted file mode 100644 index 637a8386e23e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml +++ /dev/null @@ -1,176 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6797-pinctrl.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Mediatek MT6797 Pin Controller - -maintainers: - - Sean Wang <sean.wang@kernel.org> - -description: |+ - The MediaTek's MT6797 Pin controller is used to control SoC pins. - -properties: - compatible: - const: mediatek,mt6797-pinctrl - - reg: - minItems: 5 - maxItems: 5 - - reg-names: - items: - - const: gpio - - const: iocfgl - - const: iocfgb - - const: iocfgr - - const: iocfgt - - gpio-controller: true - - "#gpio-cells": - const: 2 - description: | - Number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - - interrupt-controller: true - - interrupts: - maxItems: 1 - - "#interrupt-cells": - const: 2 - -allOf: - - $ref: "pinctrl.yaml#" - -required: - - compatible - - reg - - reg-names - - gpio-controller - - "#gpio-cells" - -patternProperties: - '-[0-9]+$': - type: object - additionalProperties: false - patternProperties: - 'pins': - type: object - additionalProperties: false - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and input - schmitt. - $ref: "/schemas/pinctrl/pincfg-node.yaml" - - properties: - pinmux: - description: - integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are - defined as macros in <soc>-pinfunc.h directly. - - bias-disable: true - - bias-pull-up: true - - bias-pull-down: true - - input-enable: true - - input-disable: true - - output-enable: true - - output-low: true - - output-high: true - - input-schmitt-enable: true - - input-schmitt-disable: true - - drive-strength: - enum: [2, 4, 8, 12, 16] - - slew-rate: - enum: [0, 1] - - mediatek,pull-up-adv: - description: | - Pull up setings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - mediatek,pull-down-adv: - description: | - Pull down settings for 2 pull resistors, R0 and R1. User can - configure those special pins. Valid arguments are described as below: - 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. - 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. - 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. - 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] - - mediatek,tdsel: - description: | - An integer describing the steps for output level shifter duty - cycle when asserted (high pulse width adjustment). Valid arguments - are from 0 to 15. - $ref: /schemas/types.yaml#/definitions/uint32 - - mediatek,rdsel: - description: | - An integer describing the steps for input level shifter duty cycle - when asserted (high pulse width adjustment). Valid arguments are - from 0 to 63. - $ref: /schemas/types.yaml#/definitions/uint32 - - required: - - pinmux - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/irq.h> - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/pinctrl/mt6797-pinfunc.h> - - soc { - #address-cells = <2>; - #size-cells = <2>; - - pio: pinctrl@10005000 { - compatible = "mediatek,mt6797-pinctrl"; - reg = <0 0x10005000 0 0x1000>, - <0 0x10002000 0 0x400>, - <0 0x10002400 0 0x400>, - <0 0x10002800 0 0x400>, - <0 0x10002C00 0 0x400>; - reg-names = "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt"; - gpio-controller; - #gpio-cells = <2>; - - uart_pins_a: uart-0 { - pins1 { - pinmux = <MT6797_GPIO232__FUNC_URXD1>, - <MT6797_GPIO233__FUNC_UTXD1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 89b8f3dd67a1..216b356cd519 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -87,6 +87,8 @@ patternProperties: "wifi_led" "led" 1, 2 "i2c" "i2c" 3, 4 "uart1_0" "uart" 7, 8, 9, 10 + "uart1_rx_tx" "uart" 42, 43 + "uart1_cts_rts" "uart" 44, 45 "pcie_clk" "pcie" 9 "pcie_wake" "pcie" 10 "spi1_0" "spi" 11, 12, 13, 14 @@ -98,9 +100,11 @@ patternProperties: "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 "spi1_1" "spi" 23, 24, 25, 26 - "uart1_2" "uart" 29, 30, 31, 32 + "uart1_2_rx_tx" "uart" 29, 30 + "uart1_2_cts_rts" "uart" 31, 32 "uart1_1" "uart" 23, 24, 25, 26 - "uart2_0" "uart" 29, 30, 31, 32 + "uart2_0_rx_tx" "uart" 29, 30 + "uart2_0_cts_rts" "uart" 31, 32 "spi0" "spi" 33, 34, 35, 36 "spi0_wp_hold" "spi" 37, 38 "uart1_3_rx_tx" "uart" 35, 36 @@ -157,7 +161,7 @@ patternProperties: then: properties: groups: - enum: [emmc, emmc_rst] + enum: [emmc_45, emmc_51] - if: properties: function: @@ -197,7 +201,9 @@ patternProperties: then: properties: groups: - enum: [pcie_clk, pcie_wake, pcie_pereset] + items: + enum: [pcie_clk, pcie_wake, pcie_pereset] + maxItems: 3 - if: properties: function: @@ -205,7 +211,9 @@ patternProperties: then: properties: groups: - enum: [pwm0, pwm1_0, pwm1_1] + items: + enum: [pwm0, pwm1_0, pwm1_1] + maxItems: 2 - if: properties: function: @@ -213,7 +221,9 @@ patternProperties: then: properties: groups: - enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] + items: + enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] + maxItems: 2 - if: properties: function: @@ -221,8 +231,12 @@ patternProperties: then: properties: groups: - enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx, - uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, uart2] + items: + enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1, + uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx, + uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts, + uart2_1, uart0, uart1, uart2] + maxItems: 2 - if: properties: function: @@ -278,9 +292,23 @@ patternProperties: bias-disable: true - bias-pull-up: true - - bias-pull-down: true + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: | + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: | + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. input-enable: true @@ -332,6 +360,7 @@ examples: - | #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> soc { #address-cells = <2>; @@ -356,6 +385,27 @@ examples: interrupt-parent = <&gic>; #interrupt-cells = <2>; + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + uart1_pins: uart1-pins { mux { function = "uart"; @@ -363,6 +413,13 @@ examples: }; }; + uart1_3_pins: uart1-3-pins { + mux { + function = "uart"; + groups = "uart1_3_rx_tx", "uart1_3_cts_rts"; + }; + }; + uart2_pins: uart2-pins { mux { function = "uart"; @@ -370,5 +427,34 @@ examples: }; }; + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml index 73ae6e11410b..9399e0215526 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml @@ -46,8 +46,11 @@ properties: const: 2 interrupts: - description: The interrupt outputs to sysirq. - maxItems: 1 + description: Interrupt outputs to the system interrupt controller (sysirq). + minItems: 1 + items: + - description: EINT interrupt + - description: EINT event_b interrupt # PIN CONFIGURATION NODES patternProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt deleted file mode 100644 index 4023bad2fe39..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sx150x.txt +++ /dev/null @@ -1,72 +0,0 @@ -SEMTECH SX150x GPIO expander bindings - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -Required properties: -- compatible: should be one of : - "semtech,sx1501q", - "semtech,sx1502q", - "semtech,sx1503q", - "semtech,sx1504q", - "semtech,sx1505q", - "semtech,sx1506q", - "semtech,sx1507q", - "semtech,sx1508q", - "semtech,sx1509q". - -- reg: The I2C slave address for this device. - -- #gpio-cells: Should be 2. The first cell is the GPIO number and the - second cell is used to specify optional parameters: - bit 0: polarity (0: normal, 1: inverted) - -- gpio-controller: Marks the device as a GPIO controller. - -Optional properties : -- interrupts: Interrupt specifier for the controllers interrupt. - -- interrupt-controller: Marks the device as a interrupt controller. - -- semtech,probe-reset: Will trigger a reset of the GPIO expander on probe, - only for sx1507q, sx1508q and sx1509q - -The GPIO expander can optionally be used as an interrupt controller, in -which case it uses the default two cell specifier. - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - bias-disable: disable any pin bias, except the OSCIO pin - - bias-pull-up: pull up the pin, except the OSCIO pin - - bias-pull-down: pull down the pin, except the OSCIO pin - - bias-pull-pin-default: use pin-default pull state, except the OSCIO pin - - drive-push-pull: drive actively high and low - - drive-open-drain: drive with open drain only for sx1507q, sx1508q and sx1509q and except the OSCIO pin - - output-low: set the pin to output mode with low level - - output-high: set the pin to output mode with high level - -Example: - - i2c0gpio-expander@20{ - #gpio-cells = <2>; - #interrupt-cells = <2>; - compatible = "semtech,sx1506q"; - reg = <0x20>; - interrupt-parent = <&gpio_1>; - interrupts = <16 0>; - - gpio-controller; - interrupt-controller; - - pinctrl-names = "default"; - pinctrl-0 = <&gpio1_cfg_pins>; - - gpio1_cfg_pins: gpio1-cfg { - pins = "gpio1"; - bias-pull-up; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml new file mode 100644 index 000000000000..7585117c0f06 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDM670 TLMM block + +maintainers: + - Richard Acayan <mailingradian@gmail.com> + +description: | + The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sdm670-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm670-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm670-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdm670-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, + atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update, + lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, + mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, + pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable, + qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, + qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk, + sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, + tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, + vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@3400000 { + compatible = "qcom,sdm670-tlmm"; + reg = <0x03400000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + + qup-i2c9-state { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml new file mode 100644 index 000000000000..df429a396ba3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Semtech SX150x GPIO expander + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + enum: + - semtech,sx1501q + - semtech,sx1502q + - semtech,sx1503q + - semtech,sx1504q + - semtech,sx1505q + - semtech,sx1506q + - semtech,sx1507q + - semtech,sx1508q + - semtech,sx1509q + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + '#gpio-cells': + const: 2 + + gpio-controller: true + + semtech,probe-reset: + description: Will trigger a reset of the GPIO expander on probe + type: boolean + +patternProperties: + '-cfg$': + type: object + properties: + pins: true + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-push-pull: true + output-low: true + output-high: true + drive-open-drain: true + + required: + - pins + + allOf: + - $ref: "pincfg-node.yaml#" + - $ref: "pinmux-node.yaml#" + - if: + properties: + pins: + contains: + const: oscio + then: + properties: + bias-disable: false + bias-pull-up: false + bias-pull-down: false + bias-pull-pin-default: false + drive-open-drain: false + + additionalProperties: false + +required: + - compatible + - reg + - '#gpio-cells' + - gpio-controller + +allOf: + - $ref: "pinctrl.yaml#" + - if: + not: + properties: + compatible: + contains: + enum: + - semtech,sx1507q + - semtech,sx1508q + - semtech,sx1509q + then: + properties: + semtech,probe-reset: false + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-3]$' + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-7]$' + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-15]$' + - if: + properties: + compatible: + contains: + const: semtech,sx1507q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-3])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1508q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-7])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1509q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-15])$' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c@1000 { + reg = <0x1000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl@20 { + compatible = "semtech,sx1501q"; + reg = <0x20>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + interrupt-controller; + + gpio1-cfg { + pins = "gpio1"; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml index 30eaa62e1aed..74f75f669e77 100644 --- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml +++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml @@ -32,6 +32,9 @@ properties: - fsl,imx8qm-lpuart - fsl,imx8dxl-lpuart - const: fsl,imx8qxp-lpuart + - items: + - const: fsl,imxrt1050-lpuart + - const: fsl,imxrt1170-lpuart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml index a4f51f46b7a1..716c6afcca1f 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -31,6 +31,8 @@ properties: - enum: - fsl,imx6sl-gpt - fsl,imx6sx-gpt + - fsl,imxrt1050-gpt + - fsl,imxrt1170-gpt - const: fsl,imx6dl-gpt reg: diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index 71eefe5a023f..0022e930e93e 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -1238,7 +1238,7 @@ default state like this:: return PTR_ERR(foo->s); } - ret = pinctrl_select_state(foo->s); + ret = pinctrl_select_state(foo->p, foo->s); if (ret < 0) { /* FIXME: clean up "foo" here */ return ret; @@ -1399,11 +1399,11 @@ on the pins defined by group B:: if (IS_ERR(p)) ... - s1 = pinctrl_lookup_state(foo->p, "pos-A"); + s1 = pinctrl_lookup_state(p, "pos-A"); if (IS_ERR(s1)) ... - s2 = pinctrl_lookup_state(foo->p, "pos-B"); + s2 = pinctrl_lookup_state(p, "pos-B"); if (IS_ERR(s2)) ... } @@ -1411,14 +1411,14 @@ on the pins defined by group B:: foo_switch() { /* Enable on position A */ - ret = pinctrl_select_state(s1); + ret = pinctrl_select_state(p, s1); if (ret < 0) ... ... /* Enable on position B */ - ret = pinctrl_select_state(s2); + ret = pinctrl_select_state(p, s2); if (ret < 0) ... diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..4aece82ae6ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16284,7 +16284,7 @@ M: Sean Wang <sean.wang@kernel.org> L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml -F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6797-pinctrl.yaml +F: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml F: Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml F: Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml F: drivers/pinctrl/mediatek/ diff --git a/drivers/gpio/gpio-arizona.c b/drivers/gpio/gpio-arizona.c index 02f9ae19cd44..c15fda99120a 100644 --- a/drivers/gpio/gpio-arizona.c +++ b/drivers/gpio/gpio-arizona.c @@ -7,13 +7,12 @@ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> */ +#include <linux/gpio/driver.h> #include <linux/kernel.h> -#include <linux/slab.h> #include <linux/module.h> -#include <linux/gpio/driver.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> -#include <linux/seq_file.h> +#include <linux/slab.h> #include <linux/mfd/arizona/core.h> #include <linux/mfd/arizona/pdata.h> diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 318a7d95a1a8..a94da80d3a95 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -5,10 +5,9 @@ * Joel Stanley <joel@jms.id.au> */ -#include <asm/div64.h> #include <linux/clk.h> -#include <linux/gpio/driver.h> #include <linux/gpio/aspeed.h> +#include <linux/gpio/driver.h> #include <linux/hashtable.h> #include <linux/init.h> #include <linux/io.h> @@ -19,6 +18,8 @@ #include <linux/spinlock.h> #include <linux/string.h> +#include <asm/div64.h> + /* * These two headers aren't meant to be used by GPIO drivers. We need * them in order to access gpio_chip_hwgpio() which we need to implement diff --git a/drivers/gpio/gpio-da9052.c b/drivers/gpio/gpio-da9052.c index 559188d80c2b..6f3905f1b8f5 100644 --- a/drivers/gpio/gpio-da9052.c +++ b/drivers/gpio/gpio-da9052.c @@ -6,17 +6,16 @@ * * Author: David Dajun Chen <dchen@diasemi.com> */ -#include <linux/module.h> #include <linux/fs.h> -#include <linux/uaccess.h> -#include <linux/platform_device.h> #include <linux/gpio/driver.h> +#include <linux/module.h> +#include <linux/platform_device.h> #include <linux/syscalls.h> -#include <linux/seq_file.h> +#include <linux/uaccess.h> #include <linux/mfd/da9052/da9052.h> -#include <linux/mfd/da9052/reg.h> #include <linux/mfd/da9052/pdata.h> +#include <linux/mfd/da9052/reg.h> #define DA9052_INPUT 1 #define DA9052_OUTPUT_OPENDRAIN 2 diff --git a/drivers/gpio/gpio-mockup.c b/drivers/gpio/gpio-mockup.c index 523dfd17dd92..e6a7049bef64 100644 --- a/drivers/gpio/gpio-mockup.c +++ b/drivers/gpio/gpio-mockup.c @@ -19,6 +19,7 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/string_helpers.h> #include <linux/uaccess.h> diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index c871602fc5ba..d5626c572d24 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -24,6 +24,12 @@ #include <linux/of_device.h> #include <linux/bug.h> +#define IMX_SCU_WAKEUP_OFF 0 +#define IMX_SCU_WAKEUP_LOW_LVL 4 +#define IMX_SCU_WAKEUP_FALL_EDGE 5 +#define IMX_SCU_WAKEUP_RISE_EDGE 6 +#define IMX_SCU_WAKEUP_HIGH_LVL 7 + /* device type dependent stuff */ struct mxc_gpio_hwdata { unsigned dr_reg; @@ -61,6 +67,9 @@ struct mxc_gpio_port { u32 both_edges; struct mxc_gpio_reg_saved gpio_saved_reg; bool power_off; + u32 wakeup_pads; + bool is_pad_wakeup; + u32 pad_type[32]; const struct mxc_gpio_hwdata *hwdata; }; @@ -130,6 +139,9 @@ static const struct of_device_id mxc_gpio_dt_ids[] = { { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, + { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); @@ -203,6 +215,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) } writel(1 << gpio_idx, port->base + GPIO_ISR); + port->pad_type[gpio_idx] = type; return 0; } @@ -254,6 +267,9 @@ static void mx3_gpio_irq_handler(struct irq_desc *desc) struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); + if (port->is_pad_wakeup) + return; + chained_irq_enter(chip, desc); irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); @@ -306,11 +322,13 @@ static int gpio_set_wake_irq(struct irq_data *d, u32 enable) ret = enable_irq_wake(port->irq_high); else ret = enable_irq_wake(port->irq); + port->wakeup_pads |= (1 << gpio_idx); } else { if (port->irq_high && (gpio_idx >= 16)) ret = disable_irq_wake(port->irq_high); else ret = disable_irq_wake(port->irq); + port->wakeup_pads &= ~(1 << gpio_idx); } return ret; @@ -365,7 +383,6 @@ static int mxc_gpio_probe(struct platform_device *pdev) return -ENOMEM; port->dev = &pdev->dev; - port->hwdata = device_get_match_data(&pdev->dev); port->base = devm_platform_ioremap_resource(pdev, 0); @@ -498,6 +515,78 @@ static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); } +static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, + unsigned int offset, unsigned long conf) +{ + struct device_node *np = port->dev->of_node; + + if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || + of_device_is_compatible(np, "fsl,imx8qxp-gpio") || + of_device_is_compatible(np, "fsl,imx8qm-gpio")) + return (gpiochip_generic_config(&port->gc, offset, conf) == 0); + + return false; +} + +static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) +{ + unsigned long config; + bool ret = false; + int i, type; + + static const u32 pad_type_map[] = { + IMX_SCU_WAKEUP_OFF, /* 0 */ + IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ + IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */ + IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ + IMX_SCU_WAKEUP_OFF, /* 5 */ + IMX_SCU_WAKEUP_OFF, /* 6 */ + IMX_SCU_WAKEUP_OFF, /* 7 */ + IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ + }; + + for (i = 0; i < 32; i++) { + if ((port->wakeup_pads & (1 << i))) { + type = port->pad_type[i]; + if (enable) + config = pad_type_map[type]; + else + config = IMX_SCU_WAKEUP_OFF; + ret |= mxc_gpio_generic_config(port, i, config); + } + } + + return ret; +} + +static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) + port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); + + return 0; +} + +static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct mxc_gpio_port *port = platform_get_drvdata(pdev); + + if (port->wakeup_pads > 0) + mxc_gpio_set_pad_wakeup(port, false); + port->is_pad_wakeup = false; + + return 0; +} + +static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) +}; + static int mxc_gpio_syscore_suspend(void) { struct mxc_gpio_port *port; @@ -537,6 +626,7 @@ static struct platform_driver mxc_gpio_driver = { .name = "gpio-mxc", .of_match_table = mxc_gpio_dt_ids, .suppress_bind_attrs = true, + .pm = &mxc_gpio_dev_pm_ops, }, .probe = mxc_gpio_probe, }; diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index ebe1943b85dd..6e67867e1dcd 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -10,8 +10,8 @@ #include <linux/acpi.h> #include <linux/bitmap.h> -#include <linux/gpio/driver.h> #include <linux/gpio/consumer.h> +#include <linux/gpio/driver.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/interrupt.h> @@ -20,6 +20,7 @@ #include <linux/platform_data/pca953x.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <asm/unaligned.h> diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 6464056cb6ae..9fc1f3dd4190 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -8,22 +8,23 @@ * * Data sheet: ARM DDI 0190B, September 2000 */ -#include <linux/spinlock.h> +#include <linux/amba/bus.h> +#include <linux/bitops.h> +#include <linux/device.h> #include <linux/errno.h> +#include <linux/gpio/driver.h> #include <linux/init.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <linux/ioport.h> -#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/irqchip/chained_irq.h> #include <linux/module.h> -#include <linux/bitops.h> -#include <linux/gpio/driver.h> -#include <linux/device.h> -#include <linux/amba/bus.h> -#include <linux/slab.h> #include <linux/pinctrl/consumer.h> #include <linux/pm.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spinlock.h> #define GPIODIR 0x400 #define GPIOIS 0x404 diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 54d9fa7da9c1..fdc5bdcd5638 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -7,12 +7,13 @@ */ #include <linux/gpio/driver.h> +#include <linux/hte.h> #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/platform_device.h> -#include <linux/hte.h> +#include <linux/seq_file.h> #include <dt-bindings/gpio/tegra186-gpio.h> #include <dt-bindings/gpio/tegra194-gpio.h> diff --git a/drivers/gpio/gpio-wm8350.c b/drivers/gpio/gpio-wm8350.c index b1b131fb9804..2421cf606ed6 100644 --- a/drivers/gpio/gpio-wm8350.c +++ b/drivers/gpio/gpio-wm8350.c @@ -8,13 +8,12 @@ * */ -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/module.h> #include <linux/gpio/driver.h> +#include <linux/kernel.h> #include <linux/mfd/core.h> +#include <linux/module.h> #include <linux/platform_device.h> -#include <linux/seq_file.h> +#include <linux/slab.h> #include <linux/mfd/wm8350/core.h> #include <linux/mfd/wm8350/gpio.h> diff --git a/drivers/gpio/gpiolib-acpi.h b/drivers/gpio/gpiolib-acpi.h index 1ac6816839db..01e0cb480a00 100644 --- a/drivers/gpio/gpiolib-acpi.h +++ b/drivers/gpio/gpiolib-acpi.h @@ -8,7 +8,19 @@ #ifndef GPIOLIB_ACPI_H #define GPIOLIB_ACPI_H +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/types.h> + +#include <linux/gpio/consumer.h> + struct acpi_device; +struct device; +struct fwnode_handle; + +struct gpio_chip; +struct gpio_desc; +struct gpio_device; /** * struct acpi_gpio_info - ACPI GPIO specific information diff --git a/drivers/gpio/gpiolib-cdev.c b/drivers/gpio/gpiolib-cdev.c index 0cb6b468f364..65b2c09a4576 100644 --- a/drivers/gpio/gpiolib-cdev.c +++ b/drivers/gpio/gpiolib-cdev.c @@ -12,6 +12,7 @@ #include <linux/file.h> #include <linux/gpio.h> #include <linux/gpio/driver.h> +#include <linux/hte.h> #include <linux/interrupt.h> #include <linux/irqreturn.h> #include <linux/kernel.h> @@ -20,11 +21,12 @@ #include <linux/mutex.h> #include <linux/pinctrl/consumer.h> #include <linux/poll.h> +#include <linux/seq_file.h> #include <linux/spinlock.h> #include <linux/timekeeping.h> #include <linux/uaccess.h> #include <linux/workqueue.h> -#include <linux/hte.h> + #include <uapi/linux/gpio.h> #include "gpiolib.h" diff --git a/drivers/gpio/gpiolib-of.h b/drivers/gpio/gpiolib-of.h index 8af2bc899aab..1b5df39a952e 100644 --- a/drivers/gpio/gpiolib-of.h +++ b/drivers/gpio/gpiolib-of.h @@ -3,8 +3,17 @@ #ifndef GPIOLIB_OF_H #define GPIOLIB_OF_H +#include <linux/err.h> +#include <linux/errno.h> +#include <linux/types.h> + +#include <linux/notifier.h> + +struct device; + struct gpio_chip; -enum of_gpio_flags; +struct gpio_desc; +struct gpio_device; #ifdef CONFIG_OF_GPIO struct gpio_desc *of_find_gpio(struct device *dev, diff --git a/drivers/gpio/gpiolib-sysfs.h b/drivers/gpio/gpiolib-sysfs.h index ddd0e503f8eb..0f213bdb4732 100644 --- a/drivers/gpio/gpiolib-sysfs.h +++ b/drivers/gpio/gpiolib-sysfs.h @@ -5,6 +5,8 @@ #ifdef CONFIG_GPIO_SYSFS +struct gpio_device; + int gpiochip_sysfs_register(struct gpio_device *gdev); void gpiochip_sysfs_unregister(struct gpio_device *gdev); diff --git a/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c b/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c index cefe6b7bfdc4..4c5027a0480d 100644 --- a/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c +++ b/drivers/media/platform/st/sti/c8sectpfe/c8sectpfe-core.c @@ -24,16 +24,18 @@ #include <linux/module.h> #include <linux/of_gpio.h> #include <linux/of_platform.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinctrl.h> #include <linux/platform_device.h> -#include <linux/usb.h> #include <linux/slab.h> #include <linux/time.h> +#include <linux/usb.h> #include <linux/wait.h> -#include <linux/pinctrl/pinctrl.h> -#include "c8sectpfe-core.h" #include "c8sectpfe-common.h" +#include "c8sectpfe-core.h" #include "c8sectpfe-debugfs.h" + #include <media/dmxdev.h> #include <media/dvb_demux.h> #include <media/dvb_frontend.h> diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index ed46abc15d72..d49b77dcfcff 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -17,13 +17,15 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/slab.h> -#include <linux/spinlock.h> #include "../core.h" #include "../pinctrl-utils.h" @@ -38,7 +40,6 @@ * @clk: clock control * @soc: reference to soc_data * @base: pinctrl register base address - * @irq_chip: IRQ chip information * @num_irq: number of possible interrupts * @irq: interrupt numbers */ @@ -50,7 +51,6 @@ struct owl_pinctrl { struct clk *clk; const struct owl_pinctrl_soc_data *soc; void __iomem *base; - struct irq_chip irq_chip; unsigned int num_irq; unsigned int *irq; }; @@ -722,10 +722,11 @@ static void owl_gpio_irq_mask(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(data); const struct owl_gpio_port *port; + unsigned int gpio = hwirq; void __iomem *gpio_base; unsigned long flags; - unsigned int gpio = data->hwirq; u32 val; port = owl_gpio_get_port(pctrl, &gpio); @@ -745,22 +746,27 @@ static void owl_gpio_irq_mask(struct irq_data *data) OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + gpiochip_disable_irq(gc, hwirq); } static void owl_gpio_irq_unmask(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(data); const struct owl_gpio_port *port; + unsigned int gpio = hwirq; void __iomem *gpio_base; unsigned long flags; - unsigned int gpio = data->hwirq; u32 value; port = owl_gpio_get_port(pctrl, &gpio); if (WARN_ON(port == NULL)) return; + gpiochip_enable_irq(gc, hwirq); + gpio_base = pctrl->base + port->offset; raw_spin_lock_irqsave(&pctrl->lock, flags); @@ -780,20 +786,21 @@ static void owl_gpio_irq_ack(struct irq_data *data) { struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct owl_pinctrl *pctrl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(data); const struct owl_gpio_port *port; + unsigned int gpio = hwirq; void __iomem *gpio_base; unsigned long flags; - unsigned int gpio = data->hwirq; /* * Switch the interrupt edge to the opposite edge of the interrupt * which got triggered for the case of emulating both edges */ if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) { - if (owl_gpio_get(gc, gpio)) - irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING); + if (owl_gpio_get(gc, hwirq)) + irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING); else - irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING); + irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING); } port = owl_gpio_get_port(pctrl, &gpio); @@ -825,6 +832,16 @@ static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type) return 0; } +static const struct irq_chip owl_gpio_irqchip = { + .name = "owl-irq", + .irq_ack = owl_gpio_irq_ack, + .irq_mask = owl_gpio_irq_mask, + .irq_unmask = owl_gpio_irq_unmask, + .irq_set_type = owl_gpio_irq_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static void owl_gpio_irq_handler(struct irq_desc *desc) { struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc); @@ -875,14 +892,8 @@ static int owl_gpio_init(struct owl_pinctrl *pctrl) chip->parent = pctrl->dev; chip->owner = THIS_MODULE; - pctrl->irq_chip.name = chip->of_node->name; - pctrl->irq_chip.irq_ack = owl_gpio_irq_ack; - pctrl->irq_chip.irq_mask = owl_gpio_irq_mask; - pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask; - pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type; - gpio_irq = &chip->irq; - gpio_irq->chip = &pctrl->irq_chip; + gpio_irq_chip_set_chip(gpio_irq, &owl_gpio_irqchip); gpio_irq->handler = handle_simple_irq; gpio_irq->default_type = IRQ_TYPE_NONE; gpio_irq->parent_handler = owl_gpio_irq_handler; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index a30912a92f05..3945612900e6 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -5,6 +5,7 @@ #include <linux/mfd/syscon.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/string.h> #include "../core.h" diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index fd52a83387ef..73dbf29c002f 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -2,16 +2,19 @@ // Copyright (C) 2013-2017 Broadcom #include <linux/err.h> -#include <linux/io.h> #include <linux/init.h> +#include <linux/io.h> #include <linux/of.h> #include <linux/platform_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include <linux/regmap.h> +#include <linux/seq_file.h> #include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c index 5251460f6327..bf9597800954 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c @@ -13,12 +13,15 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/slab.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> + #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index 52fa2f4cd618..3df56a4ea510 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -16,17 +16,19 @@ * SoCs IOMUX controller. */ -#include <linux/kernel.h> -#include <linux/slab.h> +#include <linux/gpio/driver.h> #include <linux/interrupt.h> #include <linux/io.h> -#include <linux/gpio/driver.h> #include <linux/ioport.h> +#include <linux/kernel.h> #include <linux/of_device.h> #include <linux/of_irq.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/slab.h> + +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c index 960e253f0be4..04f4fca854cc 100644 --- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c @@ -9,12 +9,14 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c index db8f79920ff0..eb6298507c1d 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c @@ -20,12 +20,14 @@ #include <linux/err.h> #include <linux/io.h> #include <linux/of.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> #include "../core.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c index 3fda4446d70b..0b78cf611afe 100644 --- a/drivers/pinctrl/cirrus/pinctrl-lochnagar.c +++ b/drivers/pinctrl/cirrus/pinctrl-lochnagar.c @@ -15,10 +15,12 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/regmap.h> + +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include <linux/mfd/lochnagar.h> #include <linux/mfd/lochnagar1_regs.h> diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index e1cfbee3643a..bb589922d8c5 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -10,13 +10,14 @@ #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include <linux/mfd/madera/core.h> #include <linux/mfd/madera/registers.h> diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 9e57f4c62e60..41fd84738707 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -12,19 +12,21 @@ */ #define pr_fmt(fmt) "pinctrl core: " fmt -#include <linux/kernel.h> -#include <linux/kref.h> -#include <linux/export.h> -#include <linux/init.h> +#include <linux/debugfs.h> #include <linux/device.h> -#include <linux/slab.h> #include <linux/err.h> +#include <linux/export.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/kref.h> #include <linux/list.h> -#include <linux/debugfs.h> #include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/devinfo.h> #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> #ifdef CONFIG_GPIOLIB #include "../gpio/gpiolib.h" @@ -33,9 +35,8 @@ #include "core.h" #include "devicetree.h" -#include "pinmux.h" #include "pinconf.h" - +#include "pinmux.h" static bool pinctrl_dummy_state; @@ -1028,7 +1029,6 @@ static struct pinctrl *create_pinctrl(struct device *dev, struct pinctrl *p; const char *devname; struct pinctrl_maps *maps_node; - int i; const struct pinctrl_map *map; int ret; @@ -1054,7 +1054,7 @@ static struct pinctrl *create_pinctrl(struct device *dev, mutex_lock(&pinctrl_maps_mutex); /* Iterate over the pin control maps to locate the right ones */ - for_each_maps(maps_node, i, map) { + for_each_pin_map(maps_node, map) { /* Map must be for this device */ if (strcmp(map->dev_name, devname)) continue; @@ -1805,13 +1805,12 @@ static inline const char *map_type(enum pinctrl_map_type type) static int pinctrl_maps_show(struct seq_file *s, void *what) { struct pinctrl_maps *maps_node; - int i; const struct pinctrl_map *map; seq_puts(s, "Pinctrl maps:\n"); mutex_lock(&pinctrl_maps_mutex); - for_each_maps(maps_node, i, map) { + for_each_pin_map(maps_node, map) { seq_printf(s, "device %s\nstate %s\ntype %s (%d)\n", map->dev_name, map->name, map_type(map->type), map->type); diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h index 840103c40c14..530370443c19 100644 --- a/drivers/pinctrl/core.h +++ b/drivers/pinctrl/core.h @@ -9,12 +9,22 @@ */ #include <linux/kref.h> +#include <linux/list.h> #include <linux/mutex.h> #include <linux/radix-tree.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/types.h> + #include <linux/pinctrl/machine.h> +struct dentry; +struct device; +struct device_node; +struct module; + +struct pinctrl; +struct pinctrl_desc; struct pinctrl_gpio_range; +struct pinctrl_state; /** * struct pinctrl_dev - pin control class device @@ -242,8 +252,8 @@ extern int pinctrl_force_default(struct pinctrl_dev *pctldev); extern struct mutex pinctrl_maps_mutex; extern struct list_head pinctrl_maps; -#define for_each_maps(_maps_node_, _i_, _map_) \ - list_for_each_entry(_maps_node_, &pinctrl_maps, node) \ - for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \ - _i_ < _maps_node_->num_maps; \ - _i_++, _map_ = &_maps_node_->maps[_i_]) +#define for_each_pin_map(_maps_node_, _map_) \ + list_for_each_entry(_maps_node_, &pinctrl_maps, node) \ + for (unsigned int __i = 0; \ + __i < _maps_node_->num_maps && (_map_ = &_maps_node_->maps[__i]); \ + __i++) diff --git a/drivers/pinctrl/devicetree.h b/drivers/pinctrl/devicetree.h index efa80779de4f..def76aba99d1 100644 --- a/drivers/pinctrl/devicetree.h +++ b/drivers/pinctrl/devicetree.h @@ -5,8 +5,14 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include <linux/errno.h> + +struct device_node; struct of_phandle_args; +struct pinctrl; +struct pinctrl_dev; + #ifdef CONFIG_OF void pinctrl_dt_free_maps(struct pinctrl *p); diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 3a7d2de10b13..e9aef764138f 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -13,14 +13,16 @@ #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> -#include <linux/regmap.h> #include "../core.h" #include "../pinconf.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 70186448d2f4..3726c0ac2560 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -16,11 +16,13 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> #include "../core.h" #include "pinctrl-imx1.h" diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c index 11f31c90ad30..def683839ebe 100644 --- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c +++ b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c @@ -13,155 +13,135 @@ #include "pinctrl-imx.h" enum imxrt1050_pads { - IMXRT1050_PAD_RESERVE0 = 0, - IMXRT1050_PAD_RESERVE1 = 1, - IMXRT1050_PAD_RESERVE2 = 2, - IMXRT1050_PAD_RESERVE3 = 3, - IMXRT1050_PAD_RESERVE4 = 4, - IMXRT1050_PAD_RESERVE5 = 5, - IMXRT1050_PAD_RESERVE6 = 6, - IMXRT1050_PAD_RESERVE7 = 7, - IMXRT1050_PAD_RESERVE8 = 8, - IMXRT1050_PAD_RESERVE9 = 9, - IMXRT1050_IOMUXC_GPIO1_IO00 = 10, - IMXRT1050_IOMUXC_GPIO1_IO01 = 11, - IMXRT1050_IOMUXC_GPIO1_IO02 = 12, - IMXRT1050_IOMUXC_GPIO1_IO03 = 13, - IMXRT1050_IOMUXC_GPIO1_IO04 = 14, - IMXRT1050_IOMUXC_GPIO1_IO05 = 15, - IMXRT1050_IOMUXC_GPIO1_IO06 = 16, - IMXRT1050_IOMUXC_GPIO1_IO07 = 17, - IMXRT1050_IOMUXC_GPIO1_IO08 = 18, - IMXRT1050_IOMUXC_GPIO1_IO09 = 19, - IMXRT1050_IOMUXC_GPIO1_IO10 = 20, - IMXRT1050_IOMUXC_GPIO1_IO11 = 21, - IMXRT1050_IOMUXC_GPIO1_IO12 = 22, - IMXRT1050_IOMUXC_GPIO1_IO13 = 23, - IMXRT1050_IOMUXC_GPIO1_IO14 = 24, - IMXRT1050_IOMUXC_GPIO1_IO15 = 25, - IMXRT1050_IOMUXC_ENET_MDC = 26, - IMXRT1050_IOMUXC_ENET_MDIO = 27, - IMXRT1050_IOMUXC_ENET_TD3 = 28, - IMXRT1050_IOMUXC_ENET_TD2 = 29, - IMXRT1050_IOMUXC_ENET_TD1 = 30, - IMXRT1050_IOMUXC_ENET_TD0 = 31, - IMXRT1050_IOMUXC_ENET_TX_CTL = 32, - IMXRT1050_IOMUXC_ENET_TXC = 33, - IMXRT1050_IOMUXC_ENET_RX_CTL = 34, - IMXRT1050_IOMUXC_ENET_RXC = 35, - IMXRT1050_IOMUXC_ENET_RD0 = 36, - IMXRT1050_IOMUXC_ENET_RD1 = 37, - IMXRT1050_IOMUXC_ENET_RD2 = 38, - IMXRT1050_IOMUXC_ENET_RD3 = 39, - IMXRT1050_IOMUXC_SD1_CLK = 40, - IMXRT1050_IOMUXC_SD1_CMD = 41, - IMXRT1050_IOMUXC_SD1_DATA0 = 42, - IMXRT1050_IOMUXC_SD1_DATA1 = 43, - IMXRT1050_IOMUXC_SD1_DATA2 = 44, - IMXRT1050_IOMUXC_SD1_DATA3 = 45, - IMXRT1050_IOMUXC_SD1_DATA4 = 46, - IMXRT1050_IOMUXC_SD1_DATA5 = 47, - IMXRT1050_IOMUXC_SD1_DATA6 = 48, - IMXRT1050_IOMUXC_SD1_DATA7 = 49, - IMXRT1050_IOMUXC_SD1_RESET_B = 50, - IMXRT1050_IOMUXC_SD1_STROBE = 51, - IMXRT1050_IOMUXC_SD2_CD_B = 52, - IMXRT1050_IOMUXC_SD2_CLK = 53, - IMXRT1050_IOMUXC_SD2_CMD = 54, - IMXRT1050_IOMUXC_SD2_DATA0 = 55, - IMXRT1050_IOMUXC_SD2_DATA1 = 56, - IMXRT1050_IOMUXC_SD2_DATA2 = 57, - IMXRT1050_IOMUXC_SD2_DATA3 = 58, - IMXRT1050_IOMUXC_SD2_RESET_B = 59, - IMXRT1050_IOMUXC_SD2_WP = 60, - IMXRT1050_IOMUXC_NAND_ALE = 61, - IMXRT1050_IOMUXC_NAND_CE0 = 62, - IMXRT1050_IOMUXC_NAND_CE1 = 63, - IMXRT1050_IOMUXC_NAND_CE2 = 64, - IMXRT1050_IOMUXC_NAND_CE3 = 65, - IMXRT1050_IOMUXC_NAND_CLE = 66, - IMXRT1050_IOMUXC_NAND_DATA00 = 67, - IMXRT1050_IOMUXC_NAND_DATA01 = 68, - IMXRT1050_IOMUXC_NAND_DATA02 = 69, - IMXRT1050_IOMUXC_NAND_DATA03 = 70, - IMXRT1050_IOMUXC_NAND_DATA04 = 71, - IMXRT1050_IOMUXC_NAND_DATA05 = 72, - IMXRT1050_IOMUXC_NAND_DATA06 = 73, - IMXRT1050_IOMUXC_NAND_DATA07 = 74, - IMXRT1050_IOMUXC_NAND_DQS = 75, - IMXRT1050_IOMUXC_NAND_RE_B = 76, - IMXRT1050_IOMUXC_NAND_READY_B = 77, - IMXRT1050_IOMUXC_NAND_WE_B = 78, - IMXRT1050_IOMUXC_NAND_WP_B = 79, - IMXRT1050_IOMUXC_SAI5_RXFS = 80, - IMXRT1050_IOMUXC_SAI5_RXC = 81, - IMXRT1050_IOMUXC_SAI5_RXD0 = 82, - IMXRT1050_IOMUXC_SAI5_RXD1 = 83, - IMXRT1050_IOMUXC_SAI5_RXD2 = 84, - IMXRT1050_IOMUXC_SAI5_RXD3 = 85, - IMXRT1050_IOMUXC_SAI5_MCLK = 86, - IMXRT1050_IOMUXC_SAI1_RXFS = 87, - IMXRT1050_IOMUXC_SAI1_RXC = 88, - IMXRT1050_IOMUXC_SAI1_RXD0 = 89, - IMXRT1050_IOMUXC_SAI1_RXD1 = 90, - IMXRT1050_IOMUXC_SAI1_RXD2 = 91, - IMXRT1050_IOMUXC_SAI1_RXD3 = 92, - IMXRT1050_IOMUXC_SAI1_RXD4 = 93, - IMXRT1050_IOMUXC_SAI1_RXD5 = 94, - IMXRT1050_IOMUXC_SAI1_RXD6 = 95, - IMXRT1050_IOMUXC_SAI1_RXD7 = 96, - IMXRT1050_IOMUXC_SAI1_TXFS = 97, - IMXRT1050_IOMUXC_SAI1_TXC = 98, - IMXRT1050_IOMUXC_SAI1_TXD0 = 99, - IMXRT1050_IOMUXC_SAI1_TXD1 = 100, - IMXRT1050_IOMUXC_SAI1_TXD2 = 101, - IMXRT1050_IOMUXC_SAI1_TXD3 = 102, - IMXRT1050_IOMUXC_SAI1_TXD4 = 103, - IMXRT1050_IOMUXC_SAI1_TXD5 = 104, - IMXRT1050_IOMUXC_SAI1_TXD6 = 105, - IMXRT1050_IOMUXC_SAI1_TXD7 = 106, - IMXRT1050_IOMUXC_SAI1_MCLK = 107, - IMXRT1050_IOMUXC_SAI2_RXFS = 108, - IMXRT1050_IOMUXC_SAI2_RXC = 109, - IMXRT1050_IOMUXC_SAI2_RXD0 = 110, - IMXRT1050_IOMUXC_SAI2_TXFS = 111, - IMXRT1050_IOMUXC_SAI2_TXC = 112, - IMXRT1050_IOMUXC_SAI2_TXD0 = 113, - IMXRT1050_IOMUXC_SAI2_MCLK = 114, - IMXRT1050_IOMUXC_SAI3_RXFS = 115, - IMXRT1050_IOMUXC_SAI3_RXC = 116, - IMXRT1050_IOMUXC_SAI3_RXD = 117, - IMXRT1050_IOMUXC_SAI3_TXFS = 118, - IMXRT1050_IOMUXC_SAI3_TXC = 119, - IMXRT1050_IOMUXC_SAI3_TXD = 120, - IMXRT1050_IOMUXC_SAI3_MCLK = 121, - IMXRT1050_IOMUXC_SPDIF_TX = 122, - IMXRT1050_IOMUXC_SPDIF_RX = 123, - IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124, - IMXRT1050_IOMUXC_ECSPI1_SCLK = 125, - IMXRT1050_IOMUXC_ECSPI1_MOSI = 126, - IMXRT1050_IOMUXC_ECSPI1_MISO = 127, - IMXRT1050_IOMUXC_ECSPI1_SS0 = 128, - IMXRT1050_IOMUXC_ECSPI2_SCLK = 129, - IMXRT1050_IOMUXC_ECSPI2_MOSI = 130, - IMXRT1050_IOMUXC_ECSPI2_MISO = 131, - IMXRT1050_IOMUXC_ECSPI2_SS0 = 132, - IMXRT1050_IOMUXC_I2C1_SCL = 133, - IMXRT1050_IOMUXC_I2C1_SDA = 134, - IMXRT1050_IOMUXC_I2C2_SCL = 135, - IMXRT1050_IOMUXC_I2C2_SDA = 136, - IMXRT1050_IOMUXC_I2C3_SCL = 137, - IMXRT1050_IOMUXC_I2C3_SDA = 138, - IMXRT1050_IOMUXC_I2C4_SCL = 139, - IMXRT1050_IOMUXC_I2C4_SDA = 140, - IMXRT1050_IOMUXC_UART1_RXD = 141, - IMXRT1050_IOMUXC_UART1_TXD = 142, - IMXRT1050_IOMUXC_UART2_RXD = 143, - IMXRT1050_IOMUXC_UART2_TXD = 144, - IMXRT1050_IOMUXC_UART3_RXD = 145, - IMXRT1050_IOMUXC_UART3_TXD = 146, - IMXRT1050_IOMUXC_UART4_RXD = 147, - IMXRT1050_IOMUXC_UART4_TXD = 148, + IMXRT1050_PAD_RESERVE0, + IMXRT1050_PAD_RESERVE1, + IMXRT1050_PAD_RESERVE2, + IMXRT1050_PAD_RESERVE3, + IMXRT1050_PAD_RESERVE4, + IMXRT1050_PAD_EMC_00, + IMXRT1050_PAD_EMC_01, + IMXRT1050_PAD_EMC_02, + IMXRT1050_PAD_EMC_03, + IMXRT1050_PAD_EMC_04, + IMXRT1050_PAD_EMC_05, + IMXRT1050_PAD_EMC_06, + IMXRT1050_PAD_EMC_07, + IMXRT1050_PAD_EMC_08, + IMXRT1050_PAD_EMC_09, + IMXRT1050_PAD_EMC_10, + IMXRT1050_PAD_EMC_11, + IMXRT1050_PAD_EMC_12, + IMXRT1050_PAD_EMC_13, + IMXRT1050_PAD_EMC_14, + IMXRT1050_PAD_EMC_15, + IMXRT1050_PAD_EMC_16, + IMXRT1050_PAD_EMC_17, + IMXRT1050_PAD_EMC_18, + IMXRT1050_PAD_EMC_19, + IMXRT1050_PAD_EMC_20, + IMXRT1050_PAD_EMC_21, + IMXRT1050_PAD_EMC_22, + IMXRT1050_PAD_EMC_23, + IMXRT1050_PAD_EMC_24, + IMXRT1050_PAD_EMC_25, + IMXRT1050_PAD_EMC_26, + IMXRT1050_PAD_EMC_27, + IMXRT1050_PAD_EMC_28, + IMXRT1050_PAD_EMC_29, + IMXRT1050_PAD_EMC_30, + IMXRT1050_PAD_EMC_31, + IMXRT1050_PAD_EMC_32, + IMXRT1050_PAD_EMC_33, + IMXRT1050_PAD_EMC_34, + IMXRT1050_PAD_EMC_35, + IMXRT1050_PAD_EMC_36, + IMXRT1050_PAD_EMC_37, + IMXRT1050_PAD_EMC_38, + IMXRT1050_PAD_EMC_39, + IMXRT1050_PAD_EMC_40, + IMXRT1050_PAD_EMC_41, + IMXRT1050_PAD_AD_B0_00, + IMXRT1050_PAD_AD_B0_01, + IMXRT1050_PAD_AD_B0_02, + IMXRT1050_PAD_AD_B0_03, + IMXRT1050_PAD_AD_B0_04, + IMXRT1050_PAD_AD_B0_05, + IMXRT1050_PAD_AD_B0_06, + IMXRT1050_PAD_AD_B0_07, + IMXRT1050_PAD_AD_B0_08, + IMXRT1050_PAD_AD_B0_09, + IMXRT1050_PAD_AD_B0_10, + IMXRT1050_PAD_AD_B0_11, + IMXRT1050_PAD_AD_B0_12, + IMXRT1050_PAD_AD_B0_13, + IMXRT1050_PAD_AD_B0_14, + IMXRT1050_PAD_AD_B0_15, + IMXRT1050_PAD_AD_B1_00, + IMXRT1050_PAD_AD_B1_01, + IMXRT1050_PAD_AD_B1_02, + IMXRT1050_PAD_AD_B1_03, + IMXRT1050_PAD_AD_B1_04, + IMXRT1050_PAD_AD_B1_05, + IMXRT1050_PAD_AD_B1_06, + IMXRT1050_PAD_AD_B1_07, + IMXRT1050_PAD_AD_B1_08, + IMXRT1050_PAD_AD_B1_09, + IMXRT1050_PAD_AD_B1_10, + IMXRT1050_PAD_AD_B1_11, + IMXRT1050_PAD_AD_B1_12, + IMXRT1050_PAD_AD_B1_13, + IMXRT1050_PAD_AD_B1_14, + IMXRT1050_PAD_AD_B1_15, + IMXRT1050_PAD_B0_00, + IMXRT1050_PAD_B0_01, + IMXRT1050_PAD_B0_02, + IMXRT1050_PAD_B0_03, + IMXRT1050_PAD_B0_04, + IMXRT1050_PAD_B0_05, + IMXRT1050_PAD_B0_06, + IMXRT1050_PAD_B0_07, + IMXRT1050_PAD_B0_08, + IMXRT1050_PAD_B0_09, + IMXRT1050_PAD_B0_10, + IMXRT1050_PAD_B0_11, + IMXRT1050_PAD_B0_12, + IMXRT1050_PAD_B0_13, + IMXRT1050_PAD_B0_14, + IMXRT1050_PAD_B0_15, + IMXRT1050_PAD_B1_00, + IMXRT1050_PAD_B1_01, + IMXRT1050_PAD_B1_02, + IMXRT1050_PAD_B1_03, + IMXRT1050_PAD_B1_04, + IMXRT1050_PAD_B1_05, + IMXRT1050_PAD_B1_06, + IMXRT1050_PAD_B1_07, + IMXRT1050_PAD_B1_08, + IMXRT1050_PAD_B1_09, + IMXRT1050_PAD_B1_10, + IMXRT1050_PAD_B1_11, + IMXRT1050_PAD_B1_12, + IMXRT1050_PAD_B1_13, + IMXRT1050_PAD_B1_14, + IMXRT1050_PAD_B1_15, + IMXRT1050_PAD_SD_B0_00, + IMXRT1050_PAD_SD_B0_01, + IMXRT1050_PAD_SD_B0_02, + IMXRT1050_PAD_SD_B0_03, + IMXRT1050_PAD_SD_B0_04, + IMXRT1050_PAD_SD_B0_05, + IMXRT1050_PAD_SD_B1_00, + IMXRT1050_PAD_SD_B1_01, + IMXRT1050_PAD_SD_B1_02, + IMXRT1050_PAD_SD_B1_03, + IMXRT1050_PAD_SD_B1_04, + IMXRT1050_PAD_SD_B1_05, + IMXRT1050_PAD_SD_B1_06, + IMXRT1050_PAD_SD_B1_07, + IMXRT1050_PAD_SD_B1_08, + IMXRT1050_PAD_SD_B1_09, + IMXRT1050_PAD_SD_B1_10, + IMXRT1050_PAD_SD_B1_11, }; /* Pad names for the pinmux subsystem */ @@ -171,150 +151,130 @@ static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = { IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3), IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8), - IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD), - IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40), + IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14), + IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10), + IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11), }; static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = { diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index 735cedd0958a..9f78c9b29ddd 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -7,12 +7,15 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> + #include "../core.h" #include "pinctrl-mxs.h" diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c index 59b5f8a35111..ea261b6e7458 100644 --- a/drivers/pinctrl/freescale/pinctrl-scu.c +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -15,6 +15,11 @@ #include "../core.h" #include "pinctrl-imx.h" +#define IMX_SC_PAD_FUNC_GET_WAKEUP 9 +#define IMX_SC_PAD_FUNC_SET_WAKEUP 4 +#define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */ +#define IMX_SC_IRQ_PAD 2 /* Pad wakeup */ + enum pad_func_e { IMX_SC_PAD_FUNC_SET = 15, IMX_SC_PAD_FUNC_GET = 16, @@ -36,10 +41,18 @@ struct imx_sc_msg_resp_pad_get { u32 val; } __packed; +struct imx_sc_msg_gpio_set_pad_wakeup { + struct imx_sc_rpc_msg hdr; + u16 pad; + u8 wakeup; +} __packed __aligned(4); + static struct imx_sc_ipc *pinctrl_ipc_handle; int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) { + imx_scu_irq_group_enable(IMX_SC_IRQ_GROUP_WAKE, + IMX_SC_IRQ_PAD, true); return imx_scu_get_handle(&pinctrl_ipc_handle); } EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init); @@ -81,6 +94,23 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned int val; int ret; + if (num_configs == 1) { + struct imx_sc_msg_gpio_set_pad_wakeup wmsg; + + hdr = &wmsg.hdr; + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_PAD; + hdr->func = IMX_SC_PAD_FUNC_SET_WAKEUP; + hdr->size = 2; + wmsg.pad = pin_id; + wmsg.wakeup = *configs; + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &wmsg, true); + + dev_dbg(ipctl->dev, "wakeup pin_id: %d type: %ld\n", + pin_id, *configs); + return ret; + } + /* * Set mux and conf together in one IPC call */ diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 5c4fd16e5b01..11b81213922d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -16,12 +16,14 @@ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> #include <linux/types.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include "pinctrl-intel.h" diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 52ecd66ce357..b85140eaa9c4 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -14,12 +14,14 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> +#include <linux/seq_file.h> #include <linux/time.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> #include "../core.h" #include "pinctrl-intel.h" diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index 5d1abee30f8f..8d05dad38556 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -16,13 +16,15 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/types.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include "pinctrl-intel.h" diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index 5e752818adb4..527957ea35b7 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -12,8 +12,10 @@ #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/seq_file.h> + #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 526faaebaf77..1ec0413959e1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -8,7 +8,11 @@ * */ +#include <dt-bindings/pinctrl/mt65xx.h> #include <linux/gpio/driver.h> + +#include <linux/pinctrl/consumer.h> + #include "pinctrl-moore.h" #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME @@ -105,7 +109,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); u32 param = pinconf_to_config_param(*config); - int val, val2, err, reg, ret = 1; + int val, val2, err, pullup, reg, ret = 1; const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; @@ -114,7 +118,13 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_disable_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) + return -EINVAL; + } else if (hw->soc->bias_disable_get) { err = hw->soc->bias_disable_get(hw, desc, &ret); if (err) return err; @@ -123,7 +133,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) + return -EINVAL; + if (!pullup) + return -EINVAL; + } else if (hw->soc->bias_get) { err = hw->soc->bias_get(hw, desc, 1, &ret); if (err) return err; @@ -132,7 +150,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) + return -EINVAL; + if (pullup) + return -EINVAL; + } else if (hw->soc->bias_get) { err = hw->soc->bias_get(hw, desc, 0, &ret); if (err) return err; @@ -235,7 +261,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_disable_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); + if (err) + return err; + } else if (hw->soc->bias_disable_set) { err = hw->soc->bias_disable_set(hw, desc); if (err) return err; @@ -244,7 +274,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, } break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 1, arg); + if (err) + return err; + } else if (hw->soc->bias_set) { err = hw->soc->bias_set(hw, desc, 1); if (err) return err; @@ -253,7 +287,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, } break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 0, arg); + if (err) + return err; + } else if (hw->soc->bias_set) { err = hw->soc->bias_set(hw, desc, 0); if (err) return err; diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index f26869f1a367..db3497d6787a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -316,10 +316,10 @@ static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), @@ -354,10 +354,10 @@ static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), @@ -392,10 +392,10 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), @@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), }; +static const unsigned int mt7986_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ +}; + static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), @@ -675,11 +729,17 @@ static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, }; static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; -static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; -static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; +static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; +static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; + +static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; +static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; -static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; -static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; +static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; +static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; + +static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; +static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; @@ -708,6 +768,12 @@ static int mt7986_pcie_reset_funcs[] = { 1, }; static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; +static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; +static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; + +static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; +static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; + static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; @@ -749,6 +815,8 @@ static const struct group_desc mt7986_groups[] = { PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), PINCTRL_PIN_GROUP("i2c", mt7986_i2c), PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), + PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), + PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), @@ -760,8 +828,10 @@ static const struct group_desc mt7986_groups[] = { PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), - PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), - PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), + PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), + PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), PINCTRL_PIN_GROUP("spi0", mt7986_spi0), PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), @@ -800,7 +870,9 @@ static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", }; static const char *mt7986_spi_groups[] = { "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; static const char *mt7986_uart_groups[] = { - "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", + "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", + "uart1_2_rx_tx", "uart1_2_cts_rts", + "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", "uart2_0", "uart2_1", "uart0", "uart1", "uart2", }; static const char *mt7986_wdt_groups[] = { "watchdog", }; @@ -848,6 +920,7 @@ static struct mtk_pin_soc mt7986a_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, @@ -869,6 +942,7 @@ static struct mtk_pin_soc mt7986b_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 57f37a294063..42b48136ab77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,6 +416,23 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; +static int mt8365_set_clr_mode(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup) +{ + int ret; + + ret = regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit); + if (ret) + return -EINVAL; + + ret = regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit); + if (ret) + return -EINVAL; + + return 0; +} + static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .pins = mtk_pins_mt8365, .npins = ARRAY_SIZE(mtk_pins_mt8365), @@ -431,6 +448,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, + .mt8365_set_clr_mode = mt8365_set_clr_mode, .dir_offset = 0x0140, .dout_offset = 0x00A0, .din_offset = 0x0000, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f25b3e09386b..076ae0b38e3d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -330,6 +330,21 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, return -EINVAL; } + if (pctl->devdata->mt8365_set_clr_mode) { + bit = pin & pctl->devdata->mode_mask; + reg_pullen = mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset; + reg_pullsel = mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset; + ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), + bit, reg_pullen, reg_pullsel, + enable, isup); + if (ret) + return -EINVAL; + + return 0; + } + bit = BIT(pin & pctl->devdata->mode_mask); if (enable) reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 6fe8564334c9..11afa12a96cb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -216,7 +216,10 @@ struct mtk_eint_offsets { * @spec_dir_set: In very few SoCs, direction control registers are not * arranged continuously, they may be cut to parts. So they need special * dir setting. - + * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because they + * need to use the main R/W register to read/update/write the modes instead of + * the SET/CLR register. + * * @dir_offset: The direction register offset. * @pullen_offset: The pull-up/pull-down enable register offset. * @pinmux_offset: The pinmux register offset. @@ -252,6 +255,9 @@ struct mtk_pinctrl_devdata { void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, unsigned int mode); void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); + int (*mt8365_set_clr_mode)(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup); unsigned int dir_offset; unsigned int ies_offset; unsigned int smt_offset; diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 74517e810958..475f4172d508 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -11,7 +11,12 @@ #include <linux/gpio/driver.h> #include <linux/module.h> +#include <linux/seq_file.h> + +#include <linux/pinctrl/consumer.h> + #include <dt-bindings/pinctrl/mt65xx.h> + #include "pinctrl-paris.h" #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 8ef0a97d2bf5..8e6aac4164df 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -6,20 +6,22 @@ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */ -#include <linux/platform_device.h> -#include <linux/slab.h> +#include <linux/err.h> +#include <linux/gpio/driver.h> #include <linux/io.h> +#include <linux/mfd/syscon.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_platform.h> -#include <linux/err.h> -#include <linux/gpio/driver.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/mfd/syscon.h> -#include <linux/regmap.h> #include "pinctrl-mvebu.h" diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 1c4e89b046de..ff5bcea172e8 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -11,14 +11,17 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> + +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/property.h> -#include <linux/regmap.h> /* GCR registers */ #define NPCM7XX_GCR_PDID 0x00 diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 8193b92da403..2d1c1652cfd9 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -49,7 +49,6 @@ struct wpcm450_bank; struct wpcm450_gpio { struct gpio_chip gc; struct wpcm450_pinctrl *pctrl; - struct irq_chip irqc; const struct wpcm450_bank *bank; }; @@ -142,7 +141,8 @@ static void wpcm450_gpio_irq_ack(struct irq_data *d) static void wpcm450_gpio_irq_mask(struct irq_data *d) { - struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct wpcm450_gpio *gpio = gpiochip_get_data(gc); struct wpcm450_pinctrl *pctrl = gpio->pctrl; unsigned long flags; unsigned long even; @@ -157,11 +157,14 @@ static void wpcm450_gpio_irq_mask(struct irq_data *d) __assign_bit(bit, &even, 0); iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); } static void wpcm450_gpio_irq_unmask(struct irq_data *d) { - struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct wpcm450_gpio *gpio = gpiochip_get_data(gc); struct wpcm450_pinctrl *pctrl = gpio->pctrl; unsigned long flags; unsigned long even; @@ -171,6 +174,8 @@ static void wpcm450_gpio_irq_unmask(struct irq_data *d) if (bit < 0) return; + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + raw_spin_lock_irqsave(&pctrl->lock, flags); even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); __assign_bit(bit, &even, 1); @@ -293,6 +298,8 @@ static const struct irq_chip wpcm450_gpio_irqchip = { .irq_unmask = wpcm450_gpio_irq_unmask, .irq_mask = wpcm450_gpio_irq_mask, .irq_set_type = wpcm450_gpio_set_irq_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static void wpcm450_gpio_irqhandler(struct irq_desc *desc) @@ -621,6 +628,9 @@ struct wpcm450_pincfg { int fn1, reg1, bit1; }; +/* Add this value to bit0 or bit1 to indicate that the MFSEL bit is inverted */ +#define INV BIT(5) + static const struct wpcm450_pincfg pincfg[] = { /* PIN FUNCTION 1 FUNCTION 2 */ WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), @@ -658,7 +668,7 @@ static const struct wpcm450_pincfg pincfg[] = { WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), - WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5 | INV, none, NONE, 0), WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ @@ -718,8 +728,8 @@ static const struct wpcm450_pincfg pincfg[] = { WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), - WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), - WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17 | INV, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17 | INV, none, NONE, 0), WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), @@ -793,6 +803,19 @@ static const struct pinctrl_pin_desc wpcm450_pins[] = { WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), }; +/* Helper function to update MFSEL field according to the selected function */ +static void wpcm450_update_mfsel(struct regmap *gcr_regmap, int reg, int bit, int fn, int fn_selected) +{ + bool value = (fn == fn_selected); + + if (bit & INV) { + value = !value; + bit &= ~INV; + } + + regmap_update_bits(gcr_regmap, reg, BIT(bit), value ? BIT(bit) : 0); +} + /* Enable mode in pin group */ static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, int npins, int func) @@ -804,13 +827,11 @@ static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, cfg = &pincfg[pin[i]]; if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { if (cfg->reg0) - regmap_update_bits(gcr_regmap, cfg->reg0, - BIT(cfg->bit0), - (cfg->fn0 == func) ? BIT(cfg->bit0) : 0); + wpcm450_update_mfsel(gcr_regmap, cfg->reg0, + cfg->bit0, cfg->fn0, func); if (cfg->reg1) - regmap_update_bits(gcr_regmap, cfg->reg1, - BIT(cfg->bit1), - (cfg->fn1 == func) ? BIT(cfg->bit1) : 0); + wpcm450_update_mfsel(gcr_regmap, cfg->reg1, + cfg->bit1, cfg->fn1, func); } } } @@ -1068,9 +1089,8 @@ static int wpcm450_gpio_register(struct platform_device *pdev, gpio->gc.fwnode = child; gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; - gpio->irqc = wpcm450_gpio_irqchip; girq = &gpio->gc.irq; - girq->chip = &gpio->irqc; + gpio_irq_chip_set_chip(girq, &wpcm450_gpio_irqchip); girq->parent_handler = wpcm450_gpio_irqhandler; girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, sizeof(*girq->parents), GFP_KERNEL); diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index be7311373299..694bfc9961fa 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -10,6 +10,16 @@ * Author: Linus Walleij <linus.walleij@linaro.org> */ +#include <linux/errno.h> + +struct dentry; +struct device_node; +struct seq_file; + +struct pinctrl_dev; +struct pinctrl_map; +struct pinctrl_setting; + #ifdef CONFIG_PINCONF int pinconf_check_ops(struct pinctrl_dev *pctldev); diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 6be896871718..9bc6e3922e78 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -628,13 +628,15 @@ static bool do_amd_gpio_irq_handler(int irq, void *dev_id) /* Each status bit covers four pins */ for (i = 0; i < 4; i++) { regval = readl(regs + i); - /* caused wake on resume context for shared IRQ */ - if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) { + + if (regval & PIN_IRQ_PENDING) dev_dbg(&gpio_dev->pdev->dev, - "Waking due to GPIO %d: 0x%x", + "GPIO %d is active: 0x%x", irqnr + i, regval); + + /* caused wake on resume context for shared IRQ */ + if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) return true; - } if (!(regval & PIN_IRQ_PENDING) || !(regval & BIT(INTERRUPT_MASK_OFF))) diff --git a/drivers/pinctrl/pinctrl-apple-gpio.c b/drivers/pinctrl/pinctrl-apple-gpio.c index 2490384ef1b8..3751c7de37aa 100644 --- a/drivers/pinctrl/pinctrl-apple-gpio.c +++ b/drivers/pinctrl/pinctrl-apple-gpio.c @@ -11,6 +11,8 @@ */ #include <dt-bindings/pinctrl/apple.h> + +#include <linux/bitfield.h> #include <linux/bits.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> @@ -18,11 +20,12 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #include "pinctrl-utils.h" #include "core.h" #include "pinmux.h" diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 82b921fd630d..39b233f73e13 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -7,18 +7,22 @@ */ #include <dt-bindings/pinctrl/at91.h> + #include <linux/clk.h> #include <linux/gpio/driver.h> +#include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> -#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> + #include "core.h" #include "pinconf.h" #include "pinctrl-utils.h" @@ -775,6 +779,8 @@ static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev, return -EINVAL; arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET; break; + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; default: return -ENOTSUPP; } @@ -883,6 +889,8 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n"); } break; + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; default: dev_warn(pctldev->dev, "unsupported configuration parameter: %u\n", @@ -897,6 +905,25 @@ static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev, return 0; } +static int atmel_conf_pin_config_set(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs, + unsigned num_configs) +{ + struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin); + + return atmel_conf_pin_config_group_set(pctldev, grp->pin, configs, num_configs); +} + +static int atmel_conf_pin_config_get(struct pinctrl_dev *pctldev, + unsigned pin, + unsigned long *configs) +{ + struct atmel_group *grp = atmel_pctl_find_group_by_pin(pctldev, pin); + + return atmel_conf_pin_config_group_get(pctldev, grp->pin, configs); +} + static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int pin_id) @@ -944,6 +971,8 @@ static const struct pinconf_ops atmel_confops = { .pin_config_group_get = atmel_conf_pin_config_group_get, .pin_config_group_set = atmel_conf_pin_config_group_set, .pin_config_dbg_show = atmel_conf_pin_config_dbg_show, + .pin_config_set = atmel_conf_pin_config_set, + .pin_config_get = atmel_conf_pin_config_get, }; static struct pinctrl_desc atmel_pinctrl_desc = { @@ -1134,6 +1163,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->gpio_chip->label = dev_name(dev); atmel_pioctrl->gpio_chip->parent = dev; atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names; + atmel_pioctrl->gpio_chip->set_config = gpiochip_generic_config; atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev, atmel_pioctrl->nbanks, diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 81dbffab621f..1e1813d7c550 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -7,22 +7,24 @@ #include <linux/clk.h> #include <linux/err.h> +#include <linux/gpio/driver.h> #include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> #include <linux/of.h> -#include <linux/of_device.h> #include <linux/of_address.h> +#include <linux/of_device.h> #include <linux/of_irq.h> +#include <linux/pm.h> +#include <linux/seq_file.h> #include <linux/slab.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/gpio/driver.h> + +/* Since we request GPIOs from ourself */ +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -/* Since we request GPIOs from ourself */ -#include <linux/pinctrl/consumer.h> -#include <linux/pm.h> #include "pinctrl-at91.h" #include "core.h" diff --git a/drivers/pinctrl/pinctrl-axp209.c b/drivers/pinctrl/pinctrl-axp209.c index 7ab20ac15391..0bc1b381a2b8 100644 --- a/drivers/pinctrl/pinctrl-axp209.c +++ b/drivers/pinctrl/pinctrl-axp209.c @@ -16,13 +16,15 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/slab.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #define AXP20X_GPIO_FUNCTIONS 0x7 #define AXP20X_GPIO_FUNCTION_OUT_LOW 0 #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1 diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index a8e267237435..b0000fe5b31d 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -9,10 +9,12 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/slab.h> #include "core.h" #include "pinctrl-utils.h" diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 68509a2301b8..564fbaabcdb8 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -20,10 +20,12 @@ #include <linux/property.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <linux/seq_file.h> -#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> /* Fast access registers */ @@ -551,36 +553,7 @@ out: static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) { - struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); - u8 port = cypress_get_port(chip, off); - u8 bit = cypress_get_pin_mask(chip, off); - int ret; - - mutex_lock(&chip->i2c_lock); - ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); - if (ret) - goto out; - - ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); - if (ret) - goto out; - - if (test_bit(off, chip->push_pull)) { - /* - * Disable driving the pin by forcing it to HighZ. Only setting the - * direction register isn't sufficient in Push-Pull mode. - */ - ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); - if (ret) - goto out; - - __clear_bit(off, chip->push_pull); - } - -out: - mutex_unlock(&chip->i2c_lock); - - return ret; + return pinctrl_gpio_direction_input(gc->base + off); } static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, @@ -597,19 +570,7 @@ static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, if (ret) return ret; - mutex_lock(&chip->i2c_lock); - /* Select port... */ - ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); - if (ret) - goto out; - - /* ...then direction */ - ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0); - -out: - mutex_unlock(&chip->i2c_lock); - - return ret; + return pinctrl_gpio_direction_output(gc->base + off); } static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) @@ -850,6 +811,8 @@ static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) { struct gpio_chip *gc = &chip->gpio_chip; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; gc->direction_input = cy8c95x0_gpio_direction_input; gc->direction_output = cy8c95x0_gpio_direction_output; gc->get = cy8c95x0_gpio_get_value; @@ -1124,9 +1087,7 @@ static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned in return 0; } -static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip, - unsigned int val, - unsigned long off) +static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) { u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); @@ -1137,10 +1098,23 @@ static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip, if (ret < 0) return ret; - ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0); + return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0); +} + +static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, + unsigned int selector, unsigned int group) +{ + u8 port = cypress_get_port(chip, group); + u8 bit = cypress_get_pin_mask(chip, group); + int ret; + + ret = cy8c95x0_set_mode(chip, group, selector); if (ret < 0) return ret; + if (selector == 0) + return 0; + /* Set direction to output & set output to 1 so that PWM can work */ ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); if (ret < 0) @@ -1156,7 +1130,67 @@ static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, int ret; mutex_lock(&chip->i2c_lock); - ret = cy8c95x0_pinmux_cfg(chip, selector, group); + ret = cy8c95x0_pinmux_mode(chip, selector, group); + mutex_unlock(&chip->i2c_lock); + + return ret; +} + +static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); + int ret; + + mutex_lock(&chip->i2c_lock); + ret = cy8c95x0_set_mode(chip, pin, false); + mutex_unlock(&chip->i2c_lock); + + return ret; +} + +static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, + unsigned int pin, bool input) +{ + u8 port = cypress_get_port(chip, pin); + u8 bit = cypress_get_pin_mask(chip, pin); + int ret; + + /* Select port... */ + ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); + if (ret) + return ret; + + /* ...then direction */ + ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0); + if (ret) + return ret; + + /* + * Disable driving the pin by forcing it to HighZ. Only setting + * the direction register isn't sufficient in Push-Pull mode. + */ + if (input && test_bit(pin, chip->push_pull)) { + ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); + if (ret) + return ret; + + __clear_bit(pin, chip->push_pull); + } + + return 0; +} + +static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); + int ret; + + mutex_lock(&chip->i2c_lock); + ret = cy8c95x0_pinmux_direction(chip, pin, input); mutex_unlock(&chip->i2c_lock); return ret; @@ -1167,6 +1201,8 @@ static const struct pinmux_ops cy8c95x0_pmxops = { .get_function_name = cy8c95x0_get_function_name, .get_function_groups = cy8c95x0_get_function_groups, .set_mux = cy8c95x0_set_mux, + .gpio_request_enable = cy8c95x0_gpio_request_enable, + .gpio_set_direction = cy8c95x0_gpio_set_direction, .strict = true, }; diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index 7521a924dffb..2eab14f86fa3 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -7,17 +7,18 @@ * Copyright (C) 2012 John Crispin <john@phrozen.org> */ +#include <linux/err.h> +#include <linux/export.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> -#include <linux/slab.h> -#include <linux/export.h> -#include <linux/err.h> #include <linux/module.h> #include <linux/of.h> -#include <linux/of_platform.h> #include <linux/of_address.h> #include <linux/of_gpio.h> +#include <linux/of_platform.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> #include "pinctrl-lantiq.h" diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index 5870956a993a..631612539af7 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -10,14 +10,16 @@ #include <linux/io.h> #include <linux/mfd/syscon.h> #include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/platform_device.h> -#include <linux/slab.h> -#include <linux/regmap.h> #include "pinctrl-utils.h" diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 7e732076dedf..dbc25a60fbff 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -14,16 +14,18 @@ #include <linux/kernel.h> #include <linux/mod_devicetable.h> #include <linux/of.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/seq_file.h> #include <linux/slab.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #include "core.h" #include "pinconf.h" #include "pinmux.h" diff --git a/drivers/pinctrl/pinctrl-k210.c b/drivers/pinctrl/pinctrl-k210.c index ecab6bf63dc6..288e44457fec 100644 --- a/drivers/pinctrl/pinctrl-k210.c +++ b/drivers/pinctrl/pinctrl-k210.c @@ -3,18 +3,20 @@ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ -#include <linux/io.h> -#include <linux/of_device.h> +#include <linux/bitfield.h> #include <linux/clk.h> +#include <linux/io.h> #include <linux/mfd/syscon.h> +#include <linux/of_device.h> #include <linux/platform_device.h> -#include <linux/bitfield.h> #include <linux/regmap.h> +#include <linux/seq_file.h> #include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include <dt-bindings/pinctrl/k210-fpioa.h> diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index 626e02d7a1ba..7145b8b0dfd4 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -6,12 +6,13 @@ * Copyright (C) 2012 John Crispin <john@phrozen.org> */ -#include <linux/module.h> #include <linux/device.h> #include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> #include <linux/slab.h> -#include <linux/of.h> #include "pinctrl-lantiq.h" diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h index c1f80886d1a8..efb25fc34f14 100644 --- a/drivers/pinctrl/pinctrl-lantiq.h +++ b/drivers/pinctrl/pinctrl-lantiq.h @@ -10,11 +10,12 @@ #define __PINCTRL_LANTIQ_H #include <linux/clkdev.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinmux.h> + #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> #include "core.h" diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c index ed9bf2c89998..13c041dd2ce0 100644 --- a/drivers/pinctrl/pinctrl-lpc18xx.c +++ b/drivers/pinctrl/pinctrl-lpc18xx.c @@ -10,13 +10,15 @@ #include <linux/bitops.h> #include <linux/clk.h> -#include <linux/io.h> #include <linux/init.h> +#include <linux/io.h> #include <linux/of.h> #include <linux/of_device.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf-generic.h> #include "core.h" #include "pinctrl-utils.h" diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index af27b72c8958..4794602316e7 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -15,13 +15,15 @@ #include <linux/mfd/ocelot.h> #include <linux/mod_devicetable.h> #include <linux/module.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/spinlock.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + #include "core.h" #include "pinconf.h" diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 62ce3957abe4..d1dea0de0129 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -14,15 +14,17 @@ #include <linux/of_device.h> #include <linux/of_irq.h> #include <linux/of_platform.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> #include <linux/platform_device.h> #include <linux/regmap.h> #include <linux/reset.h> #include <linux/slab.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #include "core.h" #include "pinconf.h" #include "pinmux.h" @@ -2038,6 +2040,11 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev, return devm_regmap_init_mmio(&pdev->dev, base, ®map_config); } +static void ocelot_destroy_workqueue(void *data) +{ + destroy_workqueue(data); +} + static int ocelot_pinctrl_probe(struct platform_device *pdev) { const struct ocelot_match_data *data; @@ -2069,6 +2076,11 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) if (!info->wq) return -ENOMEM; + ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue, + info->wq); + if (ret) + return ret; + info->pincfg_data = &data->pincfg_data; reset = devm_reset_control_get_optional_shared(dev, "switch"); @@ -2110,15 +2122,6 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) return 0; } -static int ocelot_pinctrl_remove(struct platform_device *pdev) -{ - struct ocelot_pinctrl *info = platform_get_drvdata(pdev); - - destroy_workqueue(info->wq); - - return 0; -} - static struct platform_driver ocelot_pinctrl_driver = { .driver = { .name = "pinctrl-ocelot", @@ -2126,7 +2129,6 @@ static struct platform_driver ocelot_pinctrl_driver = { .suppress_bind_attrs = true, }, .probe = ocelot_pinctrl_probe, - .remove = ocelot_pinctrl_remove, }; module_platform_driver(ocelot_pinctrl_driver); diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 67bec7ea0f8b..3a515414927e 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -16,17 +16,17 @@ #include <linux/err.h> #include <linux/list.h> #include <linux/interrupt.h> - #include <linux/irqchip/chained_irq.h> - #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/seq_file.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf-generic.h> #include <linux/platform_data/pinctrl-single.h> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index cf7f9cbe6044..1409339f0279 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -5,21 +5,26 @@ * Srinivas Kandagatla <srinivas.kandagatla@st.com> */ -#include <linux/init.h> -#include <linux/module.h> -#include <linux/slab.h> #include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> #include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> #include <linux/of.h> -#include <linux/of_irq.h> #include <linux/of_address.h> -#include <linux/gpio/driver.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> #include <linux/regmap.h> -#include <linux/mfd/syscon.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/string_helpers.h> + +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/platform_device.h> + #include "core.h" /* PIO Block registers */ @@ -1175,7 +1180,7 @@ static int st_pctl_dt_calculate_pin(struct st_pinctrl *info, for (i = 0; i < info->nbanks; i++) { chip = &info->banks[i].gpio_chip; - if (chip->of_node == np) { + if (chip->fwnode == of_fwnode_handle(np)) { if (offset < chip->ngpio) retval = chip->base + offset; break; @@ -1518,7 +1523,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info, bank->gpio_chip = st_gpio_template; bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK; bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK; - bank->gpio_chip.of_node = np; + bank->gpio_chip.fwnode = of_fwnode_handle(np); bank->gpio_chip.parent = dev; spin_lock_init(&bank->lock); diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index ab4dde40d3ed..1181c4b506b1 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -10,6 +10,8 @@ #include <linux/mfd/stmfx.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> + #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinmux.h> diff --git a/drivers/pinctrl/pinctrl-utils.h b/drivers/pinctrl/pinctrl-utils.h index cec407a8cc4e..4108ee2dd6d0 100644 --- a/drivers/pinctrl/pinctrl-utils.h +++ b/drivers/pinctrl/pinctrl-utils.h @@ -9,6 +9,11 @@ #ifndef __PINCTRL_UTILS_H__ #define __PINCTRL_UTILS_H__ +#include <linux/pinctrl/machine.h> + +struct pinctrl_dev; +struct pinctrl_map; + int pinctrl_utils_reserve_map(struct pinctrl_dev *pctldev, struct pinctrl_map **map, unsigned *reserved_maps, unsigned *num_maps, unsigned reserve); diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7d2fbf8a02cd..f2be341f73e1 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -14,10 +14,13 @@ #include <linux/module.h> #include <linux/of_address.h> #include <linux/platform_device.h> + #include <linux/firmware/xlnx-zynqmp.h> -#include <linux/pinctrl/pinmux.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> #include "core.h" #include "pinctrl-utils.h" diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index f94d43b082d9..6bd7ac37a0e0 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -13,19 +13,22 @@ #define pr_fmt(fmt) "pinmux core: " fmt #include <linux/ctype.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> +#include <linux/debugfs.h> #include <linux/device.h> -#include <linux/slab.h> -#include <linux/radix-tree.h> #include <linux/err.h> +#include <linux/init.h> +#include <linux/kernel.h> #include <linux/list.h> -#include <linux/string.h> -#include <linux/debugfs.h> +#include <linux/module.h> +#include <linux/radix-tree.h> #include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/string.h> + #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> + #include "core.h" #include "pinmux.h" diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 72fcf03eaa43..ea6f99c24aa5 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -9,6 +9,17 @@ * * Author: Linus Walleij <linus.walleij@linaro.org> */ + +#include <linux/types.h> + +struct dentry; +struct seq_file; + +struct pinctrl_dev; +struct pinctrl_gpio_range; +struct pinctrl_map; +struct pinctrl_setting; + #ifdef CONFIG_PINMUX int pinmux_check_ops(struct pinctrl_dev *pctldev); diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 9dc2d803a586..1378ddca084f 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -308,6 +308,16 @@ config PINCTRL_SDM660 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDM660 platform. +config PINCTRL_SDM670 + tristate "Qualcomm Technologies Inc SDM670 pin controller driver" + depends on OF + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDM670 platform. + config PINCTRL_SDM845 tristate "Qualcomm Technologies Inc SDM845 pin controller driver" depends on (OF || ACPI) diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 8269a1db8794..a5c40f552e5c 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index e97ce45b6d53..d5cfa91e2eff 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -8,10 +8,14 @@ #include <linux/gpio/driver.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/seq_file.h> + #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinmux.h> + #include "../pinctrl-utils.h" + #include "pinctrl-lpass-lpi.h" #define MAX_LPI_NUM_CLKS 2 diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index afbac2a6c82c..29047bb80bb8 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -6,10 +6,15 @@ #ifndef __PINCTRL_LPASS_LPI_H__ #define __PINCTRL_LPASS_LPI_H__ -#include <linux/bitops.h> -#include <linux/bitfield.h> +#include <linux/bits.h> +#include <linux/kernel.h> + #include "../core.h" +struct platform_device; + +struct pinctrl_pin_desc; + #define LPI_SLEW_RATE_CTL_REG 0xa000 #define LPI_TLMM_REG_OFFSET 0x1000 #define LPI_SLEW_RATE_MAX 0x03 diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index a2abfe987ab1..8f7d58a4efe0 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -6,31 +6,34 @@ #include <linux/delay.h> #include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> #include <linux/io.h> +#include <linux/log2.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/qcom_scm.h> +#include <linux/reboot.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/slab.h> -#include <linux/gpio/driver.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> -#include <linux/reboot.h> -#include <linux/pm.h> -#include <linux/log2.h> -#include <linux/qcom_scm.h> #include <linux/soc/qcom/irq.h> #include "../core.h" #include "../pinconf.h" -#include "pinctrl-msm.h" #include "../pinctrl-utils.h" +#include "pinctrl-msm.h" + #define MAX_NR_GPIO 300 #define MAX_NR_TILES 4 #define PS_HOLD_OFFSET 0x820 @@ -687,9 +690,8 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc, const int *reserved = pctrl->soc->reserved_gpios; u16 *tmp; - /* Driver provided reserved list overrides DT and ACPI */ + /* Remove driver-provided reserved GPIOs from valid_mask */ if (reserved) { - bitmap_fill(valid_mask, ngpios); for (i = 0; reserved[i] >= 0; i++) { if (i >= ngpios || reserved[i] >= ngpios) { dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index dd0d949f7a9e..05a1209bf9ae 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -5,6 +5,11 @@ #ifndef __PINCTRL_MSM_H__ #define __PINCTRL_MSM_H__ +#include <linux/pm.h> +#include <linux/types.h> + +struct platform_device; + struct pinctrl_pin_desc; /** diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670.c b/drivers/pinctrl/qcom/pinctrl-sdm670.c new file mode 100644 index 000000000000..b888bca7ecd7 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm670.c @@ -0,0 +1,1345 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Richard Acayan. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define WEST 0x00100000 + +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +/* + * A dummy pingroup is a pin group that cannot be assigned a function and has + * no registers to control or monitor it. + */ +#define PINGROUP_DUMMY(id) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .ctl_reg = 0, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = -1, \ + .drv_bit = -1, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sdm670_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "UFS_RESET"), + PINCTRL_PIN(151, "SDC1_RCLK"), + PINCTRL_PIN(152, "SDC1_CLK"), + PINCTRL_PIN(153, "SDC1_CMD"), + PINCTRL_PIN(154, "SDC1_DATA"), + PINCTRL_PIN(155, "SDC2_CLK"), + PINCTRL_PIN(156, "SDC2_CMD"), + PINCTRL_PIN(157, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int ufs_reset_pins[] = { 150 }; +static const unsigned int sdc1_rclk_pins[] = { 151 }; +static const unsigned int sdc1_clk_pins[] = { 152 }; +static const unsigned int sdc1_cmd_pins[] = { 153 }; +static const unsigned int sdc1_data_pins[] = { 154 }; +static const unsigned int sdc2_clk_pins[] = { 155 }; +static const unsigned int sdc2_cmd_pins[] = { 156 }; +static const unsigned int sdc2_data_pins[] = { 157 }; + +enum sdm670_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_copy_gp, + msm_mux_copy_phase, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gps_tx, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sec_mi2s, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux_wsa_clk, + msm_mux_wsa_data, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76", + "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", + "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", + "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const qup9_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const qup_l4_groups[] = { + "gpio8", "gpio35", "gpio75", "gpio105", "gpio123", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio66", +}; +static const char * const qup_l5_groups[] = { + "gpio9", "gpio36", "gpio76", "gpio106", "gpio124", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio97", "gpio98", +}; +static const char * const qup_l6_groups[] = { + "gpio10", "gpio37", "gpio77", "gpio107", "gpio125", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const tsif1_sync_groups[] = { + "gpio12", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qup1_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const jitter_bist_groups[] = { + "gpio26", "gpio35", +}; +static const char * const qup2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; +static const char * const pll_bist_groups[] = { + "gpio27", "gpio36", +}; +static const char * const agera_pll_groups[] = { + "gpio28", "gpio37", +}; +static const char * const atest_tsens_groups[] = { + "gpio29", +}; +static const char * const phase_flag_groups[] = { + "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96", + "gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142", "gpio143", +}; +static const char * const qup11_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const qup14_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const qup3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const qup6_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const qup12_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const qup10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const gp_pdm0_groups[] = { + "gpio54", "gpio95", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio54", +}; +static const char * const atest_usb13_groups[] = { + "gpio54", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio54", "gpio55", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio55", +}; +static const char * const atest_usb12_groups[] = { + "gpio55", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const pri_mi2s_groups[] = { + "gpio65", "gpio67", "gpio68", +}; +static const char * const qup8_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const wsa_clk_groups[] = { + "gpio65", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const wsa_data_groups[] = { + "gpio66", +}; +static const char * const atest_usb2_groups[] = { + "gpio67", +}; +static const char * const atest_usb23_groups[] = { + "gpio68", +}; +static const char * const ter_mi2s_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const atest_usb22_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio77", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const gp_pdm2_groups[] = { + "gpio79", +}; +static const char * const qup15_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const qup5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const copy_gp_groups[] = { + "gpio86", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qup4_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const tgu_ch3_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const tgu_ch2_groups[] = { + "gpio92", +}; +static const char * const sdc4_data_groups[] = { + "gpio92", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qup7_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const prng_rosc_groups[] = { + "gpio99", "gpio102", +}; +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; +static const char * const copy_phase_groups[] = { + "gpio103", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const qup13_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const edp_hot_groups[] = { + "gpio113", +}; +static const char * const nav_pps_groups[] = { + "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128", + "gpio129", "gpio129", "gpio143", "gpio143", +}; +static const char * const gps_tx_groups[] = { + "gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145", +}; +static const char * const atest_char_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; + +static const struct msm_function sdm670_functions[] = { + FUNCTION(gpio), + FUNCTION(adsp_ext), + FUNCTION(agera_pll), + FUNCTION(atest_char), + FUNCTION(atest_tsens), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(atest_usb10), + FUNCTION(atest_usb11), + FUNCTION(atest_usb12), + FUNCTION(atest_usb13), + FUNCTION(atest_usb2), + FUNCTION(atest_usb20), + FUNCTION(atest_usb21), + FUNCTION(atest_usb22), + FUNCTION(atest_usb23), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(copy_gp), + FUNCTION(copy_phase), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(edp_hot), + FUNCTION(edp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gps_tx), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(lpass_slimbus), + FUNCTION(m_voc), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mss_lte), + FUNCTION(nav_pps), + FUNCTION(pa_indicator), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss), + FUNCTION(qlink_enable), + FUNCTION(qlink_request), + FUNCTION(qua_mi2s), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sdc4_data), + FUNCTION(sd_write), + FUNCTION(sec_mi2s), + FUNCTION(ter_mi2s), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(tsif2_clk), + FUNCTION(tsif2_data), + FUNCTION(tsif2_en), + FUNCTION(tsif2_error), + FUNCTION(tsif2_sync), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(uim_batt), + FUNCTION(usb_phy), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), + FUNCTION(wlan1_adc0), + FUNCTION(wlan1_adc1), + FUNCTION(wlan2_adc0), + FUNCTION(wlan2_adc1), + FUNCTION(wsa_clk), + FUNCTION(wsa_data), +}; + +/* + * Each pin is individually controlled by its own group and gpios that cannot + * be requested are represented by the PINGROUP_DUMMY macro so that the group + * numbers and names correspond to their respective gpio. These dummy pins do + * not have a valid set of pinfuncs or a valid ctl_reg and should not be + * requested. + */ +static const struct msm_pingroup sdm670_groups[] = { + PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _), + PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _), + PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _), + PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _), + PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _), + PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _), + PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _), + PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _), + PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _), + PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), + PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), + PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _), + PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), + PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _), + PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _), + PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _), + PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _), + PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _), + PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _), + PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _), + PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _), + PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _), + PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _), + PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _), + PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _), + PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _), + PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _), + PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _), + PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _), + PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _), + PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _), + PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _), + PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _), + PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), + PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _), + PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), + PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _), + PINGROUP_DUMMY(58), + PINGROUP_DUMMY(59), + PINGROUP_DUMMY(60), + PINGROUP_DUMMY(61), + PINGROUP_DUMMY(62), + PINGROUP_DUMMY(63), + PINGROUP_DUMMY(64), + PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _), + PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _), + PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _), + PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _), + PINGROUP_DUMMY(69), + PINGROUP_DUMMY(70), + PINGROUP_DUMMY(71), + PINGROUP_DUMMY(72), + PINGROUP_DUMMY(73), + PINGROUP_DUMMY(74), + PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _), + PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _), + PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _), + PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), + PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _), + PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _), + PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), + PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _), + PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _), + PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _), + PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _), + PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti), + PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _), + PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _), + PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _), + PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _), + PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _), + PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _), + PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _), + PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _), + PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _), + PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _), + PINGROUP_DUMMY(104), + PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _), + PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _), + PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _), + PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _), + PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _), + PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _), + PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _), + PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _), + PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _), + PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _), + PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _), + PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _), + PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _), + PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _), + PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _), + PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), + PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), + PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _), + PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _), + PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _), + PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _), + PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _), + PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _), + PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _), + PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), + PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + UFS_RESET(ufs_reset, 0x99d000), + SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0), + SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6), + SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3), + SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0), + SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0), +}; + +static const int sdm670_reserved_gpios[] = { + 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1 +}; + +static const struct msm_pinctrl_soc_data sdm670_pinctrl = { + .pins = sdm670_pins, + .npins = ARRAY_SIZE(sdm670_pins), + .functions = sdm670_functions, + .nfunctions = ARRAY_SIZE(sdm670_functions), + .groups = sdm670_groups, + .ngroups = ARRAY_SIZE(sdm670_groups), + .ngpios = 151, + .reserved_gpios = sdm670_reserved_gpios, +}; + +static int sdm670_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm670_pinctrl); +} + +static const struct of_device_id sdm670_pinctrl_of_match[] = { + { .compatible = "qcom,sdm670-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match); + +static struct platform_driver sdm670_pinctrl_driver = { + .driver = { + .name = "sdm670-pinctrl", + .of_match_table = sdm670_pinctrl_of_match, + }, + .probe = sdm670_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm670_pinctrl_init(void) +{ + return platform_driver_register(&sdm670_pinctrl_driver); +} +arch_initcall(sdm670_pinctrl_init); + +static void __exit sdm670_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm670_pinctrl_driver); +} +module_exit(sdm670_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 8c31a8f6b7e4..89695b5a2ce7 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -9,15 +9,17 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/spmi.h> #include <linux/types.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "../core.h" diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 6937157f50b3..063177b79927 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -7,14 +7,16 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/seq_file.h> #include <linux/slab.h> #include <linux/types.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinmux.h> + #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> #include "../core.h" diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c index 1b41adda8129..b1748791a01e 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c @@ -4,18 +4,20 @@ * Copyright (c) 2013, The Linux Foundation. All rights reserved. */ -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/slab.h> -#include <linux/regmap.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> +#include <linux/module.h> #include <linux/of_device.h> #include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 49893a5133a8..30a934245c1b 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -4,18 +4,20 @@ * Copyright (c) 2013, The Linux Foundation. All rights reserved. */ -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/slab.h> -#include <linux/regmap.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> +#include <linux/module.h> #include <linux/of_device.h> #include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index a43824fd9505..a08eee092430 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -8,16 +8,19 @@ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/gpio/driver.h> -#include <linux/io.h> #include <linux/interrupt.h> +#include <linux/io.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/of_irq.h> +#include <linux/seq_file.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/spinlock.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> diff --git a/drivers/pinctrl/renesas/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c index 849d091205d4..9158c1757492 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzn1.c +++ b/drivers/pinctrl/renesas/pinctrl-rzn1.c @@ -7,16 +7,20 @@ */ #include <dt-bindings/pinctrl/rzn1-pinctrl.h> + #include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> + #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/renesas/pinctrl-rzv2m.c b/drivers/pinctrl/renesas/pinctrl-rzv2m.c index e8c18198bebd..061f16c77304 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzv2m.c +++ b/drivers/pinctrl/renesas/pinctrl-rzv2m.c @@ -15,11 +15,13 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/spinlock.h> + +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/spinlock.h> #include <dt-bindings/pinctrl/rzv2m-pinctrl.h> diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index b438d24c13b5..b74147800319 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -12,14 +12,16 @@ #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> +#include <linux/seq_file.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> -#include <linux/spinlock.h> #include "core.h" #include "../core.h" diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index bd13b5ef246d..5736761927cb 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -15,15 +15,16 @@ // but provides extensions to which platform specific implementation of the gpio // and wakeup interrupts can be hooked to. -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/property.h> -#include <linux/slab.h> #include <linux/err.h> #include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/io.h> #include <linux/irqdomain.h> #include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/seq_file.h> +#include <linux/slab.h> #include <linux/spinlock.h> #include "../core.h" diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index e0543c1ad641..18de2e70ea50 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -19,11 +19,13 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_gpio.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/slab.h> #include "pinctrl-spear.h" diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index dca7a505d413..ca9659f4e4b1 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -13,12 +13,15 @@ #include <linux/of.h> #include <linux/of_device.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + +#include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> #include "../core.h" #include "../pinmux.h" diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c index 5b544fb7f3d8..a90b770821d6 100644 --- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c @@ -15,8 +15,11 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/reset.h> +#include <linux/seq_file.h> #include <linux/spinlock.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index e485506ea599..cc9472b28404 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -13,22 +13,24 @@ #include <linux/irq.h> #include <linux/mfd/syscon.h> #include <linux/module.h> -#include <linux/of.h> #include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/of.h> #include <linux/of_irq.h> -#include <linux/pinctrl/consumer.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/property.h> #include <linux/regmap.h> #include <linux/reset.h> +#include <linux/seq_file.h> #include <linux/slab.h> +#include <linux/pinctrl/consumer.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #include "../core.h" #include "../pinconf.h" #include "../pinctrl-utils.h" diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 6c04027d0dd9..f35179eceb4e 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -10,26 +10,28 @@ * warranty of any kind, whether express or implied. */ -#include <linux/io.h> #include <linux/clk.h> +#include <linux/export.h> #include <linux/gpio/driver.h> #include <linux/interrupt.h> -#include <linux/irqdomain.h> +#include <linux/io.h> #include <linux/irqchip/chained_irq.h> -#include <linux/export.h> +#include <linux/irqdomain.h> #include <linux/of.h> -#include <linux/of_clk.h> #include <linux/of_address.h> +#include <linux/of_clk.h> #include <linux/of_device.h> #include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/slab.h> + #include <linux/pinctrl/consumer.h> #include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/regulator/consumer.h> -#include <linux/platform_device.h> -#include <linux/slab.h> #include <dt-bindings/pinctrl/sun4i-a10.h> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index 43922ab81666..7641848be4de 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -8,12 +8,15 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> #include <linux/platform_device.h> #include <linux/reset.h> +#include <linux/seq_file.h> #include <linux/slab.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> + #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include "../core.h" diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 50bd26a30ac0..1729b7ddfa94 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -15,11 +15,13 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/slab.h> + #include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/slab.h> #include "../core.h" #include "../pinctrl-utils.h" @@ -668,19 +670,6 @@ static const struct pinconf_ops tegra_pinconf_ops = { #endif }; -static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { - .name = "Tegra GPIOs", - .id = 0, - .base = 0, -}; - -static struct pinctrl_desc tegra_pinctrl_desc = { - .pctlops = &tegra_pinctrl_ops, - .pmxops = &tegra_pinmux_ops, - .confops = &tegra_pinconf_ops, - .owner = THIS_MODULE, -}; - static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) { int i = 0; @@ -831,10 +820,18 @@ int tegra_pinctrl_probe(struct platform_device *pdev, } } - tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; - tegra_pinctrl_desc.name = dev_name(&pdev->dev); - tegra_pinctrl_desc.pins = pmx->soc->pins; - tegra_pinctrl_desc.npins = pmx->soc->npins; + pmx->gpio_range.name = "Tegra GPIOs"; + pmx->gpio_range.id = 0; + pmx->gpio_range.base = 0; + pmx->gpio_range.npins = pmx->soc->ngpios; + + pmx->desc.pctlops = &tegra_pinctrl_ops; + pmx->desc.pmxops = &tegra_pinmux_ops; + pmx->desc.confops = &tegra_pinconf_ops; + pmx->desc.owner = THIS_MODULE; + pmx->desc.name = dev_name(&pdev->dev); + pmx->desc.pins = pmx->soc->pins; + pmx->desc.npins = pmx->soc->npins; for (i = 0; ; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); @@ -860,7 +857,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, return PTR_ERR(pmx->regs[i]); } - pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx); + pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx); if (IS_ERR(pmx->pctl)) { dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); return PTR_ERR(pmx->pctl); @@ -869,7 +866,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, tegra_pinctrl_clear_parked_bits(pmx); if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx)) - pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range); + pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range); platform_set_drvdata(pdev, pmx); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index f8269858eb78..6130cba7cce5 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -15,6 +15,8 @@ struct tegra_pmx { const struct tegra_pinctrl_soc_data *soc; const char **group_pins; + struct pinctrl_gpio_range gpio_range; + struct pinctrl_desc desc; int nbanks; void __iomem **regs; u32 *backup_regs; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c index f6c5d5e6dbb6..277973c88434 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -16,6 +16,7 @@ #include <linux/init.h> #include <linux/of.h> +#include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> @@ -23,7 +24,7 @@ #include "pinctrl-tegra.h" /* Define unique ID for each pins */ -enum pin_id { +enum { TEGRA_PIN_DAP6_SCLK_PA0, TEGRA_PIN_DAP6_DOUT_PA1, TEGRA_PIN_DAP6_DIN_PA2, @@ -189,6 +190,31 @@ enum pin_id { TEGRA_PIN_SPI1_MOSI_PZ5, TEGRA_PIN_SPI1_CS0_PZ6, TEGRA_PIN_SPI1_CS1_PZ7, + TEGRA_PIN_UFS0_REF_CLK_PFF0, + TEGRA_PIN_UFS0_RST_PFF1, + TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, + TEGRA_PIN_PEX_L5_RST_N_PGG1, + TEGRA_PIN_DIRECTDC_COMP, + TEGRA_PIN_SDMMC4_CLK, + TEGRA_PIN_SDMMC4_CMD, + TEGRA_PIN_SDMMC4_DQS, + TEGRA_PIN_SDMMC4_DAT7, + TEGRA_PIN_SDMMC4_DAT6, + TEGRA_PIN_SDMMC4_DAT5, + TEGRA_PIN_SDMMC4_DAT4, + TEGRA_PIN_SDMMC4_DAT3, + TEGRA_PIN_SDMMC4_DAT2, + TEGRA_PIN_SDMMC4_DAT1, + TEGRA_PIN_SDMMC4_DAT0, + TEGRA_PIN_SDMMC1_COMP, + TEGRA_PIN_SDMMC1_HV_TRIM, + TEGRA_PIN_SDMMC3_COMP, + TEGRA_PIN_SDMMC3_HV_TRIM, + TEGRA_PIN_EQOS_COMP, + TEGRA_PIN_QSPI_COMP, +}; + +enum { TEGRA_PIN_CAN1_DOUT_PAA0, TEGRA_PIN_CAN1_DIN_PAA1, TEGRA_PIN_CAN0_DOUT_PAA2, @@ -219,28 +245,6 @@ enum pin_id { TEGRA_PIN_POWER_ON_PEE4, TEGRA_PIN_PWR_I2C_SCL_PEE5, TEGRA_PIN_PWR_I2C_SDA_PEE6, - TEGRA_PIN_UFS0_REF_CLK_PFF0, - TEGRA_PIN_UFS0_RST_PFF1, - TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, - TEGRA_PIN_PEX_L5_RST_N_PGG1, - TEGRA_PIN_DIRECTDC_COMP, - TEGRA_PIN_SDMMC4_CLK, - TEGRA_PIN_SDMMC4_CMD, - TEGRA_PIN_SDMMC4_DQS, - TEGRA_PIN_SDMMC4_DAT7, - TEGRA_PIN_SDMMC4_DAT6, - TEGRA_PIN_SDMMC4_DAT5, - TEGRA_PIN_SDMMC4_DAT4, - TEGRA_PIN_SDMMC4_DAT3, - TEGRA_PIN_SDMMC4_DAT2, - TEGRA_PIN_SDMMC4_DAT1, - TEGRA_PIN_SDMMC4_DAT0, - TEGRA_PIN_SDMMC1_COMP, - TEGRA_PIN_SDMMC1_HV_TRIM, - TEGRA_PIN_SDMMC3_COMP, - TEGRA_PIN_SDMMC3_HV_TRIM, - TEGRA_PIN_EQOS_COMP, - TEGRA_PIN_QSPI_COMP, TEGRA_PIN_SYS_RESET_N, TEGRA_PIN_SHUTDOWN_N, TEGRA_PIN_PMU_INT_N, @@ -415,36 +419,6 @@ static const struct pinctrl_pin_desc tegra194_pins[] = { PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"), PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"), PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"), - PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"), - PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"), - PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"), - PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"), - PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"), - PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"), - PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"), - PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"), - PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"), - PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"), - PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"), - PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"), - PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"), - PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"), - PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"), - PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"), - PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"), - PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"), - PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"), - PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"), - PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"), - PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"), - PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"), - PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"), - PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"), - PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"), - PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"), - PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"), - PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"), - PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"), PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"), PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"), PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"), @@ -467,11 +441,6 @@ static const struct pinctrl_pin_desc tegra194_pins[] = { PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"), PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"), PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"), - PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"), - PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"), - PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"), - PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"), - PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), }; static const unsigned int dap6_sclk_pa0_pins[] = { @@ -1379,29 +1348,7 @@ static struct tegra_function tegra194_functions[] = { .drvtype_bit = 13, \ .lpdr_bit = e_lpdr, \ -#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 1) -#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 1) +/* main drive pin groups */ #define drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0) @@ -1509,17 +1456,6 @@ static struct tegra_function tegra194_functions[] = { #define drive_sdmmc3_dat0_po2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0) #define drive_sdmmc3_cmd_po1 DRV_PINGROUP_ENTRY_Y(0xa02c, -1, -1, -1, -1, 28, 2, 30, 2, 0) #define drive_sdmmc3_clk_po0 DRV_PINGROUP_ENTRY_Y(0xa034, -1, -1, -1, -1, 28, 2, 30, 2, 0) -#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1) -#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1) #define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xD004, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xD00c, 12, 5, 20, 5, -1, -1, -1, -1, 0) #define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xD014, 12, 5, 20, 5, -1, -1, -1, -1, 0) @@ -1600,6 +1536,42 @@ static struct tegra_function tegra194_functions[] = { #define drive_directdc1_in_pv1 DRV_PINGROUP_ENTRY_N(no_entry) #define drive_directdc1_clk_pv0 DRV_PINGROUP_ENTRY_N(no_entry) +/* AON drive pin groups */ +#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0) +#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0) +#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0) + #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \ gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail) \ { \ @@ -1622,30 +1594,6 @@ static struct tegra_function tegra194_functions[] = { } static const struct tegra_pingroup tegra194_groups[] = { - - PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), - PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), - PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), PINGROUP(soc_gpio33_pt0, RSVD0, SPDIF, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"), PINGROUP(soc_gpio32_ps7, RSVD0, SPDIF, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"), PINGROUP(soc_gpio31_ps6, RSVD0, SDMMC1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"), @@ -1805,17 +1753,6 @@ static const struct tegra_pingroup tegra194_groups[] = { PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"), PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"), PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"), - PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 1, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 1, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), - PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"), PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"), PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"), @@ -1857,13 +1794,104 @@ static const struct tegra_pinctrl_soc_data tegra194_pinctrl = { .sfsel_in_mux = true, }; +static const struct pinctrl_pin_desc tegra194_aon_pins[] = { + PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"), + PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"), + PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"), + PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"), + PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"), + PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"), + PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"), + PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"), + PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"), + PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"), + PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"), + PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"), + PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"), + PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"), + PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"), + PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"), + PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"), + PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"), + PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"), + PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"), + PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"), + PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"), + PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"), + PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"), + PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"), + PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"), + PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"), + PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"), + PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"), + PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"), + PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"), + PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"), +}; + +static const struct tegra_pingroup tegra194_aon_groups[] = { + PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"), + PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"), + PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), + PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"), +}; + +static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = { + .pins = tegra194_aon_pins, + .npins = ARRAY_SIZE(tegra194_aon_pins), + .functions = tegra194_functions, + .nfunctions = ARRAY_SIZE(tegra194_functions), + .groups = tegra194_aon_groups, + .ngroups = ARRAY_SIZE(tegra194_aon_groups), + .hsm_in_mux = true, + .schmitt_in_mux = true, + .drvtype_in_mux = true, + .sfsel_in_mux = true, +}; + static int tegra194_pinctrl_probe(struct platform_device *pdev) { - return tegra_pinctrl_probe(pdev, &tegra194_pinctrl); + const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev); + + return tegra_pinctrl_probe(pdev, soc); } static const struct of_device_id tegra194_pinctrl_of_match[] = { - { .compatible = "nvidia,tegra194-pinmux", }, + { .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl }, + { .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon }, { }, }; diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 4e2382778d38..53abddaebce1 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -15,12 +15,14 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> -#include <linux/pinctrl/pinconf.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinctrl.h> #include <linux/regmap.h> +#include <linux/seq_file.h> #include <linux/slab.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinctrl.h> + #include "../core.h" #include "../devicetree.h" diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index ade348b49b31..18d3a4f69e63 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -6,12 +6,14 @@ #include <linux/list.h> #include <linux/mfd/syscon.h> #include <linux/of.h> -#include <linux/pinctrl/pinconf.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/seq_file.h> + #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> -#include <linux/platform_device.h> -#include <linux/regmap.h> #include "../core.h" #include "../pinctrl-utils.h" diff --git a/include/dt-bindings/pinctrl/mt6795-pinfunc.h b/include/dt-bindings/pinctrl/mt6795-pinfunc.h index bd1c5a9fad06..dfd3f6f13e0d 100644 --- a/include/dt-bindings/pinctrl/mt6795-pinfunc.h +++ b/include/dt-bindings/pinctrl/mt6795-pinfunc.h @@ -4,8 +4,8 @@ * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> */ -#ifndef __DTS_MT8173_PINFUNC_H -#define __DTS_MT8173_PINFUNC_H +#ifndef __DTS_MT6795_PINFUNC_H +#define __DTS_MT6795_PINFUNC_H #include <dt-bindings/pinctrl/mt65xx.h> diff --git a/include/linux/gpio.h b/include/linux/gpio.h index a370387fa406..346f60bbab30 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -98,9 +98,9 @@ int devm_gpio_request_one(struct device *dev, unsigned gpio, #else /* ! CONFIG_GPIOLIB */ +#include <linux/bug.h> #include <linux/kernel.h> #include <linux/types.h> -#include <linux/bug.h> struct device; struct gpio_chip; diff --git a/include/linux/gpio/aspeed.h b/include/linux/gpio/aspeed.h index 1bfb3cdc86d0..9a547e66c8c4 100644 --- a/include/linux/gpio/aspeed.h +++ b/include/linux/gpio/aspeed.h @@ -1,6 +1,10 @@ #ifndef __GPIO_ASPEED_H #define __GPIO_ASPEED_H +#include <linux/types.h> + +struct gpio_desc; + struct aspeed_gpio_copro_ops { int (*request_access)(void *data); int (*release_access)(void *data); diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 6aeea1071b1b..2a44600b01f7 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -7,8 +7,8 @@ #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h> #include <linux/lockdep.h> -#include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> #include <linux/property.h> #include <linux/types.h> diff --git a/include/linux/gpio/gpio-reg.h b/include/linux/gpio/gpio-reg.h index 39b888c40b39..3913b6660ed1 100644 --- a/include/linux/gpio/gpio-reg.h +++ b/include/linux/gpio/gpio-reg.h @@ -2,9 +2,13 @@ #ifndef GPIO_REG_H #define GPIO_REG_H +#include <linux/types.h> + struct device; struct irq_domain; +struct gpio_chip; + struct gpio_chip *gpio_reg_init(struct device *dev, void __iomem *reg, int base, int num, const char *label, u32 direction, u32 def_out, const char *const *names, struct irq_domain *irqdom, const int *irqs); diff --git a/include/linux/gpio/machine.h b/include/linux/gpio/machine.h index 0b619eb7ae83..44e5f162973e 100644 --- a/include/linux/gpio/machine.h +++ b/include/linux/gpio/machine.h @@ -3,7 +3,6 @@ #define __LINUX_GPIO_MACHINE_H #include <linux/types.h> -#include <linux/list.h> enum gpio_lookup_flags { GPIO_ACTIVE_HIGH = (0 << 0), diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 019fecd75d0c..4729d54e8995 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -12,14 +12,15 @@ #define __LINUX_PINCTRL_CONSUMER_H #include <linux/err.h> -#include <linux/list.h> -#include <linux/seq_file.h> +#include <linux/types.h> + #include <linux/pinctrl/pinctrl-state.h> +struct device; + /* This struct is private to the core and should be regarded as a cookie */ struct pinctrl; struct pinctrl_state; -struct device; #ifdef CONFIG_PINCTRL @@ -33,9 +34,8 @@ extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config); extern struct pinctrl * __must_check pinctrl_get(struct device *dev); extern void pinctrl_put(struct pinctrl *p); -extern struct pinctrl_state * __must_check pinctrl_lookup_state( - struct pinctrl *p, - const char *name); +extern struct pinctrl_state * __must_check pinctrl_lookup_state(struct pinctrl *p, + const char *name); extern int pinctrl_select_state(struct pinctrl *p, struct pinctrl_state *s); extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev); @@ -101,9 +101,8 @@ static inline void pinctrl_put(struct pinctrl *p) { } -static inline struct pinctrl_state * __must_check pinctrl_lookup_state( - struct pinctrl *p, - const char *name) +static inline struct pinctrl_state * __must_check pinctrl_lookup_state(struct pinctrl *p, + const char *name) { return NULL; } @@ -145,8 +144,8 @@ static inline int pinctrl_pm_select_idle_state(struct device *dev) #endif /* CONFIG_PINCTRL */ -static inline struct pinctrl * __must_check pinctrl_get_select( - struct device *dev, const char *name) +static inline struct pinctrl * __must_check pinctrl_get_select(struct device *dev, + const char *name) { struct pinctrl *p; struct pinctrl_state *s; @@ -171,14 +170,13 @@ static inline struct pinctrl * __must_check pinctrl_get_select( return p; } -static inline struct pinctrl * __must_check pinctrl_get_select_default( - struct device *dev) +static inline struct pinctrl * __must_check pinctrl_get_select_default(struct device *dev) { return pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); } -static inline struct pinctrl * __must_check devm_pinctrl_get_select( - struct device *dev, const char *name) +static inline struct pinctrl * __must_check devm_pinctrl_get_select(struct device *dev, + const char *name) { struct pinctrl *p; struct pinctrl_state *s; @@ -203,8 +201,7 @@ static inline struct pinctrl * __must_check devm_pinctrl_get_select( return p; } -static inline struct pinctrl * __must_check devm_pinctrl_get_select_default( - struct device *dev) +static inline struct pinctrl * __must_check devm_pinctrl_get_select_default(struct device *dev) { return devm_pinctrl_get_select(dev, PINCTRL_STATE_DEFAULT); } diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h index a48ff69acddd..9e8b559e1253 100644 --- a/include/linux/pinctrl/devinfo.h +++ b/include/linux/pinctrl/devinfo.h @@ -14,11 +14,15 @@ #ifndef PINCTRL_DEVINFO_H #define PINCTRL_DEVINFO_H +struct device; + #ifdef CONFIG_PINCTRL /* The device core acts as a consumer toward pinctrl */ #include <linux/pinctrl/consumer.h> +struct pinctrl; + /** * struct dev_pin_info - pin state container for devices * @p: pinctrl handle for the containing device @@ -42,8 +46,6 @@ extern int pinctrl_init_done(struct device *dev); #else -struct device; - /* Stubs if we're not using pinctrl */ static inline int pinctrl_bind_pins(struct device *dev) diff --git a/include/linux/pinctrl/machine.h b/include/linux/pinctrl/machine.h index e987dc9fd2af..0639b36f43c5 100644 --- a/include/linux/pinctrl/machine.h +++ b/include/linux/pinctrl/machine.h @@ -11,7 +11,7 @@ #ifndef __LINUX_PINCTRL_MACHINE_H #define __LINUX_PINCTRL_MACHINE_H -#include <linux/bug.h> +#include <linux/kernel.h> /* ARRAY_SIZE() */ #include <linux/pinctrl/pinctrl-state.h> @@ -149,16 +149,18 @@ struct pinctrl_map { #define PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(dev, grp, cfgs) \ PIN_MAP_CONFIGS_GROUP(dev, PINCTRL_STATE_DEFAULT, dev, grp, cfgs) +struct pinctrl_map; + #ifdef CONFIG_PINCTRL extern int pinctrl_register_mappings(const struct pinctrl_map *map, - unsigned num_maps); + unsigned num_maps); extern void pinctrl_unregister_mappings(const struct pinctrl_map *map); extern void pinctrl_provide_dummies(void); #else static inline int pinctrl_register_mappings(const struct pinctrl_map *map, - unsigned num_maps) + unsigned num_maps) { return 0; } diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 2422211d6a5a..940fc4e9e17c 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -11,9 +11,12 @@ #ifndef __LINUX_PINCTRL_PINCONF_GENERIC_H #define __LINUX_PINCTRL_PINCONF_GENERIC_H -#include <linux/device.h> +#include <linux/types.h> + #include <linux/pinctrl/machine.h> +struct device_node; + struct pinctrl_dev; struct pinctrl_map; @@ -196,25 +199,25 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps); -static inline int pinconf_generic_dt_node_to_map_group( - struct pinctrl_dev *pctldev, struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) +static inline int pinconf_generic_dt_node_to_map_group(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) { return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, PIN_MAP_TYPE_CONFIGS_GROUP); } -static inline int pinconf_generic_dt_node_to_map_pin( - struct pinctrl_dev *pctldev, struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) +static inline int pinconf_generic_dt_node_to_map_pin(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) { return pinconf_generic_dt_node_to_map(pctldev, np_config, map, num_maps, PIN_MAP_TYPE_CONFIGS_PIN); } -static inline int pinconf_generic_dt_node_to_map_all( - struct pinctrl_dev *pctldev, struct device_node *np_config, - struct pinctrl_map **map, unsigned *num_maps) +static inline int pinconf_generic_dt_node_to_map_all(struct pinctrl_dev *pctldev, + struct device_node *np_config, struct pinctrl_map **map, + unsigned *num_maps) { /* * passing the type as PIN_MAP_TYPE_INVALID causes the underlying parser diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h index 487117ccb1bc..a0d39b303431 100644 --- a/include/linux/pinctrl/pinctrl.h +++ b/include/linux/pinctrl/pinctrl.h @@ -11,20 +11,20 @@ #ifndef __LINUX_PINCTRL_PINCTRL_H #define __LINUX_PINCTRL_PINCTRL_H -#include <linux/radix-tree.h> -#include <linux/list.h> -#include <linux/seq_file.h> -#include <linux/pinctrl/pinctrl-state.h> -#include <linux/pinctrl/devinfo.h> +#include <linux/types.h> struct device; +struct device_node; +struct gpio_chip; +struct module; +struct seq_file; + +struct pin_config_item; +struct pinconf_generic_params; +struct pinconf_ops; struct pinctrl_dev; struct pinctrl_map; struct pinmux_ops; -struct pinconf_ops; -struct pin_config_item; -struct gpio_chip; -struct device_node; /** * struct pingroup - provides information on pingroup @@ -40,7 +40,7 @@ struct pingroup { /* Convenience macro to define a single named or anonymous pingroup */ #define PINCTRL_PINGROUP(_name, _pins, _npins) \ -(struct pingroup){ \ +(struct pingroup) { \ .name = _name, \ .pins = _pins, \ .npins = _npins, \ diff --git a/include/linux/pinctrl/pinmux.h b/include/linux/pinctrl/pinmux.h index 9a647fa5c8f1..a7e370965c53 100644 --- a/include/linux/pinctrl/pinmux.h +++ b/include/linux/pinctrl/pinmux.h @@ -11,11 +11,10 @@ #ifndef __LINUX_PINCTRL_PINMUX_H #define __LINUX_PINCTRL_PINMUX_H -#include <linux/list.h> -#include <linux/seq_file.h> -#include <linux/pinctrl/pinctrl.h> +#include <linux/types.h> struct pinctrl_dev; +struct pinctrl_gpio_range; /** * struct pinmux_ops - pinmux operations, to be implemented by pin controller |