diff options
| -rw-r--r-- | Documentation/devicetree/bindings/spi/cadence-quadspi.txt (renamed from Documentation/devicetree/bindings/mtd/cadence-quadspi.txt) | 1 | ||||
| -rw-r--r-- | drivers/spi/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/spi/spi-cadence-quadspi.c | 24 | ||||
| -rw-r--r-- | drivers/spi/spi-hisi-sfc-v3xx.c | 8 | ||||
| -rw-r--r-- | drivers/spi/spi-qcom-qspi.c | 3 | ||||
| -rw-r--r-- | drivers/spi/spi-stm32.c | 28 |
6 files changed, 29 insertions, 37 deletions
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt index 945be7d5b236..8ace832a2d80 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt @@ -5,6 +5,7 @@ Required properties: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index aa0c61c0a890..7d3af8120da4 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -203,7 +203,7 @@ config SPI_CADENCE config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || COMPILE_TEST) + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST) help Enable support for the Cadence Quad SPI Flash controller. diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index af13c0025bf5..b7ecbc8c1caa 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -76,6 +76,7 @@ struct cqspi_st { bool is_decoded_cs; u32 fifo_depth; u32 fifo_width; + u32 num_chipselect; bool rclk_en; u32 trigger_address; u32 wr_delay; @@ -1353,6 +1354,9 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi) return -ENXIO; } + if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) + cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; + cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); return 0; @@ -1384,10 +1388,12 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) writel(cqspi->fifo_depth * cqspi->fifo_width / 8, cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); - /* Enable Direct Access Controller */ - reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); - reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; - writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + /* Disable direct access controller */ + if (!cqspi->use_direct_mode) { + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL; + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + } cqspi_controller_enable(cqspi, 1); } @@ -1587,6 +1593,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->current_cs = -1; cqspi->sclk = 0; + master->num_chipselect = cqspi->num_chipselect; + ret = cqspi_setup_flash(cqspi); if (ret) { dev_err(dev, "failed to setup flash parameters %d\n", ret); @@ -1675,6 +1683,10 @@ static const struct cqspi_driver_platdata am654_ospi = { .quirks = CQSPI_NEEDS_WR_DELAY, }; +static const struct cqspi_driver_platdata intel_lgm_qspi = { + .quirks = CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1688,6 +1700,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "ti,am654-ospi", .data = &am654_ospi, }, + { + .compatible = "intel,lgm-qspi", + .data = &intel_lgm_qspi, + }, { /* end of table */ } }; diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c index 4650b483a33d..832b80e7ef67 100644 --- a/drivers/spi/spi-hisi-sfc-v3xx.c +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -465,14 +465,10 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev) version = readl(host->regbase + HISI_SFC_V3XX_VERSION); - switch (version) { - case 0x351: + if (version >= 0x351) host->max_cmd_dword = 64; - break; - default: + else host->max_cmd_dword = 16; - break; - } ret = devm_spi_register_controller(dev, ctlr); if (ret) diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index 8863be370884..1dbcc410cd35 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -511,8 +511,7 @@ static int qcom_qspi_probe(struct platform_device *pdev) ret = platform_get_irq(pdev, 0); if (ret < 0) return ret; - ret = devm_request_irq(dev, ret, qcom_qspi_irq, - IRQF_TRIGGER_HIGH, dev_name(dev), ctrl); + ret = devm_request_irq(dev, ret, qcom_qspi_irq, 0, dev_name(dev), ctrl); if (ret) { dev_err(dev, "Failed to request irq %d\n", ret); return ret; diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index be0fb169d7a7..db3e305d9ec4 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -473,34 +473,14 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, */ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) { - u32 fthlv, half_fifo, packet; + u32 packet, bpw; /* data packet should not exceed 1/2 of fifo space */ - half_fifo = (spi->fifo_size / 2); - - /* data_packet should not exceed transfer length */ - if (half_fifo > xfer_len) - packet = xfer_len; - else - packet = half_fifo; - - if (spi->cur_bpw <= 8) - fthlv = packet; - else if (spi->cur_bpw <= 16) - fthlv = packet / 2; - else - fthlv = packet / 4; + packet = clamp(xfer_len, 1U, spi->fifo_size / 2); /* align packet size with data registers access */ - if (spi->cur_bpw > 8) - fthlv += (fthlv % 2) ? 1 : 0; - else - fthlv += (fthlv % 4) ? (4 - (fthlv % 4)) : 0; - - if (!fthlv) - fthlv = 1; - - return fthlv; + bpw = DIV_ROUND_UP(spi->cur_bpw, 8); + return DIV_ROUND_UP(packet, bpw); } /** |