diff options
| -rw-r--r-- | Documentation/arch/arm64/silicon-errata.rst | 2 | ||||
| -rw-r--r-- | arch/arm64/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 1 | 
3 files changed, 4 insertions, 0 deletions
| diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index b42fea07c5ce..b6dacd012539 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -198,6 +198,8 @@ stable kernels.  +----------------+-----------------+-----------------+-----------------------------+  | ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |  +----------------+-----------------+-----------------+-----------------------------+ +| ARM            | Neoverse-V3AE   | #3312417        | ARM64_ERRATUM_3194386       | ++----------------+-----------------+-----------------+-----------------------------+  | ARM            | MMU-500         | #841119,826419  | N/A                         |  +----------------+-----------------+-----------------+-----------------------------+  | ARM            | MMU-600         | #1076982,1209401| N/A                         | diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 7887d18cce3e..40ae4dd961b1 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1111,6 +1111,7 @@ config ARM64_ERRATUM_3194386  	  * ARM Neoverse-V1 erratum 3324341  	  * ARM Neoverse V2 erratum 3324336  	  * ARM Neoverse-V3 erratum 3312417 +	  * ARM Neoverse-V3AE erratum 3312417  	  On affected cores "MSR SSBS, #0" instructions may not affect  	  subsequent speculative instructions, which may permit unexepected diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index a78f247029ae..3f675ae57d09 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -455,6 +455,7 @@ static const struct midr_range erratum_spec_ssbs_list[] = {  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),  	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3), +	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),  	{}  };  #endif | 
