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authorMiquel Raynal <miquel.raynal@bootlin.com>2025-04-03 11:19:18 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2025-06-27 11:13:42 +0100
commit2667e28cf5c59847bf81628d13ad5f41301e3a55 (patch)
treef945c98686b32fc5c0a8bf5ff7c7b27a43c960eb /net/lapb/lapb_out.c
parent8a39fa1753796a1955bf73bfff7dd09131b6a379 (diff)
mtd: spinand: Use more specific naming for the (dual output) read from cache ops
[ Upstream commit 684f7105e8534f6500de389c089ba204cb1c8058 ] SPI operations have been initially described through macros implicitly implying the use of a single SPI SDR bus. Macros for supporting dual and quad I/O transfers have been added on top, generally inspired by vendor naming, followed by DTR operations. Soon we might see octal and even octal DTR operations as well (including the opcode byte). Let's clarify what the macro really mean by describing the expected bus topology in the (dual output) read from cache macro names. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Stable-dep-of: dba90f5a79c1 ("mtd: spinand: winbond: Prevent unsupported frequencies on dual/quad I/O variants") Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'net/lapb/lapb_out.c')
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