diff options
| author | Yang Yingliang <yangyingliang@huawei.com> | 2023-04-24 10:19:03 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2023-04-26 13:51:56 +0200 |
| commit | 71e7ed6e3aa9e7c745ed3d7ccf634a1f9f094497 (patch) | |
| tree | d70a656a882a630f5dde6957e993e0baaaabacd5 | |
| parent | 48c5fd373345f5103db960a651f8657733aaf027 (diff) | |
soc: sifive: l2_cache: fix missing free_irq() in error path in sifive_l2_init()
commit 756344e7cb1afbb87da8705c20384dddd0dea233 upstream.
Add missing free_irq() before return error from sifive_l2_init().
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
[conor: ccache -> l2_cache]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/soc/sifive/sifive_l2_cache.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index 483aeaf0d405..1248127009f6 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -221,7 +221,7 @@ static int __init sifive_l2_init(void) rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); if (rc) { pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); - goto err_unmap; + goto err_free_irq; } } @@ -235,6 +235,9 @@ static int __init sifive_l2_init(void) #endif return 0; +err_free_irq: + while (--i >= 0) + free_irq(g_irq[i], NULL); err_unmap: iounmap(l2_base); return rc; |