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| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 16:22:26 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 16:22:26 +0300 |
| commit | c10b9b13f7471b08273effc8cd7e51b119df9348 (patch) | |
| tree | ca058c3446a247a5bccea211bd84a9c0130e1388 /sysdeps/x86_64/fpu/svml_d_pow_data.h | |
| parent | 1663be053d50c06bb0f971c87d41a7b83f96fe15 (diff) | |
Vector pow for x86_64 and tests.
Here is implementation of vectorized pow containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* bits/libm-simd-decl-stubs.h: Added stubs for pow.
* math/bits/mathcalls.h: Added pow declaration with __MATHCALL_VEC.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New versions added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for pow.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/svml_d_wrapper_impl.h: Added 2 argument wrappers.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow2_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow4_core_avx2.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow2_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow4_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow8_core.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow_data.S: New file.
* sysdeps/x86_64/fpu/svml_d_pow_data.h: New file.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Added vector pow test.
* sysdeps/x86_64/fpu/test-double-vlen2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector pow.
Diffstat (limited to 'sysdeps/x86_64/fpu/svml_d_pow_data.h')
| -rw-r--r-- | sysdeps/x86_64/fpu/svml_d_pow_data.h | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/sysdeps/x86_64/fpu/svml_d_pow_data.h b/sysdeps/x86_64/fpu/svml_d_pow_data.h new file mode 100644 index 0000000000..a1b9f9bc46 --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_d_pow_data.h @@ -0,0 +1,104 @@ +/* Offsets for data table for function pow. + Copyright (C) 2014-2015 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + <http://www.gnu.org/licenses/>. */ + +#ifndef D_POW_DATA_H +#define D_POW_DATA_H + +#define _hsw_log2_table 0 +#define _hsw_dTe 8256 +#define _hsw_dMantMask 10304 +#define _hsw_dOne 10368 +#define _hsw_dCvtMask 10432 +#define _hsw_dMinNorm 10496 +#define _hsw_dMaxNorm 10560 +#define _hsw_lRndBit 10624 +#define _hsw_lRndMask 10688 +#define _hsw_dc6 10752 +#define _hsw_dc5 10816 +#define _hsw_dc4 10880 +#define _hsw_dc3 10944 +#define _hsw_dc1 11008 +#define _hsw_dc1h 11072 +#define _hsw_dc2 11136 +#define _hsw_dAbsMask 11200 +#define _hsw_dDomainRange 11264 +#define _hsw_dShifter 11328 +#define _hsw_dIndexMask 11392 +#define _hsw_dce4 11456 +#define _hsw_dce3 11520 +#define _hsw_dce2 11584 +#define _hsw_dce1 11648 +#define _rcp_t1 11712 +#define _log2_t1 19968 +#define _exp2_tbl 36416 +#define _clv_1 38464 +#define _clv_2 38528 +#define _clv_3 38592 +#define _clv_4 38656 +#define _clv_5 38720 +#define _clv_6 38784 +#define _clv_7 38848 +#define _cev_1 38912 +#define _cev_2 38976 +#define _cev_3 39040 +#define _cev_4 39104 +#define _cev_5 39168 +#define _iMantissaMask 39232 +#define _i3fe7fe0000000000 39296 +#define _dbOne 39360 +#define _iffffffff00000000 39424 +#define _db2p20_2p19 39488 +#define _iHighMask 39552 +#define _LHN 39616 +#define _ifff0000000000000 39680 +#define _db2p45_2p44 39744 +#define _NEG_INF 39808 +#define _NEG_ZERO 39872 +#define _d2pow52 39936 +#define _d1div2pow111 40000 +#define _HIDELTA 40064 +#define _LORANGE 40128 +#define _ABSMASK 40192 +#define _INF 40256 +#define _DOMAINRANGE 40320 +#define _iIndexMask 40384 +#define _iIndexAdd 40448 +#define _i3fe7fe00 40512 +#define _i2p20_2p19 40576 +#define _iOne 40640 +#define _jIndexMask 40704 + +.macro double_vector offset value +.if .-__svml_dpow_data != \offset +.err +.endif +.rept 8 +.quad \value +.endr +.endm + +.macro float_vector offset value +.if .-__svml_dpow_data != \offset +.err +.endif +.rept 16 +.long \value +.endr +.endm + +#endif |