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authorJakub Jelinek <jakub@redhat.com>2007-10-10 21:00:50 +0000
committerJakub Jelinek <jakub@redhat.com>2007-10-10 21:00:50 +0000
commitfc2a4f5f837f259c239fbd15911f80ca8c6907e3 (patch)
tree2be478cfcb93051f657027d6fafd96778aa49317 /sysdeps/x86_64/cacheinfo.c
parent75cb5a0d471729d28a59b693441e2d527c9e962e (diff)
Updated to fedora-glibc-20071010T2047cvs/fedora-glibc-2_6_90-18
Diffstat (limited to 'sysdeps/x86_64/cacheinfo.c')
-rw-r--r--sysdeps/x86_64/cacheinfo.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index 5b92bd5849..12102fea81 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -456,6 +456,13 @@ init_cacheinfo (void)
asm volatile ("cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "0" (4), "2" (i++));
+
+ /* There seems to be a bug in at least some Pentium Ds
+ which sometimes fail to iterate all cache parameters.
+ Do not loop indefinitely here, stop in this case and
+ assume there is no such information. */
+ if ((eax & 0x1f) == 0)
+ goto intel_bug_no_cache_info;
}
while (((eax >> 5) & 0x7) != level);
@@ -463,6 +470,7 @@ init_cacheinfo (void)
}
else
{
+ intel_bug_no_cache_info:
/* Assume that all logical threads share the highest cache level. */
asm volatile ("cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)