diff options
| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 16:10:51 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2015-06-17 16:10:51 +0300 |
| commit | 1663be053d50c06bb0f971c87d41a7b83f96fe15 (patch) | |
| tree | 4bfbbfac7a83c1e52b2a7ab23dd9677f5cab4267 /sysdeps/unix/sysv/linux/x86_64/libmvec.abilist | |
| parent | 9c02f663f6b387b3905b629ffe584c9abf2030dc (diff) | |
Vector expf for x86_64 and tests.
Here is implementation of vectorized expf containing SSE, AVX,
AVX2 and AVX512 versions according to Vector ABI
<https://groups.google.com/forum/#!topic/x86-64-abi/LmppCfN1rZ4>.
* sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added.
* sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm
redirections for expf.
* sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files.
* sysdeps/x86_64/fpu/Versions: New versions added.
* sysdeps/x86_64/fpu/libm-test-ulps: Regenerated.
* sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added
build of SSE, AVX2 and AVX512 IFUNC versions.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf4_core_sse4.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core.S: New file.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf8_core_avx2.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf16_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf4_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf8_core.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf_data.S: New file.
* sysdeps/x86_64/fpu/svml_s_expf_data.h: New file.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Vector expf tests.
* sysdeps/x86_64/fpu/test-float-vlen16.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise.
* NEWS: Mention addition of x86_64 vector expf.
Diffstat (limited to 'sysdeps/unix/sysv/linux/x86_64/libmvec.abilist')
| -rw-r--r-- | sysdeps/unix/sysv/linux/x86_64/libmvec.abilist | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist index ff9431fa10..9652215777 100644 --- a/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist +++ b/sysdeps/unix/sysv/linux/x86_64/libmvec.abilist @@ -5,6 +5,7 @@ GLIBC_2.22 _ZGVbN2v_log F _ZGVbN2v_sin F _ZGVbN4v_cosf F + _ZGVbN4v_expf F _ZGVbN4v_logf F _ZGVbN4v_sinf F _ZGVcN4v_cos F @@ -12,6 +13,7 @@ GLIBC_2.22 _ZGVcN4v_log F _ZGVcN4v_sin F _ZGVcN8v_cosf F + _ZGVcN8v_expf F _ZGVcN8v_logf F _ZGVcN8v_sinf F _ZGVdN4v_cos F @@ -19,9 +21,11 @@ GLIBC_2.22 _ZGVdN4v_log F _ZGVdN4v_sin F _ZGVdN8v_cosf F + _ZGVdN8v_expf F _ZGVdN8v_logf F _ZGVdN8v_sinf F _ZGVeN16v_cosf F + _ZGVeN16v_expf F _ZGVeN16v_logf F _ZGVeN16v_sinf F _ZGVeN8v_cos F |