diff options
author | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2016-08-20 19:50:45 +0200 |
---|---|---|
committer | Samuel Thibault <samuel.thibault@ens-lyon.org> | 2016-08-20 19:50:45 +0200 |
commit | 4dd9e35bfd35d3138bc44169baba098005bad51e (patch) | |
tree | a4939c43a9c3fe00eb27f023e14acc5e1fe8808c /sysdeps/sparc/sparc32/bits/atomic.h | |
parent | bd42a4599d1b6f77bcfe1e4f67b7cbd9e1cb2dfd (diff) | |
parent | f76453c31593957fec1a99b986bfa5506618b79c (diff) |
Merge commit 'refs/top-bases/t/bigmem' into t/bigmem
Diffstat (limited to 'sysdeps/sparc/sparc32/bits/atomic.h')
-rw-r--r-- | sysdeps/sparc/sparc32/bits/atomic.h | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/sysdeps/sparc/sparc32/bits/atomic.h b/sysdeps/sparc/sparc32/bits/atomic.h index 39c2b37655..4242ba831a 100644 --- a/sysdeps/sparc/sparc32/bits/atomic.h +++ b/sysdeps/sparc/sparc32/bits/atomic.h @@ -1,5 +1,5 @@ /* Atomic operations. sparc32 version. - Copyright (C) 2003-2014 Free Software Foundation, Inc. + Copyright (C) 2003-2015 Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Jakub Jelinek <jakub@redhat.com>, 2003. @@ -47,6 +47,9 @@ typedef uintptr_t uatomicptr_t; typedef intmax_t atomic_max_t; typedef uintmax_t uatomic_max_t; +#define __HAVE_64B_ATOMICS 0 +#define USE_ATOMIC_COMPILER_BUILTINS 0 + /* We have no compare and swap, just test and set. The following implementation contends on 64 global locks @@ -102,27 +105,28 @@ volatile unsigned char __sparc32_atomic_locks[64] #define __sparc32_atomic_do_unlock24(addr) \ do \ { \ - *(char *) (addr) = 0; \ __asm __volatile ("" ::: "memory"); \ + *(char *) (addr) = 0; \ } \ while (0) #ifndef SHARED # define __v9_compare_and_exchange_val_32_acq(mem, newval, oldval) \ -({ \ - register __typeof (*(mem)) __acev_tmp __asm ("%g6"); \ +({union { __typeof (oldval) a; uint32_t v; } oldval_arg = { .a = (oldval) }; \ + union { __typeof (newval) a; uint32_t v; } newval_arg = { .a = (newval) }; \ + register uint32_t __acev_tmp __asm ("%g6"); \ register __typeof (mem) __acev_mem __asm ("%g1") = (mem); \ - register __typeof (*(mem)) __acev_oldval __asm ("%g5"); \ - __acev_tmp = (newval); \ - __acev_oldval = (oldval); \ + register uint32_t __acev_oldval __asm ("%g5"); \ + __acev_tmp = newval_arg.v; \ + __acev_oldval = oldval_arg.v; \ /* .word 0xcde05005 is cas [%g1], %g5, %g6. Can't use cas here though, \ because as will then mark the object file as V8+ arch. */ \ __asm __volatile (".word 0xcde05005" \ : "+r" (__acev_tmp), "=m" (*__acev_mem) \ : "r" (__acev_oldval), "m" (*__acev_mem), \ "r" (__acev_mem) : "memory"); \ - __acev_tmp; }) + (__typeof (oldval)) __acev_tmp; }) #endif /* The only basic operation needed is compare and exchange. */ @@ -343,8 +347,8 @@ extern uint64_t _dl_hwcap __attribute__((weak)); #define atomic_write_barrier() \ do { \ if (__atomic_is_v9) \ - /* membar #StoreLoad | #StoreStore */ \ - __asm __volatile (".word 0x8143e00a" : : : "memory"); \ + /* membar #LoadStore | #StoreStore */ \ + __asm __volatile (".word 0x8143e00c" : : : "memory"); \ else \ __asm __volatile ("" : : : "memory"); \ } while (0) |