diff options
| author | Jakub Jelinek <jakub@redhat.com> | 2005-04-01 15:13:31 +0000 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2005-04-01 15:13:31 +0000 |
| commit | e8eaba2b25948c0e60f70c33c5c52aad70bbf5fc (patch) | |
| tree | 020566c0ffd2d27131ee7bac45eea5560a4732bd /sysdeps/mips/sys | |
| parent | e3166b6660ce5f0640242a4806a380bb651a2291 (diff) | |
Updated to fedora-glibc-20050401T1444
Diffstat (limited to 'sysdeps/mips/sys')
| -rw-r--r-- | sysdeps/mips/sys/asm.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/sysdeps/mips/sys/asm.h b/sysdeps/mips/sys/asm.h index b04c36ba5e..b590802fd9 100644 --- a/sysdeps/mips/sys/asm.h +++ b/sysdeps/mips/sys/asm.h @@ -1,4 +1,5 @@ -/* Copyright (C) 1997, 1998, 2002, 2003, 2004 Free Software Foundation, Inc. +/* Copyright (C) 1997, 1998, 2002, 2003, 2004, 2005 + Free Software Foundation, Inc. This file is part of the GNU C Library. Contributed by Ralf Baechle <ralf@gnu.org>. @@ -470,4 +471,20 @@ symbol = value # define MTC0 dmtc0 #endif +/* The MIPS archtectures do not have a uniform memory model. Particular + platforms may provide additional guarantees - for instance, the R4000 + LL and SC instructions implicitly perform a SYNC, and the 4K promises + strong ordering. + + However, in the absence of those guarantees, we must assume weak ordering + and SYNC explicitly where necessary. + + Some obsolete MIPS processors may not support the SYNC instruction. This + applies to "true" MIPS I processors; most of the processors which compile + using MIPS I implement parts of MIPS II. */ + +#ifndef MIPS_SYNC +# define MIPS_SYNC sync +#endif + #endif /* sys/asm.h */ |