diff options
| author | Maciej W. Rozycki <macro@codesourcery.com> | 2013-08-22 17:50:20 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@codesourcery.com> | 2013-08-22 17:55:17 +0100 |
| commit | b72ca61b71abd3e2d5b6cdb0680d7179f95be222 (patch) | |
| tree | 79913c2c6a952e2eda419b7d0766df4c13b2f48b /ports/ChangeLog.mips | |
| parent | d1141ff6c875bc53c5ef6cd62b1bbfe91bdccd21 (diff) | |
MIPS: Correct the handling of reserved FCSR bits
Reserved bits in the Floating-Point Control and Status Register (FCSR)
should not be implicitly cleared by fedisableexcept or feenableexcept,
there is no reason to. Among these are the 8 condition codes and one of
the two bits reserved for architecture implementers (bits #22 & #21).
As to the latter, there is no reason to treat any of them as reserved
either, they should be user controllable and settable via __fpu_control
override as the user sees fit. For example in processors implemented by
MIPS Technologies, such as the 5Kf or the 24Kf, these bits are used to
change the treatment of denormalised operands and tiny results: bit #22
is Flush Override (FO) and bit #21 is Flush to Nearest (FN). They cause
non-IEEE-compliant behaviour, but some programs may have a use for such
modes of operation; the library should not obstruct such use just as it
does not for the architectural Flush to Zero (FS) bit (bit #24).
Therefore the change adjusts the reserved mask accordingly and also
documents the distinction between bits 22:21 and 20:18.
Diffstat (limited to 'ports/ChangeLog.mips')
| -rw-r--r-- | ports/ChangeLog.mips | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/ports/ChangeLog.mips b/ports/ChangeLog.mips index 6e42b77de3..9b952c6101 100644 --- a/ports/ChangeLog.mips +++ b/ports/ChangeLog.mips @@ -1,3 +1,12 @@ +2013-08-22 Maciej W. Rozycki <macro@codesourcery.com> + + * sysdeps/mips/fpu_control.h: Document bits reserved for + architecture implementers. + (_FPU_RESERVED): Clear bit #21. + * sysdeps/mips/fpu/fedisblxcpt.c (fedisableexcept): Don't clear + reserved bits. + * sysdeps/mips/fpu/feenablxcpt.c (feenableexcept): Likewise. + 2013-07-02 Joseph Myers <joseph@codesourcery.com> * sysdeps/mips/mips32/libm-test-ulps: Regenerated. |