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/*
 *  XIOH power sequence
 *  Copyright (C) 2013  Avencall
 *
 *  xioh_v6.h - platform definitions for V6 board
 *  Author:
 *    Guillaume Knispel
 *
 *  This program is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

/* NOTES:
 *
 * * V1P2_CORE_EN_N is initialized as an output high for a reason!
 *
 * ATX specifies that there can be as much as 20 ms between 5V reaching
 * its 95% level and 3.3V doing likewise. U5H1 (ISL6545) is powered by
 * 5V, and Q5U1 (that disables it) has a pull-up to 3.3V on its gate.
 * ISL6545 can ramp up its output between ~ 10 and 17 ms after
 * Power On Reset (defined by an high enough voltage on the 5V plane),
 * and might do it even before.
 * So when only using the pull-up to 3.3V rail and with an ATX
 * power supply that has a particular timing, V1P2 would start to
 * ramp up too early.
 */

#ifndef XIOH_V6_H
#define XIOH_V6_H

/* PYTHON:
defines="""
 * WARNING: DON'T FORGET TO MAINTAIN ALL_SIGNALS(w)
 */
#define VRMPWRGD(w)		GD_(w, P1_0, GPIO_OUT,      0)
#define V1P2_CORE_EN_N(w)	GD_(w, P1_1, GPIO_OUT,      1)
#define START_SW_N(w)		GD_(w, P1_2, GPIO_IN_PULL,  1)
#define WDT_TOUT_N(w)		GD_(w, P1_3, GPIO_IN_FLOAT, 0)

/* RED_LED_N and PWM_FAN are shared with JTAG on V6 */
#define RED_LED_N(w)		GD_(w, P1_5, GPIO_OUT,      1)
#define PWM_FAN(w)		GD_(w, P1_6, GPIO_OUT,      0)

#define CK410_PWR_GD_N(w)	GD_(w, P2_0, GPIO_IN_PULL,  1)
#define TEMP_SENSOR(w)		GD_(w, P2_1, GPIO_IN_FLOAT, 0)
#define CPU_VCCP_EN_N(w)	GD_(w, P2_2, GPIO_OUT,      1)
#define GREEN_LED_N(w)		GD_(w, P2_3, GPIO_OUT,      1)
#define _2V5_REF(w)		GD_(w, P2_4, GPIO_IN_FLOAT, 0)
#define SYS_RESET_N(w)		GD_(w, P2_5, GPIO_IN_PULL,  1)
#define IMCH_PWRBTN_N(w)	GD_(w, P2_6, GPIO_IN_FLOAT, 0)
#define IMCH_RSMRST_N(w)	GD_(w, P2_7, GPIO_OUT,      0)
#define VCC3(w)			GD_(w, P3_0, GPIO_IN_FLOAT, 0)
#define I2C_SMBDAT(w)		GD_(w, P3_1, GPIO_IN_FLOAT, 0)
#define I2C_SMBCLK(w)		GD_(w, P3_2, GPIO_IN_FLOAT, 0)
#define SYS_PWR_OK(w)		GD_(w, P3_3, GPIO_OUT,      0)
#ifdef TRACE_SERIAL
# define MSP_BSL_TXD(w)		GD_(w, P3_4, PERIPH,        0)
# define MSP_BSL_RXD(w)		GD_(w, P3_5, PERIPH,        0)
#else /* ndef TRACE_SERIAL */
# define MSP_BSL_TXD(w)		GD_(w, P3_4, GPIO_IN_FLOAT, 0)
# define MSP_BSL_RXD(w)		GD_(w, P3_5, GPIO_IN_FLOAT, 0)
#endif /* TRACE_SERIAL */
#define P1V8_PGOOD(w)		GD_(w, P3_6, GPIO_IN_FLOAT, 0)
#define _2V5_REF_DIV2(w)	GD_(w, P3_7, GPIO_IN_FLOAT, 0)
#define SLP_S3_N(w)		GD_(w, P4_0, GPIO_IN_PULL,  0)
#define ATX_PWROK(w)		GD_(w, P4_1, GPIO_IN_PULL,  0)
#define CMDPWR(w)		GD_(w, P4_2, GPIO_OUT,      0)
#define V1P0(w)			GD_(w, P4_3, GPIO_IN_FLOAT, 0)
#define V1P2(w)			GD_(w, P4_4, GPIO_IN_FLOAT, 0)
#define V1P8_DDR(w)		GD_(w, P4_5, GPIO_IN_FLOAT, 0)
#define V2P5(w)			GD_(w, P4_6, GPIO_IN_FLOAT, 0)
#define V1P8_CMD(w)		GD_(w, P4_7, GPIO_OUT,      0)
/*
 * WARNING: DON'T FORGET TO MAINTAIN ALL_SIGNALS(w)
"""
import re

def add_backslash(s):
    return s + (" " * (20 - len(s))) + "\\"

def extract_and_print():
    deflines = [line.strip()
                for line in defines.splitlines()
                if "define " in line]
    all_signals = list(set([re.search(r'define\s+([^\s]+)', line).group(1)
                            for line in deflines]))
    for sig in all_signals:
        if not sig.endswith("(w)"):
            raise ValueError("all signal defines should ends with (w), "
	                     "%s does not" % sig)
    print "#define ALL_SIGNALS(w)\t\t" + add_backslash(all_signals[0])
    for sig in all_signals[1:-1]:
        print "\t\t\t\t" + add_backslash(sig)
    print "\t\t\t\t" + all_signals[-1]

extract_and_print()
 */
#define ALL_SIGNALS(w)		RED_LED_N(w)        \
				CPU_VCCP_EN_N(w)    \
				IMCH_RSMRST_N(w)    \
				SYS_PWR_OK(w)       \
				V2P5(w)             \
				MSP_BSL_TXD(w)      \
				PWM_FAN(w)          \
				START_SW_N(w)       \
				IMCH_PWRBTN_N(w)    \
				ATX_PWROK(w)        \
				V1P0(w)             \
				WDT_TOUT_N(w)       \
				VCC3(w)             \
				I2C_SMBDAT(w)       \
				V1P2(w)             \
				P1V8_PGOOD(w)       \
				MSP_BSL_RXD(w)      \
				SLP_S3_N(w)         \
				GREEN_LED_N(w)      \
				_2V5_REF_DIV2(w)    \
				CK410_PWR_GD_N(w)   \
				V1P8_CMD(w)         \
				VRMPWRGD(w)         \
				TEMP_SENSOR(w)      \
				CMDPWR(w)           \
				SYS_RESET_N(w)      \
				V1P2_CORE_EN_N(w)   \
				_2V5_REF(w)         \
				I2C_SMBCLK(w)       \
				V1P8_DDR(w)

#endif /* XIOH_V6_H */