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diff --git a/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h new file mode 100644 index 0000000..3a8351b --- /dev/null +++ b/Acceleration/library/icp_telephony/tdm_infrastructure_downloader/include/IxPiuDlPiuMgrEcRegisters_p.h @@ -0,0 +1,982 @@ +/** + * @file IxPiuDlPiuMgrEcRegisters_p.h + * + * @author Intel Corporation + * @date 13 August 2003 + + * + * @par + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * GPL LICENSE SUMMARY + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * The full GNU General Public License is included in this distribution + * in the file called LICENSE.GPL. + * + * Contact Information: + * Intel Corporation + * + * BSD LICENSE + * + * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * +*/ + + +#ifndef IXPIUDLPIUMGRECREGISTERS_P_H +#define IXPIUDLPIUMGRECREGISTERS_P_H + +/* + * Put the system defined include files required. + */ + +#if defined(__linux) +#if !defined(__ep805xx) +#include <asm/hardware.h> +#endif +#endif + +/* + * Put the user defined include files required. + */ + + +/* + * Instruction Memory Size (in words) for each PIU + */ + +#define IX_PIUDL_PIUBASEADDRESS_PIU0_MAP(phys)\ +IX_OSAL_MEM_MAP((phys),0) + +#define IX_PIUDL_PIUBASEADDRESS_PIU1_MAP(phys)\ +IX_OSAL_MEM_MAP((phys),0) + +#define IX_PIUDL_PIUBASEADDRESS_UNMAP(virt)\ +IX_OSAL_MEM_UNMAP((virt)) + + + + + +/** + * @def IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 + * @brief Size (in words) of PIU-0 Instruction Memory + */ +#if defined(__ep805xx) +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 (8192) +#else +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU0 (4096) +#endif + +/** + * @def IX_PIUDL_INS_MEMSIZE_WORDS_PIU1 + * @brief Size (in words) of PIU-1 Instruction Memory + */ +#define IX_PIUDL_INS_MEMSIZE_WORDS_PIU1 (4096) + + +/* + * Data Memory Size (in words) for each PIU + */ + +/** + * @def IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 + * @brief Size (in words) of PIU-0 Data Memory + */ +#define IX_PIUDL_DATA_MEMSIZE_WORDS_PIU0 (8192) + +/** + * @def IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 + * @brief Size (in words) of PIU-1 Data Memory + */ +#define IX_PIUDL_DATA_MEMSIZE_WORDS_PIU1 (4096) + + +/* + * Configuration Bus Register offsets (in bytes) from PIU Base Address + */ + +/** + * @def IX_PIUDL_REG_OFFSET_EXAD + * @brief Offset (in bytes) of EXAD (Execution Address) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXAD (0x00000000) + +/** + * @def IX_PIUDL_REG_OFFSET_EXDATA + * @brief Offset (in bytes) of EXDATA (Execution Data) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXDATA (0x00000004) + +/** + * @def IX_PIUDL_REG_OFFSET_EXCTL + * @brief Offset (in bytes) of EXCTL (Execution Control) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXCTL (0x00000008) + +/** + * @def IX_PIUDL_REG_OFFSET_EXCT + * @brief Offset (in bytes) of EXCT (Execution Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_EXCT (0x0000000C) + +/** + * @def IX_PIUDL_REG_OFFSET_AP0 + * @brief Offset (in bytes) of AP0 (Action Point 0) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP0 (0x00000010) + +/** + * @def IX_PIUDL_REG_OFFSET_AP1 + * @brief Offset (in bytes) of AP1 (Action Point 1) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP1 (0x00000014) + +/** + * @def IX_PIUDL_REG_OFFSET_AP2 + * @brief Offset (in bytes) of AP2 (Action Point 2) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP2 (0x00000018) + +/** + * @def IX_PIUDL_REG_OFFSET_AP3 + * @brief Offset (in bytes) of AP3 (Action Point 3) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_AP3 (0x0000001C) + +/** + * @def IX_PIUDL_REG_OFFSET_WFIFO + * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_WFIFO (0x00000020) + +/** + * @def IX_PIUDL_REG_OFFSET_WC + * @brief Offset (in bytes) of WC (Watch Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_WC (0x00000024) + +/** + * @def IX_PIUDL_REG_OFFSET_PROFCT + * @brief Offset (in bytes) of PROFCT (Profile Count) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_PROFCT (0x00000028) + +/** + * @def IX_PIUDL_REG_OFFSET_STAT + * @brief Offset (in bytes) of STAT (Messaging Status) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_STAT (0x0000002C) + +/** + * @def IX_PIUDL_REG_OFFSET_CTL + * @brief Offset (in bytes) of CTL (Messaging Control) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_CTL (0x00000030) + +/** + * @def IX_PIUDL_REG_OFFSET_MBST + * @brief Offset (in bytes) of MBST (Mailbox Status) register from PIU Base + * Address + */ +#define IX_PIUDL_REG_OFFSET_MBST (0x00000034) + +/** + * @def IX_PIUDL_REG_OFFSET_FIFO + * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from PIU + * Base Address + */ +#define IX_PIUDL_REG_OFFSET_FIFO (0x00000038) + + +/* + * Non-zero reset values for the Configuration Bus registers + */ + +/** + * @def IX_PIUDL_REG_RESET_FIFO + * @brief Reset value for Mailbox (MBST) register + * NOTE that if used, it should be complemented with an PIU intruction + * to clear the Mailbox at the PIU side as well + */ +#define IX_PIUDL_REG_RESET_MBST (0x0000F0F0) + + +/* + * Bit-masks used to read/write particular bits in Configuration Bus registers + */ + +/** + * @def IX_PIUDL_MASK_WFIFO_VALID + * @brief Masks the VALID bit in the WFIFO register + */ +#define IX_PIUDL_MASK_WFIFO_VALID (0x80000000) + +/** + * @def IX_PIUDL_MASK_STAT_OFNE + * @brief Masks the OFNE bit in the STAT register + */ +#define IX_PIUDL_MASK_STAT_OFNE (0x00010000) + +/** + * @def IX_PIUDL_MASK_STAT_IFNE + * @brief Masks the IFNE bit in the STAT register + */ +#define IX_PIUDL_MASK_STAT_IFNE (0x00080000) + + +/* + * EXCTL (Execution Control) Register commands +*/ + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_STEP + * @brief EXCTL Command to Step execution of an PIU Instruction + */ + +#define IX_PIUDL_EXCTL_CMD_PIU_STEP (0x01) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_START + * @brief EXCTL Command to Start PIU execution + */ +#define IX_PIUDL_EXCTL_CMD_PIU_START (0x02) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_STOP + * @brief EXCTL Command to Stop PIU execution + */ +#define IX_PIUDL_EXCTL_CMD_PIU_STOP (0x03) + +/** + * @def IX_PIUDL_EXCTL_CMD_CLR_TRIGGER + * @brief EXCTL Command to clear TRIGGER interrupt event source + */ +#define IX_PIUDL_EXCTL_CMD_CLR_TRIGGER (0x0d) + +/** + * @def IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE + * @brief EXCTL Command to Clear PIU instruction pipeline + */ +#define IX_PIUDL_EXCTL_CMD_PIU_CLR_PIPE (0x04) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_INS_MEM + * @brief EXCTL Command to read PIU instruction memory at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_INS_MEM (0x10) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_INS_MEM + * @brief EXCTL Command to write PIU instruction memory at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_INS_MEM (0x11) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_DATA_MEM + * @brief EXCTL Command to read PIU data memory at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_DATA_MEM (0x12) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_DATA_MEM + * @brief EXCTL Command to write PIU data memory at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_DATA_MEM (0x13) + +/** + * @def IX_PIUDL_EXCTL_CMD_RD_ECS_REG + * @brief EXCTL Command to read Execution Access register at address in EXAD + * register and return value in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_RD_ECS_REG (0x14) + +/** + * @def IX_PIUDL_EXCTL_CMD_WR_ECS_REG + * @brief EXCTL Command to write Execution Access register at address in EXAD + * register with data in EXDATA register + */ +#define IX_PIUDL_EXCTL_CMD_WR_ECS_REG (0x15) + +/** + * @def IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT + * @brief EXCTL Command to clear Profile Count register + */ +#define IX_PIUDL_EXCTL_CMD_CLR_PROFILE_CNT (0x0C) + + +/* + * EXCTL (Execution Control) Register status bit masks + */ + +/** + * @def IX_PIUDL_EXCTL_STATUS_RUN + * @brief Masks the RUN status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_RUN (0x80000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_STOP + * @brief Masks the STOP status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_STOP (0x40000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_CLEAR + * @brief Masks the CLEAR status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_CLEAR (0x20000000) + +/** + * @def IX_PIUDL_EXCTL_STATUS_ECS_K + * @brief Masks the K (pipeline Klean) status bit in the EXCTL register + */ +#define IX_PIUDL_EXCTL_STATUS_ECS_K (0x00800000) + + +/* + * Executing Context Stack (ECS) level registers + */ + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_0 (0x00) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_1 (0x01) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Backgound + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_2 (0x02) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_0 (0x04) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_1 (0x05) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Priority 1 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_2 (0x06) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_0 (0x08) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_1 (0x09) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Priority 2 + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_2 (0x0A) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_0 + * @brief Execution Access register address for register 0 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_0 (0x0C) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_1 + * @brief Execution Access register address for register 1 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_1 (0x0D) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_2 + * @brief Execution Access register address for register 2 at Debug + * Executing Context Stack level + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_2 (0x0E) + +/** + * @def IX_PIUDL_ECS_INSTRUCT_REG + * @brief Execution Access register address for PIU Instruction Register + */ +#define IX_PIUDL_ECS_INSTRUCT_REG (0x11) + + +/* + * Execution Access register reset values + */ + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Background ECS level register 0 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_0_RESET (0xA0000000) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Background ECS level register 1 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_BG_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Background ECS level register 2 + */ +#define IX_PIUDL_ECS_BG_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 0 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_0_RESET (0x20000080) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 1 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Priority 1 ECS level register 2 + */ +#define IX_PIUDL_ECS_PRI_1_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 0 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_0_RESET (0x20000080) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 1 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_1_RESET (0x01000000) + +/** + * @def IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Priority 2 ECS level register 2 + */ +#define IX_PIUDL_ECS_PRI_2_CTXT_REG_2_RESET (0x00008000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET + * @brief Reset value for Execution Access Debug ECS level register 0 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_0_RESET (0x20000000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET + * @brief Reset value for Execution Access Debug ECS level register 1 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_1_RESET (0x00000000) + +/** + * @def IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET + * @brief Reset value for Execution Access Debug ECS level register 2 + */ +#define IX_PIUDL_ECS_DBG_CTXT_REG_2_RESET (0x001E0000) + +/** + * @def IX_PIUDL_ECS_INSTRUCT_REG_RESET + * @brief Reset value for Execution Access PIU Instruction Register + */ +#define IX_PIUDL_ECS_INSTRUCT_REG_RESET (0x1003C00F) + + +/* + * masks used to read/write particular bits in Execution Access registers + */ + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_ACTIVE + * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS + * levels + */ +#define IX_PIUDL_MASK_ECS_REG_0_ACTIVE (0x80000000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_NEXTPC + * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS + * levels (except Debug ECS level) + */ +#define IX_PIUDL_MASK_ECS_REG_0_NEXTPC (0x1FFF0000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_0_LDUR + * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_0_LDUR (0x00000700) + +/** + * @def IX_PIUDL_MASK_ECS_REG_1_CCTXT + * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_1_CCTXT (0x000F0000) + +/** + * @def IX_PIUDL_MASK_ECS_REG_1_SELCTXT + * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels + */ +#define IX_PIUDL_MASK_ECS_REG_1_SELCTXT (0x0000000F) + +/** + * @def IX_PIUDL_MASK_ECS_DBG_REG_2_IF + * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level + */ +#define IX_PIUDL_MASK_ECS_DBG_REG_2_IF (0x00100000) + +/** + * @def IX_PIUDL_MASK_ECS_DBG_REG_2_IE + * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level + */ +#define IX_PIUDL_MASK_ECS_DBG_REG_2_IE (0x00080000) + + +/* + * Bit-Offsets from LSB of particular bit-fields in Execution Access registers + */ + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC + * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS + * levels (except Debug ECS level) + */ +#define IX_PIUDL_OFFSET_ECS_REG_0_NEXTPC (16) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_0_LDUR + * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_0_LDUR (8) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_1_CCTXT + * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_1_CCTXT (16) + +/** + * @def IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT + * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS + * levels + */ +#define IX_PIUDL_OFFSET_ECS_REG_1_SELCTXT (0) + + +/* + * PIU core & co-processor instruction templates to load into PIU Instruction + * Register, for read/write of PIU register file registers + */ + +/** + * @def IX_PIUDL_INSTR_RD_REG_BYTE + * @brief PIU Instruction, used to read an 8-bit PIU internal logical register + * and return the value in the EXDATA register (aligned to MSB). + * PIU Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_BYTE (0x0FC00000) + +/** + * @def IX_PIUDL_INSTR_RD_REG_SHORT + * @brief PIU Instruction, used to read a 16-bit PIU internal logical register + * and return the value in the EXDATA register (aligned to MSB). + * PIU Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_SHORT (0x0FC08010) + +/** + * @def IX_PIUDL_INSTR_RD_REG_WORD + * @brief PIU Instruction, used to read a 16-bit PIU internal logical register + * and return the value in the EXDATA register. + * PIU Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" + */ +#define IX_PIUDL_INSTR_RD_REG_WORD (0x0FC08210) + +/** + * @def IX_PIUDL_INSTR_WR_REG_BYTE + * @brief PIU Immediate-Mode Instruction, used to write an 8-bit PIU internal + * logical register. + * PIU Assembler instruction: "mov8 d0, #0" + */ +#define IX_PIUDL_INSTR_WR_REG_BYTE (0x00004000) + +/** + * @def IX_PIUDL_INSTR_WR_REG_SHORT + * @brief PIU Immediate-Mode Instruction, used to write a 16-bit PIU internal + * logical register. + * PIU Assembler instruction: "mov16 d0, #0" + */ +#define IX_PIUDL_INSTR_WR_REG_SHORT (0x0000C000) + +/** + * @def IX_PIUDL_INSTR_RD_FIFO + * @brief PIU Immediate-Mode Instruction, used to write a 16-bit PIU internal + * logical register. + * PIU Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" + */ +#define IX_PIUDL_INSTR_RD_FIFO (0x0F888220) + +/** + * @def IX_PIUDL_INSTR_RESET_MBOX + * @brief PIU Instruction, used to reset Mailbox (MBST) register + * PIU Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" + */ +#define IX_PIUDL_INSTR_RESET_MBOX (0x0FAC8210) + + +/** + * @def IX_PIUDL_INSTR_RESET_COPROCS + * @brief PIU Instruction, used to reset co-processors. Register d0 must + * contain the value (0xFFFF to reset all co-processors. + * PIU Assembler instruction: "mov16 d0, d0 &&&DBG_WrRst" + */ +#define IX_PIUDL_INSTR_RESET_COPROCS (0xAFB88010) + + +/* + * Bit-offsets from LSB, of particular bit-fields in an PIU instruction + */ + +/** + * @def IX_PIUDL_OFFSET_INSTR_SRC + * @brief LSB-offset to SRC (source operand) field of an PIU Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_SRC (4) + +/** + * @def IX_PIUDL_OFFSET_INSTR_DEST + * @brief LSB-offset to DEST (destination operand) field of an PIU Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_DEST (9) + +/** + * @def IX_PIUDL_OFFSET_INSTR_COPROC + * @brief LSB-offset to COPROC (coprocessor instruction) field of an PIU + * Instruction + */ +#define IX_PIUDL_OFFSET_INSTR_COPROC (18) + + +/* + * masks used to read/write particular bits of an PIU Instruction + */ + +/** + * @def IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA + * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in + * SRC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_MASK_IMMED_INSTR_SRC_DATA (0x1F) + +/** + * @def IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA + * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in + * COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_MASK_IMMED_INSTR_COPROC_DATA (0xFFE0) + +/** + * @def IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA + * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) + * to be used in COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA (5) + +/** + * @def IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA + * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit + * data value into COPROC field of immediate-mode PIU instruction + */ +#define IX_PIUDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ + (IX_PIUDL_OFFSET_INSTR_COPROC - IX_PIUDL_OFFSET_IMMED_INSTR_COPROC_DATA) + +/** + * @def IX_PIUDL_WR_INSTR_LDUR + * @brief LDUR value used with immediate-mode PIU Instructions by the PiuDl + * for writing to PIU internal logical registers + */ +#define IX_PIUDL_WR_INSTR_LDUR (1) + +/** + * @def IX_PIUDL_RD_INSTR_LDUR + * @brief LDUR value used with NON-immediate-mode PIU Instructions by the PiuDl + * for reading from PIU internal logical registers + */ +#define IX_PIUDL_RD_INSTR_LDUR (0) + + +/** + * @enum IxPiuDlCtxtRegNum + * @brief Numeric values to identify the PIU internal Context Store registers + */ +typedef enum +{ + IX_PIUDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ + IX_PIUDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ + IX_PIUDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ + IX_PIUDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ + IX_PIUDL_CTXT_REG_MAX /**< Total number of Context Store registers */ +} IxPiuDlCtxtRegNum; + + +/* + * PIU Context Store register logical addresses + */ + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_STEVT + * @brief Logical address of STEVT PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_STEVT (0x0000001B) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_STARTPC + * @brief Logical address of STARTPC PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_STARTPC (0x0000001C) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_REGMAP + * @brief Logical address of REGMAP PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_REGMAP (0x0000001E) + +/** + * @def IX_PIUDL_CTXT_REG_ADDR_CINDEX + * @brief Logical address of CINDEX PIU internal Context Store register + */ +#define IX_PIUDL_CTXT_REG_ADDR_CINDEX (0x0000001F) + + +/* + * PIU Context Store register reset values + */ + +/** + * @def IX_PIUDL_CTXT_REG_RESET_STEVT + * @brief Reset value of STEVT PIU internal Context Store register + * (STEVT = off, 0x80) + */ +#define IX_PIUDL_CTXT_REG_RESET_STEVT (0x80) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_STARTPC + * @brief Reset value of STARTPC PIU internal Context Store register + * (STARTPC = 0x0000) + */ +#define IX_PIUDL_CTXT_REG_RESET_STARTPC (0x0000) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_REGMAP + * @brief Reset value of REGMAP PIU internal Context Store register + * (REGMAP = d0->p0, d8->p2, d16->p4) + */ +#define IX_PIUDL_CTXT_REG_RESET_REGMAP (0x0820) + +/** + * @def IX_PIUDL_CTXT_REG_RESET_CINDEX + * @brief Reset value of CINDEX PIU internal Context Store register + * (CINDEX = 0) + */ +#define IX_PIUDL_CTXT_REG_RESET_CINDEX (0x00) + + +/* + * numeric range of context levels available on an PIU + */ + +/** + * @def IX_PIUDL_CTXT_NUM_MIN + * @brief Lowest PIU Context number in range + */ +#define IX_PIUDL_CTXT_NUM_MIN (0) + +/** + * @def IX_PIUDL_CTXT_NUM_MAX + * @brief Highest PIU Context number in range + */ +#define IX_PIUDL_CTXT_NUM_MAX (15) + + +/* + * Physical PIU internal registers + */ + +/** + * @def IX_PIUDL_TOTAL_NUM_PHYS_REG + * @brief Number of Physical registers currently supported + * Initial PIU implementations will have a 32-word register file. + * Later implementations may have a 64-word register file. + */ +#define IX_PIUDL_TOTAL_NUM_PHYS_REG (32) + +/** + * @def IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP + * @brief LSB-offset of Regmap number in Physical PIU register address, used + * for Physical To Logical register address mapping in the PIU + */ +#define IX_PIUDL_OFFSET_PHYS_REG_ADDR_REGMAP (1) + +/** + * @def IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR + * @brief Mask to extract a logical PIU register address from a physical + * register address, used for Physical To Logical address mapping + */ +#define IX_PIUDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR (0x1) + +#if defined(__ep805xx) +/* + * application specific dual related defines + */ + +/** + * @def IX_PIUDL_APPDUAL_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction Id + */ +#define IX_PIUDL_APPDUAL_ID_MAX (0xF) + +/** + * @def IX_PIUDL_APPDUAL_COPR_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction coprocessor Id + */ +#define IX_PIUDL_APPDUAL_COPR_ID_MAX (0xF) + +/** + * @def IX_PIUDL_APPDUAL_INST_ID_MAX + * @brief The maximum number for an application specific dual coprocessor + * instruction instruction Id + */ +#define IX_PIUDL_APPDUAL_INST_ID_MAX (0x3F) + +/** + * @def IX_PIUDL_APPDUAL_REG_OFFSET + * @brief The register offset from the base address for application specific + * dual coprocessor instruction configuration registers + */ +#define IX_PIUDL_APPDUAL_REG_OFFSET (0x20) + +/** + * @def IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 0 decode field + */ +#define IX_PIUDL_APPDUAL_REG_COPR0_BIT_OFFSET (16) + +/** + * @def IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 0 instruction decode field + */ +#define IX_PIUDL_APPDUAL_REG_INST0_BIT_OFFSET (0) + +/** + * @def IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 1 decode field + */ +#define IX_PIUDL_APPDUAL_REG_COPR1_BIT_OFFSET (24) + +/** + * @def IX_PIUDL_APPDUAL_REG_INST1_OFFSET + * @brief The offset within the application specific dual coprocessor register + * for the coprocessor 1 instruction decode field + */ +#define IX_PIUDL_APPDUAL_REG_INST1_BIT_OFFSET (8) + +#endif // #if defined(__ep805xx) + +#endif /* IXPIUDLPIUMGRECREGISTERS_P_H */ |