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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
#define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
#include <stdint.h>
#define __stringify_1(x) #x
#define __stringify(x) __stringify_1(x)
#define mdelay(msecs) udelay(1000*(msecs))
#define DIMM_SOCKETS 2
#define BAR 0x90000000
/* DDR2 SDRAM mode register (MR) */
#define MR_BURST_LENGTH 0
#define MR_BL_4 2
#define MR_BL_8 3
#define MR_BURST_TYPE 3
#define MR_CAS_LAT 4
#define MR_TM 7
#define MR_DLL_RST 8
#define MR_WR 9
#define MR_PD 12
/* DDR2 SDRAM extended mode register 1 (EMR(1)) */
#define EMR1_Rtt0 2
#define EMR1_Rtt1 6
#define EMR1_Rtt1_disable 0
#define EMR1_Rtt0_disable 0
#define EMR1_Rtt1_75ohm 0
#define EMR1_Rtt0_75ohm 1
#define EMR1_Rtt1_150ohm 1
#define EMR1_Rtt0_150ohm 0
#define EMR1_OCD 7
#define EMR1_OCD_cal_exit 0
#define EMR1_OCD_cal_default 0
/* DCALADDR values */
#define DCALADDR_MR 0
#define DCALADDR_EMR1 1
#define DCALADDR_EMR2 2
#define DCALADDR_EMR3 3
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
#else
#define PRINTK_DEBUG(x...)
#endif
enum ddr_speed { DDR_400, DDR_533, DDR_667, DDR_800, DDR_1066 };
enum dev_size { DEV_2Gb, DEV_1Gb, DEV_512Mb, DEV_256Mb };
enum fsb_speed { FSB_133, FSB_100 };
struct ram_timing { enum ddr_speed speed; u8 CL, tRCD, tRP; };
enum speed_bin {
DDR2_1066E,
DDR2_1066F,
DDR2_800C,
DDR2_800D,
DDR2_800E,
DDR2_667C,
DDR2_667D,
DDR2_533B,
DDR2_533C,
DDR2_400B,
DDR2_400C,
NUM_SPEED_BINS
};
struct mem_controller {
u8* spd;
int dimm_num;
enum ddr_speed max_speed;
int CL[2][3];
int tAC[2][3];
int tCK[2][3];
u8 tRP[2];
u8 tRCD[2];
/* Max timing confs supported = number of standard speed bins + 3 other
* speed bins explicitly supported in SPD */
struct ram_timing support[2][NUM_SPEED_BINS+3];
struct ram_timing common[NUM_SPEED_BINS+3];
int n_support[2];
int n_common;
struct ram_timing timing;
u8 mastcntl;
u8 ecc;
};
/* Function prototypes. */
void sdram_initialize(struct mem_controller *mch);
int memory_initialized(void);
#endif /* NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H */
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