path: root/src/northbridge/intel/i3100/raminit_ep80579.c

/*
 * This file is part of the coreboot project.
 *
 * Copyright (C) 2011 Avencall
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <console/console.h>
#include <delay.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <stdlib.h>
#include <spd_ddr2.h>
#include <cpu/x86/msr.h>
#include <arch/hlt.h>
#include "southbridge/intel/i3100/early_smbus.h"
// #include <device/pci.h>
// #include <device/pci_def.h>
// #include <device/pci_ops.h>

#include "ep80579.h"
#include "raminit_ep80579.h"

#define BAR 0x90000000

#define dbg_pci_write_config32(dev, reg, val) do { \
		PRINTK_DEBUG(#reg "=%08x\n", val); \
		pci_write_config32(dev, reg, val); \
	} while (0)

#define dbg_pci_write_config16(dev, reg, val) do { \
		PRINTK_DEBUG(#reg "=%04x\n", val); \
		pci_write_config16(dev, reg, val); \
	} while (0)

#define dbg_pci_write_config8(dev, reg, val) do { \
		PRINTK_DEBUG(#reg "=%02x\n", val); \
		pci_write_config8(dev, reg, val); \
	} while (0)


#define spd_read_byte smbus_read_byte

#if CONFIG_DEBUG_RAM_SETUP

# define die(...) do { \
		printk(BIOS_EMERG, __VA_ARGS__); \
		\
		printk(BIOS_DEBUG, "\nRAM STARTUP FAILURE, DUMPING REGS:\n"); \
		dump_ram_regs(BIOS_DEBUG);\
		\
		while(1) hlt(); \
	} while (0)

#else

# define die(...) do { printk(BIOS_EMERG, __VA_ARGS__); while(1) hlt(); } \
		  while(0)

#endif

#if CONFIG_DEBUG_RAM_SETUP

static void dump_spd_registers(struct mem_controller *mch)
{
	unsigned device;
	int j;

	for (j = 0; j < DIMM_SOCKETS; j++) {
		device = mch->spd[j];
		int status = 0;
		int i;
		printk(BIOS_DEBUG, "\ndimm %02x", device);

		for(i = 0; (i < 256) ; i++) {

			if ((i % 16) == 0)
				printk(BIOS_DEBUG, "\n%02x: ", i);

			status = smbus_read_byte(device, i);
			if (status < 0) {
				printk(BIOS_DEBUG, "bad device: %02x\n",
				       -status);
				break;
			}
			printk(BIOS_DEBUG, "%02x ", status);
		}
		device++;
		printk(BIOS_DEBUG, "\n");
	}
}

static void dump_pci_config(int lvl, device_t dev)
{
	int i, j;
	printk(lvl, "   f  e  d  c  b  a  9  8  7  6  5  4  3  2  1  0");
	for (i = 0xf; i >= 0; i--) {
		printk(lvl, "\n%01x", i);
		for (j = 0xf; j >= 0; j--)
			printk(lvl, " %02x", pci_read_config8(dev, (i<<4)|j));
	}
	printk(lvl, "\n");
}

static void dump_mmio(int lvl, u32 start, int sz)
{
	int i, j;
	printk(lvl, "     f  e  d  c  b  a  9  8  7  6  5  4  3  2  1  0");
	for (i = (sz>>4); i >= 0; i--) {
		printk(lvl, "\n%02x ", i);
		for (j = 0xf; j >= 0; j--)
			printk(lvl, " %02x", read8(start+(i<<4)+j));
	}
	printk(lvl, "\n");
}

static void dump_ram_regs(int lvl)
{
	printk(lvl, "\nDumping B0:D0:F0\n");
	dump_pci_config(lvl, PCI_DEV(0,0,0));

	printk(lvl, "\nDumping SMRBASE regs\n");
	dump_mmio(lvl, BAR, 0x298);
}

#endif

static void clear_fifo_pointers(void)
{
	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | 1<<DDRIOMC2_FIFOWPTRCLR);
	udelay(16);
	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2)
				& ~(1<<DDRIOMC2_FIFOWPTRCLR));
	udelay(16);
}

inline int memory_initialized(void)
{
	return pci_read_config32(PCI_DEV(0, 0x00, 0), DRC) &
		(1 << DRC_INIT_COMP);
}

#include "wl_cal3.c"

static inline unsigned tCK_to_10ps(const u8 x)
{
	return 100 * (x>>4) +
	       ((x&0xf) == 0xA ? 25 :
	        (x&0xf) == 0xB ? 33 :
	        (x&0xf) == 0xC ? 66 :
	        (x&0xf) == 0xD ? 75 : 10 * (x&0xf));
}

static inline unsigned tRP_to_10ps(const u8 x)
{
	return 25 * x;
}

#define tRCD_to_10ps tRP_to_10ps

static inline unsigned div_ceil(const unsigned a, const unsigned b)
{
	return (a+b-1)/b;
}

static const int freq_to_int[] = {
	[DDR_800] = 800,
	[DDR_667] = 667,
	[DDR_533] = 533,
	[DDR_400] = 400,
};

static const int ck_period[] = { /* clock period in 10*picoseconds */
	[DDR_800] = 250, /* 2.5ns  */
	[DDR_667] = 300, /* 3ns    */
	[DDR_533] = 375, /* 3.75ns */
	[DDR_400] = 500, /* 5ns    */
};

static const struct ram_timing speed_bins[] = {
	[DDR2_1066E] = {DDR_1066, 6, 6, 6},
	[DDR2_1066F] = {DDR_1066, 7, 7, 7},
	[DDR2_800C] = {DDR_800, 4, 4, 4},
	[DDR2_800D] = {DDR_800, 5, 5, 5},
	[DDR2_800E] = {DDR_800, 6, 6, 6},
	[DDR2_667C] = {DDR_667, 4, 4, 4},
	[DDR2_667D] = {DDR_667, 5, 5, 5},
	[DDR2_533B] = {DDR_533, 3, 3, 3},
	[DDR2_533C] = {DDR_533, 4, 4, 4},
	[DDR2_400B] = {DDR_400, 3, 3, 3},
	[DDR2_400C] = {DDR_400, 4, 4, 4},
};

/* if speed_bin a is supported, speed_bin b is supported if
 * (speed_bin_support[a] & 1 << b) */
static const unsigned int speed_bin_support[] = {
	[DDR2_1066E] =
		1 << DDR2_1066F |
		1 << DDR2_1066E |
		1 << DDR2_800E |
		1 << DDR2_800D |
		1 << DDR2_667D |
		1 << DDR2_667C |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_1066F] =
		1 << DDR2_1066F |
		1 << DDR2_800E |
		1 << DDR2_667D |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_800C] =
		1 << DDR2_800D |
		1 << DDR2_667D |
		1 << DDR2_800C |
		1 << DDR2_667C |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_800D] =
		1 << DDR2_800D |
		1 << DDR2_667D |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_800E] =
		1 << DDR2_800E |
		1 << DDR2_667D |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_667C] =
		1 << DDR2_667D |
		1 << DDR2_667C |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_667D] =
		1 << DDR2_667D |
		1 << DDR2_533C |
		1 << DDR2_400C,
	[DDR2_533B] =
		1 << DDR2_533C |
		1 << DDR2_400C |
		1 << DDR2_533B |
		1 << DDR2_400B,
	[DDR2_533C] =
		1 << DDR2_533C |
		1 << DDR2_400C |
		1 << DDR2_400B,
	[DDR2_400B] =
		1 << DDR2_400C |
		1 << DDR2_400B,
	[DDR2_400C] =
		1 << DDR2_400B,
};

static void print_ram_timing(int level, const struct ram_timing *conf)
{
	printk(level, "DDR2-%d %d-%d-%d",
			freq_to_int[conf->speed],
			conf->CL, conf->tRCD, conf->tRP);
}

static enum ddr_speed get_speed(u8 tCK)
{
	unsigned tCK_ps = tCK_to_10ps(tCK);

	if (tCK_ps <= ck_period[DDR_800])
		return DDR_800;
	if (tCK_ps <= ck_period[DDR_667])
		return DDR_667;
	if (tCK_ps <= ck_period[DDR_533])
		return DDR_533;
	if (tCK_ps <= ck_period[DDR_400])
		return DDR_400;

	die("Minimum clock time too high: %dps\n", tCK_ps);
}

static inline int timing_to_sb(const struct ram_timing *timing)
{
	enum speed_bin sb;

	for (sb = 0; sb < NUM_SPEED_BINS; sb++)
		if (speed_bins[sb].speed == timing->speed &&
				speed_bins[sb].CL == timing->CL)
			return sb;
	print_ram_timing(BIOS_SPEW, timing);
	printk(BIOS_SPEW, " is a non-standard speed bin.\n");
	return -1;
}

static inline int ram_timing_equal(const struct ram_timing *a,
				   const struct ram_timing *b)
{
	return
		a->speed == b->speed &&
		a->CL == b->CL &&
		a->tRCD == b->tRCD &&
		a->tRP == b->tRP;
}

static void get_supported_timings(struct mem_controller *mch)
{
	int i, j, n;
	int sb;
	u8 tRCD, tRP;
	unsigned required_support;

	for (i = 0; i < mch->dimm_num; i++) {
		/* Speed bins explicitly supported in SPD */
		for (j = 0; j < 3 && mch->CL[i][j] != 0; j++) {
			tRCD = div_ceil(tRCD_to_10ps(mch->tRCD[i]),
					tCK_to_10ps(mch->tCK[i][j]));
			tRP = div_ceil(tRP_to_10ps(mch->tRP[i]),
					tCK_to_10ps(mch->tCK[i][j]));

			mch->support[i][mch->n_support[i]++] =
				(struct ram_timing){
					get_speed(mch->tCK[i][j]),
					mch->CL[i][j], tRCD, tRP };
		}

		/* For each speed bin explicitly supported, add other speed
		 * bins required by the standard */
		n = mch->n_support[i];
		required_support = 0;
		for (j = 0; j < n; j++) {
			sb = timing_to_sb(&mch->support[i][j]);
			if (sb < 0)
				continue;

			required_support |= speed_bin_support[sb];
		}

		for (j = 0; j < NUM_SPEED_BINS; j++)
			if (required_support & 1 << j)
				mch->support[i][mch->n_support[i]++] =
					speed_bins[j];

#if CONFIG_DEBUG_RAM_SETUP
		printk(BIOS_DEBUG, "Supported timings on DIMM%d:\n", i);
		for (j = 0; j < mch->n_support[i]; j++) {
			printk(BIOS_DEBUG, " - ");
			print_ram_timing(BIOS_DEBUG, &mch->support[i][j]);
			printk(BIOS_DEBUG, "\n");
		}
#endif
	}
}

#if CONFIG_DEBUG_RAM_SETUP
#define INCOMPATIBLE(conf, reason) do { \
	printk(BIOS_DEBUG, "Cannot choose "); \
	print_ram_timing(BIOS_DEBUG, conf); \
	printk(BIOS_DEBUG, ", " reason "\n"); \
	return 0; } while (0)
#else
#define INCOMPATIBLE(...) do { return 0; } while (1)
#endif

static int supported_by_ep80579(struct mem_controller *mch,
				struct ram_timing *timing)
{
	if (timing->speed > mch->max_speed)
		INCOMPATIBLE(timing, "speed not supported by SKU");
	if (timing->speed == DDR_800 && mch->dimm_num == 2)
		INCOMPATIBLE(timing, "not supported for two DIMMs");
	if (timing->CL <= 3) /* xref2 */
		INCOMPATIBLE(timing, "CL=2 and CL=3 not supported on systems "
				     "with ODT");

/* XXX tAC should maybe be tested somewhere as follows:
	static const int ac_max[] = {
		[DDR_800] = 0x40,
		[DDR_667] = 0x45,
		[DDR_533] = 0x50,
		[DDR_400] = 0x60,
	};

	if (ac_max[conf->speed] < mch->tAC[j][n])
		INCOMPATIBLE_DIMM("data access time from clock "
			       "too high", j);
*/

	return 1;
}

static int compare_speed_bins(struct ram_timing *a, struct ram_timing *b)
{
	if (a->CL == 0)
		return 1;
	if (b->CL == 0)
		return 0;

	if (a->speed < b->speed)
		return 1;
	if (a->speed > b->speed)
		return 0;

	return a->CL + a->tRCD + a->tRP >= b->CL + b->tRCD + b->tRP;
}

static struct ram_timing get_common_timing(
		const struct ram_timing *a,
		const struct ram_timing *b)
{
	return (struct ram_timing){
		a->speed,
		a->CL,
		MAX(a->tRCD, b->tRCD),
		MAX(a->tRP, b->tRP)};
}

static void maybe_select_timing(
		struct mem_controller *mch,
		struct ram_timing t)
{
	if (supported_by_ep80579(mch, &t) &&
			compare_speed_bins(&mch->timing, &t))
		mch->timing = t;
}

static void choose_common_supported_timing(struct mem_controller *mch)
{
	int i, j;

	if (mch->dimm_num == 1)
		for (i = 0; i < mch->n_support[0]; i++)
			maybe_select_timing(mch, mch->support[0][i]);
	else {
		for (i = 0; i < mch->n_support[0]; i++)
			for (j = 0; j < mch->n_support[1]; j++)
				maybe_select_timing(mch,
						get_common_timing(
							&mch->support[0][i],
							&mch->support[1][j]));
	}
}

static void warn_if_non_validated(struct ram_timing *timing)
{
	static const struct ram_timing conf[] = { /* supported configurations,
						     from fastest to slowest */
		{DDR_800, 5, 5, 5},
		{DDR_800, 6, 6, 6},
		{DDR_667, 5, 5, 5},
		{DDR_533, 4, 4, 4},
		{DDR_400, 3, 3, 3}, /* xref2: truxton does not support 3-3-3 */
		{DDR_400, 4, 4, 4},
	};

	int i;
	for (i = 0; i < ARRAY_SIZE(conf); i++)
		if (ram_timing_equal(timing, &conf[i]))
			return;

	printk(BIOS_WARNING, "Using speed ");
	print_ram_timing(BIOS_WARNING, timing);
	printk(BIOS_WARNING, " which is not officially validated for use on "
			"EP80579\n");
}

static void read_timing_info(struct mem_controller *mch)
{
	int i, j, n;
	u8 cas_lat;

	for (i = 0; i < mch->dimm_num; i++) {
		mch->tRP[i] = spd_read_byte(mch->spd[i], SPD_TRP);
		mch->tRCD[i] = spd_read_byte(mch->spd[i], SPD_TRCD);

		cas_lat = spd_read_byte(mch->spd[i], SPD_CAS_LAT);
		for (j = 7, n = 0; j >= 2 && n < 3; j--)
			if (cas_lat & 1 << j)
				mch->CL[i][n++] = j;

		mch->tCK[i][0] = spd_read_byte(mch->spd[i], 9);
		mch->tAC[i][0] = spd_read_byte(mch->spd[i], 10);
		mch->tCK[i][1] = spd_read_byte(mch->spd[i], 23);
		mch->tAC[i][1] = spd_read_byte(mch->spd[i], 24);
		mch->tCK[i][2] = spd_read_byte(mch->spd[i], 25);
		mch->tAC[i][2] = spd_read_byte(mch->spd[i], 26);
	}

#if CONFIG_DEBUG_RAM_SETUP
	printk(BIOS_DEBUG, "Timings read:\n\tCL tCK tAC\n");
	for (i = 0; i < mch->dimm_num; i++) {
		printk(BIOS_DEBUG, "DIMM%d: tRP=%02x tRCD=%02x\n",
				i, mch->tRP[i], mch->tRCD[i]);
		for (j = 0; j < 3; j++)
			printk(BIOS_DEBUG, "\t%d  %02x  %02x\n",
					mch->CL[i][j],
					mch->tCK[i][j],
					mch->tAC[i][j]);
	}
#endif
}

static void select_timing(struct mem_controller *mch)
{
	read_timing_info(mch);
	get_supported_timings(mch);
	choose_common_supported_timing(mch);

	if (mch->timing.CL == 0)
		die("No common supported RAM speed found!");

	printk(BIOS_DEBUG, "Chosen DRAM speed: ");
	print_ram_timing(BIOS_DEBUG, &mch->timing);
	printk(BIOS_DEBUG, "\n");

	warn_if_non_validated(&mch->timing);
}


static void send_ram_command(u8 nr_cs, u32 dcaladdr, u32 dcalcsr)
{
	u8 cs = 0;
	for (cs = 0; cs < nr_cs; cs++) {
		write32(BAR+DCALADDR, dcaladdr);
		write32(BAR+DCALCSR, (dcalcsr |
					(1 << DCALCSR_START) |
					((cs+1) << DCALCSR_CS)));
		while (read32(BAR+DCALCSR) & 1 << DCALCSR_START);
	}
}

static void jedec_init(int nr_cs, struct ram_timing timing, int sodimm)
{
	int i;

	udelay(200);
	send_ram_command(nr_cs, 0, DCALCSR_OPCODE_NOP);

	udelay(1);
	send_ram_command(nr_cs, 0x0400 << 16, DCALCSR_OPCODE_PRECHARGE);

	send_ram_command(nr_cs, DCALADDR_EMR2, DCALCSR_OPCODE_MRS);

	send_ram_command(nr_cs, DCALADDR_EMR3, DCALCSR_OPCODE_MRS);

	u16 emr1 = (sodimm ?
		EMR1_Rtt0_disable << EMR1_Rtt0 |
		EMR1_Rtt1_disable << EMR1_Rtt1
		:
		EMR1_Rtt0_75ohm << EMR1_Rtt0 |
		EMR1_Rtt1_75ohm << EMR1_Rtt1);

	send_ram_command(nr_cs, emr1 << 16 | DCALADDR_EMR1, DCALCSR_OPCODE_MRS);

	static const unsigned wr[] = { /* coherent with DRT0 config (xref1) */
		[DDR_400] = 1,
		[DDR_533] = 2,
		[DDR_667] = 3,
		[DDR_800] = 4,
	};
	u16 mr =
		wr[timing.speed] << MR_WR |		/* xref1 */
		MR_BL_4		<< MR_BURST_LENGTH |	/* for 64-bit bus */
		timing.CL	<< MR_CAS_LAT |		/* CAS latency */
		0		<< MR_PD |		/* Fast exit */
		0		<< MR_TM |		/* Normal mode */
		0		<< MR_BURST_TYPE;	/* Sequential */
	send_ram_command(nr_cs,
			(mr | 1 << MR_DLL_RST) << 16 | DCALADDR_MR,
			DCALCSR_OPCODE_MRS);

	send_ram_command(nr_cs, 0x0400 << 16, DCALCSR_OPCODE_PRECHARGE);

	for (i = 0; i < 6; i++) {
		send_ram_command(nr_cs, 0, DCALCSR_OPCODE_REFRESH);
		udelay(1);
	}

	send_ram_command(nr_cs, mr << 16 | DCALADDR_MR, DCALCSR_OPCODE_MRS);

	send_ram_command(nr_cs,
			(emr1 | EMR1_OCD_cal_default << EMR1_OCD) << 16 |
			DCALADDR_EMR1,
			DCALCSR_OPCODE_MRS);
	send_ram_command(nr_cs,
			(emr1 | EMR1_OCD_cal_exit << EMR1_OCD) << 16 |
			DCALADDR_EMR1,
			DCALCSR_OPCODE_MRS);
}

struct membist_param { int val; const char *desc; };
static void membist(int nr_cs)
{
	int h, i, j, k, pf, fail = 0;

	for(h = 0; h < nr_cs; h++) {
		PRINTK_DEBUG("Beginning MemBIST for rank %d\n", h);

		static const struct membist_param cmd[] = {
#if CONFIG_DEBUG_RAM_SETUP
			{3, "Write followed by read with data comparison" },
#else
			{1, "Write only" },
#endif
		};

		static const struct membist_param pat[] = {
#if CONFIG_DEBUG_RAM_SETUP
			{1, "1111"},
			{2, "1010"},
			{3, "0101"},
			{4, "1100"},
			{5, "0011"},
			{6, "1001"},
			{7, "0110"},
#endif
			{0, "0000 (clear memory)"},
		};

		static const struct membist_param dir[] = {
#if CONFIG_DEBUG_RAM_SETUP
			{1, "decrements"},
#endif
			{0, "increments"},
		};

		for (i = 0; i < ARRAY_SIZE(cmd); i++)
		for (j = 0; j < ARRAY_SIZE(pat); j++)
		for (k = 0; k < ARRAY_SIZE(dir); k++)
		{
			u32 mbcsr = 0;
			mbcsr |= 0 << MBCSR_DTYPE; /* Fixed data pattern */
			mbcsr |= 3 << MBCSR_ATYPE; /* Full address range => not
						      programming MB_START_ADDR
						      nor MB_START_END */
			mbcsr |= (h+1) << MBCSR_CS; /* Select rank */
			mbcsr |= cmd[i].val << MBCSR_CMD;
			mbcsr |= dir[k].val << MBCSR_ADIR;
			mbcsr |= pat[j].val << MBCSR_FX;
			mbcsr |= 1 << MBCSR_HALT;
			mbcsr |= 1 << MBCSR_START; /* start MemBIST execution */

			write32(BAR+MBCSR, mbcsr);

			PRINTK_DEBUG("%s with pattern %s, address %s... ",
					cmd[i].desc, pat[j].desc, dir[k].desc);

			while((mbcsr = read32(BAR+MBCSR)) & 1 << MBCSR_START);

			pf = mbcsr & 1 << MBCSR_PF;

			fail = fail || pf;
			PRINTK_DEBUG("%s\n", pf ? "FAIL" : cmd[i].val != 1 ?
								"PASS" : "");
		}
	}

	if (fail)
		die("Memory test failed.\n");

	clear_fifo_pointers();
}

void sdram_initialize(struct mem_controller *mch)
{
	int i;

#if CONFIG_DEBUG_RAM_SETUP
	dump_spd_registers(mch);
#endif
	/* Do this early */
	pci_write_config8(PCI_DEV(0,0,0), DEVPRES,
			DEVPRES_D1F0 |
			DEVPRES_D2F0 |
			DEVPRES_D3F0 |
			DEVPRES_D4F0 |
			DEVPRES_D10F0);

	/* Activate B0:D0:F1 and B0:D8:F0 */
	pci_write_config8(PCI_DEV(0,0,0), DEVPRES1,
			pci_read_config8(PCI_DEV(0,0,0), DEVPRES1) | 0x22);

	/* Enable BAR defined by SMRBASE */
	pci_write_config8(PCI_DEV(0,0,0), IMCH_TST2,
			pci_read_config8(PCI_DEV(0,0,0), IMCH_TST2) |
			1 << IMCH_TST2_SYSMMREN);

	pci_write_config32(PCI_DEV(0,0,0), SMRBASE, BAR);

	u8 fdhc = pci_read_config8(PCI_DEV(0,0,0), FDHC);
	fdhc &= 0x7f;
	dbg_pci_write_config8(PCI_DEV(0,0,0), FDHC, fdhc);

	u8 pam = pci_read_config8(PCI_DEV(0,0,0), PAM);
	pam &= 0xcc;
	pam |= 0x30;
	dbg_pci_write_config8(PCI_DEV(0,0,0), PAM, pam);

	for (i = 1; i <= 6; i++) {
		pam = pci_read_config8(PCI_DEV(0,0,0), PAM+i);
		pam &= 0xcc;
		pam |= 0x33;
		PRINTK_DEBUG("PAM%d=%02x\n", i, pam);
		pci_write_config8(PCI_DEV(0,0,0), PAM+i, pam);
	}

	/* Max memory speed is limited by FSB speed and FUSESPEED */
	enum fsb_speed fsb_speed;

	fsb_speed = (rdmsr(0xcd).lo & 3) ? FSB_133 : FSB_100;
	PRINTK_DEBUG("%dMHz FSB\n", fsb_speed == FSB_133 ? 133 : 100);
	switch ((pci_read_config8(PCI_DEV(0,0,0), SDRC) >> SDRC_FUSESPEED)
			& 3) {
		case 0: mch->max_speed = (fsb_speed == FSB_133) ? DDR_800 :
									DDR_667;
			break;
		case 1: mch->max_speed = DDR_667; break;
		case 2: mch->max_speed = DDR_533; break;
		case 3: mch->max_speed = DDR_400; break;
	}
	PRINTK_DEBUG("Max DRAM speed: %dMTS\n",
			freq_to_int[mch->max_speed]);

	int nb_registered = 0;
	int sodimm = 0;
	u8 is_double_rank = 0;
	u8 row_num[2];
	u8 bank_num[2];
	u8 col_num[2];
	enum dev_size size[2];
	mch->ecc = 1;

	mch->dimm_num = 2;

	/* SPD checks */
	if (spd_read_byte(mch->spd[0], SPD_MEM_TYPE) != SPD_MEM_TYPE_SDRAM_DDR2)
		die("DIMM0: No DDR2 module found!\n");
	if (spd_read_byte(mch->spd[1], SPD_MEM_TYPE) != SPD_MEM_TYPE_SDRAM_DDR2)
		mch->dimm_num = 1;
	printk(BIOS_DEBUG, "%d DDR2 SDRAM modules found\n", mch->dimm_num);

	select_timing(mch);

	for (i = 0; i < mch->dimm_num; i++) {
		row_num[i] = spd_read_byte(mch->spd[i], SPD_ROW_NUM) & 0x1f;
		if (row_num[i] != 13 && row_num[i] != 14 && row_num[i] != 15)
			die("DIMM%d: Unsupported number of rows %d\n",
					i, row_num[i]);

		col_num[i] = spd_read_byte(mch->spd[i], SPD_COL_NUM) & 0xf;
		if (col_num[i] != 10)
			die("DIMM%d: Unsupported number of cols %d\n",
					i, col_num[i]);

		is_double_rank =
			spd_read_byte(mch->spd[i], SPD_MOD_ATTRIB_RANK) & 3;
		if (is_double_rank) {
			if (is_double_rank != 1)
				die("DIMM%d: Unsupported rank number %d",
						i, is_double_rank + 1);
			if (mch->dimm_num != 1)
				die("DIMM%d: Dual rank only supported with one "
						"module in the first slot.\n",
						i);
		}

		u8 data_width = spd_read_byte(mch->spd[i], SPD_DATA_WIDTH);
		if (data_width < 64)
			die("DIMM%d: Only 64-bit DIMM supported.\n", i);

		u8 dimm_conf_type =
			spd_read_byte(mch->spd[i], SPD_DIMM_CONF_TYPE);
		mch->ecc = mch->ecc && data_width >= 72 &&
				(dimm_conf_type & 3) == SPD_DIMM_CONF_TYPE_ECC;

		u8 pri_width = spd_read_byte(mch->spd[i], SPD_PRI_WIDTH);

		if (pri_width == 16 || pri_width == 18)
			printk(BIOS_WARNING, "DIMM%d: use of x%d module "
					"not validated\n", i, pri_width);

		else if (!(pri_width == 8 || pri_width == 9))
			die("DIMM%d: invalid primary width x%d.\n",
					i, pri_width);

		bank_num[i] = spd_read_byte(mch->spd[i], SPD_BANK_NUM);
		if (bank_num[i] != 4 && bank_num[i] != 8)
			die("DIMM%d: invalid bank number %d.\n",
			    i, bank_num[i]);

		if (bank_num[i] == 8 && row_num[i] == 15)
			size[i] = DEV_2Gb;
		else if (bank_num[i] == 8 && row_num[i] == 14)
			size[i] = DEV_1Gb;
		else if (bank_num[i] == 4 && row_num[i] == 14)
			size[i] = DEV_512Mb;
		else if (bank_num[i] == 4 && row_num[i] == 13)
			size[i] = DEV_256Mb;
		else
			die("DIMM%d: incorrect number of banks/rows (%d/%d)\n",
					i, bank_num[i], row_num[i]);

		u8 dimm_type = spd_read_byte(mch->spd[i], SPD_DIMM_TYPE);
		nb_registered +=
			dimm_type == SPD_DIMM_TYPE_RDIMM ||
			dimm_type == SPD_DIMM_TYPE_mRDIMM ||
			dimm_type == SPD_DIMM_TYPE_SORDIMM;
		if (i == 1 && nb_registered == 1)
			die("Only one of the two DIMMs is registered\n");
		sodimm =
			dimm_type == SPD_DIMM_TYPE_SODIMM ||
			dimm_type == SPD_DIMM_TYPE_SOCDIMM ||
			dimm_type == SPD_DIMM_TYPE_SORDIMM;
	}

	int rank_num = (mch->dimm_num == 2 || is_double_rank) ? 2 : 1;

	PRINTK_DEBUG("Configuring gearing ratio\n");
	u8 sku_id = pci_read_config8(PCI_DEV(0,10,0), SKU_ID);
	int QuickAssist = sku_id & 1;
	printk(BIOS_DEBUG, "SKU %d (%s QuickAssist)\n",
			sku_id, QuickAssist ? "with" : "without");

	if (QuickAssist) {
		dbg_pci_write_config32(PCI_DEV(0,0,0), MAGIC_A8, 0x3000d);
		dbg_pci_write_config32(PCI_DEV(0,0,0), MAGIC_AC, 0x4000f);
	}

	if (mch->timing.speed == DDR_667) {
		if (fsb_speed == FSB_100) {
			dbg_pci_write_config32(PCI_DEV(0,0,0), MAGIC_A0,
								0xFDFFF);
			dbg_pci_write_config32(PCI_DEV(0,0,0), MAGIC_A4,
								0x4001D);
			if (!QuickAssist) {
				dbg_pci_write_config32(PCI_DEV(0,0,0),
							MAGIC_A8, 0x700DF);
				dbg_pci_write_config32(PCI_DEV(0,0,0),
							MAGIC_AC, 0x4001B);
			}
		} else /* 133 MHz */ {
			dbg_pci_write_config32(PCI_DEV(0,0,0), MAGIC_A0,
								0xB0FDF);
			dbg_pci_write_config32(PCI_DEV(0,0,0), MAGIC_A4,
								0x40017);
			if (!QuickAssist) {
				dbg_pci_write_config32(PCI_DEV(0,0,0),
							MAGIC_A8, 0x5001F);
				dbg_pci_write_config32(PCI_DEV(0,0,0),
							MAGIC_AC, 0x4001D);
			}
		}
	}

	PRINTK_DEBUG("Put the VOX in reset mode\n");
	write32(BAR+DDRIOMC0, read32(BAR+DDRIOMC0) |
			1 << DDRIOMC0_DDRVOXCTL1 | 1 << DDRIOMC0_DDRVOXCTL0);

	PRINTK_DEBUG("DQS delay bypass\n");
	write32(BAR+DRAMDLLC, read32(BAR+DRAMDLLC) | 1 << DRAMDLLC_SLVBYP);

	u32 drc = pci_read_config32(PCI_DEV(0,0,0), DRC);
	u8 ds = (mch->timing.speed == DDR_400 ? 2 :
		 mch->timing.speed == DDR_533 ? 0 :
		 mch->timing.speed == DDR_667 ? 7 :
		 /* DDR_800 */      5);

	drc = (drc & ~(0xf << DRC_DS)) | ds << DRC_DS;

	drc |= 1 << DRC_CKEPNM;

	if (rank_num == 1)
		drc |= 1 << DRC_ODT1DIS | 1 << DRC_CS1DIS;
	else
		drc &= ~(1 << DRC_ODT1DIS | 1 << DRC_CS1DIS);

	drc |= 1 << DRC_CKE0;

	if (rank_num == 2)
	       drc |= 1 << DRC_CKE1;
	else
	       drc &= ~(1 << DRC_CKE1);

	PRINTK_DEBUG("DRC=%08x\n", drc);
	pci_write_config32(PCI_DEV(0,0,0), DRC, drc);

	drc = pci_read_config32(PCI_DEV(0,0,0), DRC);
	if ((drc & 0xf) != ds)
		die("Impossible to update the DRC_DS ratio\n");

	for (i = 0; i < 5; i++) {
		u32 wl_cntl = read32(BAR+WL_CNTL0+(i*4));
		wl_cntl &= ~0x00000fff;
		wl_cntl |= mch->timing.speed == DDR_400 ? 0x904 :
			   mch->timing.speed == DDR_533 ? 0x92C :
			   mch->timing.speed == DDR_667 ? 0x94C :
				/* DDR_800 */ 0x918;
		if (i < 4)
			wl_cntl |= 1 << WL_CNTL_WDLL_CLKG;

		PRINTK_DEBUG("WL_CNTL%d=%08x\n", i, wl_cntl);
		write32(BAR+WL_CNTL0+(i*4), wl_cntl);
	}

	u32 wdll_misc = (read32(BAR+WDLL_MISC) & 0xfe80f00f) | 0x1200902;
	PRINTK_DEBUG("WDLL_MISC=%08x\n", wdll_misc);
	write32(BAR+WDLL_MISC, wdll_misc);

	u32 ddriomc1;
	if (nb_registered)
		ddriomc1 = 0x52 << DDRIOMC1_CASLEW | 0x52 << DDRIOMC1_DQSLEW;
	else
		ddriomc1 = 0xFE << DDRIOMC1_CASLEW | 0xF8 << DDRIOMC1_DQSLEW |
			1 << 2 | 3 << DDRIOMC1_FASTSLEW;

	PRINTK_DEBUG("DDRIOMC1=%08x\n", ddriomc1);
	write32(BAR+DDRIOMC1, ddriomc1);

	static const u8 mastcntl_tbl[] = {
		[DDR_400] = 6,
		[DDR_533] = 4,
		[DDR_667] = 4,
		[DDR_800] = 3,
	};

	mch->mastcntl = mastcntl_tbl[mch->timing.speed];
	u32 ddriomc2 = mch->mastcntl << DDRIOMC2_MASTCNTL |
			(nb_registered ? 0x20e : 0x294) << DDRIOMC2_LEGOVERRIDE;

	PRINTK_DEBUG("DDRIOMC2=%08x\n", ddriomc2);
	write32(BAR+DDRIOMC2, ddriomc2);

	PRINTK_DEBUG("Reset DQS delay bypass\n");
	write32(BAR+DRAMDLLC, read32(BAR+DRAMDLLC) & ~(1 << DRAMDLLC_SLVBYP));
	mdelay(50);

	u32 ddriomc0 = ((read32(BAR+DDRIOMC0) & ~0x1e00) |
			(0xB << DDRIOMC0_DQVOXADJ))
		& ~(1 << DDRIOMC0_DDRVOXCTL1);
	PRINTK_DEBUG("DDRIOMC0=%08x\n", ddriomc0);
	write32(BAR+DDRIOMC0, ddriomc0);
	mdelay(50);

	u8 ckdis = 0;
	if (mch->dimm_num == 1)
		ckdis |= (1 << 3) | (1 << 4) | (1 << 5);
	if (nb_registered)
		ckdis |= (1 << 1) | (1 << 2) | (1 << 4) | (1 << 5);
	if (sodimm)
		ckdis |= (1 << 2);
	dbg_pci_write_config8(PCI_DEV(0,0,0), CKDIS, ckdis);

	u32 sdrc =
		2 << SDRC_ODTZENA1 |
		2 << SDRC_ODTZENA |
		1 << SDRC_mu_enable_aioccmd |
		1 << SDRC_mu_enable_bcmd |
		0x30 << SDRC_ASU_CMDQSIZE;

	dbg_pci_write_config32(PCI_DEV(0,0,0), SDRC, sdrc);

	for (i = 0; i < mch->dimm_num; i++) {
		static const u32 dimmtech[] = {
			[DEV_2Gb] = 3 << DRA_DIMMTECH_EVEN |
				3 << DRA_DIMMTECH_ODD,
			[DEV_1Gb] = 4 << DRA_DIMMTECH_EVEN |
				4 << DRA_DIMMTECH_ODD,
			[DEV_512Mb] = 5 << DRA_DIMMTECH_EVEN |
				5 << DRA_DIMMTECH_ODD,
			[DEV_256Mb] = 6 << DRA_DIMMTECH_EVEN |
				6 << DRA_DIMMTECH_ODD,
		};

		u32 dra = dimmtech[size[i]];
		dra |= is_double_rank << 17;
		dra |= (!!nb_registered) << 14;
		dra |= 1 << DRA_DWEVEN;
		dra |= 1 << DRA_DWODD;

		switch(row_num[i]) {
		case 13: dra |= 0 << DRA_NR_EVEN;
			 dra |= 0 << DRA_NR_ODD;
			 break;
		case 14: dra |= 1 << DRA_NR_EVEN;
			 dra |= 1 << DRA_NR_ODD;
			 break;
		case 15: dra |= 2 << DRA_NR_EVEN;
			 dra |= 2 << DRA_NR_ODD;
			 break;
		}

		dra |= 0 << DRA_NC_EVEN;
		dra |= 0 << DRA_NC_ODD;

		PRINTK_DEBUG("DRA%d=%08x\n", i, dra);
		pci_write_config32(PCI_DEV(0,0,0), DRA+(i*4), dra);
	}


	static const u8 drb_tbl[] = {
		[DEV_2Gb] = 0x20,
		[DEV_1Gb] = 0x10,
		[DEV_512Mb] = 0x08,
		[DEV_256Mb] = 0x04,
	};

	u8 drb = drb_tbl[size[0]];
	PRINTK_DEBUG("DRB0=DRB1=%02x\n", drb);
	pci_write_config8(PCI_DEV(0,0,0), DRB0, drb);
	pci_write_config8(PCI_DEV(0,0,0), DRB1, drb);

	if (mch->dimm_num == 2)
		drb += drb_tbl[size[1]];
	else if (is_double_rank)
		drb += drb_tbl[size[0]];
	/* else DRB3 = DRB2 = DRB1 = DRB0 */
	PRINTK_DEBUG("DRB2=DRB3=%02x\n", drb);
	pci_write_config8(PCI_DEV(0,0,0), DRB2, drb);
	pci_write_config8(PCI_DEV(0,0,0), DRB3, drb);

	static const u32 drt0_tbl[] = { /* coherent with MR config (xref1) */
		[DDR_400] = 0x24222000,
		[DDR_533] = 0x24245000,
		[DDR_667] = 0x2436A000,
		[DDR_800] = 0x2438D000
	};

	u32 drt0 = drt0_tbl[mch->timing.speed] |
		(mch->timing.CL - 3) << DRT0_CL |
		(mch->timing.CL - 3) << DRT0_Trp |
		(mch->timing.CL - 3) << DRT0_Trcd;

	PRINTK_DEBUG("DRT0=%08x\n", drt0);
	pci_write_config32(PCI_DEV(0,0,0), DRT0, drt0);

	static const u32 drt1_tbl[] = {
		[DDR_400] = 0x10210000,
		[DDR_533] = 0x40410000,
		[DDR_667] = 0x72618000,
		[DDR_800] = 0xA2918000
	};
	u32 drt1 = drt1_tbl[mch->timing.speed];

	if (nb_registered == 0 &&
			(mch->dimm_num == 2 || mch->timing.speed == DDR_800))
		drt1 |= 1 << DRT1_2Tor1T;

	PRINTK_DEBUG("DRT1=%08x\n", drt1);
	pci_write_config32(PCI_DEV(0,0,0), DRT1, drt1);

	jedec_init(rank_num, mch->timing, sodimm);

	wl_rcven_calibrate(mch);

	u32 dcalcsr;
	write32(BAR+DCALADDR, 0x10008);
	write32(BAR+DCALCSR, 0x88020015);
	while ((dcalcsr = read32(BAR+DCALCSR)) & 1 << DCALCSR_START);
	if (dcalcsr & 1 << DCALCSR_FAIL)
		die("DQS calibration failed.\n");

	clear_fifo_pointers();

	jedec_init(rank_num, mch->timing, sodimm);

	u32 ddr2odtc = (rank_num == 1) ? (sodimm ? 0 : 0x10) : 0x1122;
	dbg_pci_write_config32(PCI_DEV(0,0,0), DDR2ODTC, ddr2odtc);

	u16 tom = drb / 2;
	dbg_pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
	u16 tolm = MIN(tom, 0x18) << 11;
	dbg_pci_write_config16(PCI_DEV(0,0,0), TOLM, tolm);

	static const u32 ddrrefresh[][4] = {
		[DDR_400] = {
			[DEV_256Mb] = 0x005ca0f1,
			[DEV_512Mb] = 0x005ca151,
			[DEV_1Gb] = 0x005ca1a1,
			[DEV_2Gb] = 0x005ca271,
		},
		[DDR_533] = {
			[DEV_256Mb] = 0x007b8141,
			[DEV_512Mb] = 0x007b81c1,
			[DEV_1Gb] = 0x007b8221,
			[DEV_2Gb] = 0x007b8341,
		},
		[DDR_667] = {
			[DEV_256Mb] = 0x00943181,
			[DEV_512Mb] = 0x00943221,
			[DEV_1Gb] = 0x00943291,
			[DEV_2Gb] = 0x009433f1,
		},
		[DDR_800] = {
			[DEV_256Mb] = 0x00b941e1,
			[DEV_512Mb] = 0x00b942a1,
			[DEV_1Gb] = 0x00b94331,
			[DEV_2Gb] = 0x00b944e1,
		},
	};

	enum dev_size highest_rank_sz =
		mch->dimm_num == 1 ? size[0] : MAX(size[0], size[1]);
	dbg_pci_write_config32(PCI_DEV(0,8,0), DDRREFRESH,
			ddrrefresh[mch->timing.speed][highest_rank_sz]);

#if CONFIG_DEBUG_RAM_SETUP
	dump_ram_regs(BIOS_SPEW);
#endif

#if 0 /* Useless because of MemBIST */
#include <lib.h>
	printk(BIOS_DEBUG, "\nSoftware RAM check\n");
	ram_check(0x00100000, 0x00f00000);
	ram_check(0x01000000, tolm << 16);
#endif

	membist(rank_num);

	/* Clear error from previous boots */
	pci_write_config16(PCI_DEV(0,0,0), DRAM_FERR, 0xFFFF);
	pci_write_config16(PCI_DEV(0,0,0), DRAM_NERR, 0xFFFF);
	pci_write_config16(PCI_DEV(0,0,1), DRAM_SEC_R0, 0x0000);
	pci_write_config16(PCI_DEV(0,0,1), DRAM_DED_R0, 0x0000);
	pci_write_config16(PCI_DEV(0,0,1), DRAM_SEC_R1, 0x0000);
	pci_write_config16(PCI_DEV(0,0,1), DRAM_DED_R1, 0x0000);
	pci_write_config16(PCI_DEV(0,0,1), RANKTHREX, 0xFFFF);

	pci_write_config32(PCI_DEV(0,0,0), DRC,
			pci_read_config32(PCI_DEV(0, 0, 0), DRC) |
			1 << DRC_INIT_COMP |
			(!!mch->ecc) << DRC_ECC);

	clear_fifo_pointers();
}