============================================================ 0h NOTESPAD table_ref 16-221 offset 0h reg_name NOTESPAD recurring None reg_base_name NOTESPAD title_desc Note (Sticky) Pad for BIOS Support Register description None view PCI bar SMRBASE offset_start 0h offset_end 1h power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym BSR description BIOS Sticky Register [STICKY]: This register is used by BIOS. It is sticky through reset. sticky Y reset 0000000000000000b [ 0000h ] access RW ============================================================ 2h NOTEPAD table_ref 16-222 offset 2h reg_name NOTEPAD recurring None reg_base_name NOTEPAD title_desc Note Pad for BIOS Support Register description None view PCI bar SMRBASE offset_start 2h offset_end 3h power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym BNSR description BIOS Register: This register is used by BIOS. sticky N reset 0000000000000000b [ 0000h ] access RW ============================================================ 40h DCALCSR table_ref 16-223 offset 40h reg_name DCALCSR recurring None reg_base_name DCALCSR title_desc DCAL Control and Status Register description DCALCSR - DCAL Control and Status Register view PCI bar SMRBASE offset_start 40h offset_end 43h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31 acronym START description Start Operation When set to 1 by software, the operation selected by the DCALCSR.OPCODE is initiated. Hardware clears this bit when the operation is complete. sticky N reset [ 0b ] 0h access RWS ---------------- range 30-28 acronym FAIL description Completion Status 1xx = Fail, 0xx = Pass Note: Best practice is to rely on MemBIST following calibration to confirm a reliable DRAM interface. sticky N reset [ 000b ] 0h access RW ---------------- range 27 acronym BASPAT description Basic Data Pattern Enable: This controls which data pattern is used for the DQS Delay calibration. Setting this field enables the use of the basic data pattern selected by the DCALCSR.PATTERN bits. When cleared, the extended data pattern specified in the DDQSCVDP and DDQSCADP registers is used. Note: extended data pattern mode is not to be used in 2T configurations. sticky N reset [ 0b ] 0h access RW ---------------- range 26 acronym RSTREGSS description Reset Registers in Single Step Mode: Reset DCALDATA CSR in single step calibration mode. This bit should be set during the first step of a single step calibration. It will enable hardware to clear all registers and status bits during the calibration step the same way hardware does on the first step of an automatic "all passes" calibration. sticky N reset [ 0b ] 0h access RW ---------------- range 25-24 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 23 acronym SGLSTP description Single Step Calibration Operation: Applies only to Receive enable and DQS cal. "1" = Single step - a single step of the algorithm selected by the DCALCSR.OPCODE is run by hardware. No data analysis is run."0" = All passes - all steps of the algorithm selected by the DACLCSR.OPCODE is run by hardware including data analysis. sticky N reset [ 0b ] 0h access RW ---------------- range 22-21 acronym CS description Chip select: This field corresponds to the chip select outputs: CS[1:0]. This field Applies to NOP, Refresh, Precharge all, and MRS/EMRS commands. It also applies to Receive Enable, and DQS Delay cal in single step mode. 01: select Rank 0 10: select Rank 1 00: Reserved 11: ReservedNote:Set CS to 01 for Self Refresh Entry. Hardware will automatically detect presence of a second rank/DIMM and sequence Self Refresh Entry via both chip selects if necessary. sticky N reset [ 00b ] 0h access RW ---------------- range 20-19 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 18-16 acronym PAT description Data pattern: for DQS cal. This sets the burst length 4 pattern for a nibble of data. The pattern is repeated for BL8. This pattern is replicated on all nibbles of the data bus. "000" = F > 0 > F > 0"001" = 0 > F > 0 > F"010" = A > 5 > A > 5"011" = 5 > A > 5 > A"100" = C > 3 > C > 3"101" = 3 > C > 3 > C"110" = 9 > 6 > 9 > 6"111" = 6 > 9 > 6 > 9 sticky N reset [ 000b ] 0h access RW ---------------- range 15 acronym DARWPR description Disable FIFO reset: in single pass mode. Applies only to Receiver enable and DQS cal. When set to 1, this bit inhibits the core to DDR cluster reset signal generated during the calibration modes. This prevents the DDR cluster synchronizer FIFO write pointer and data latches from being reset so that they can be read out of the cluster using the error monitor function. The reset signal can only be disabled in single step mode. When the DCALCSR.SGLSTP bit is set to 0, the DARWPR bit has no effect. sticky N reset [ 0b ] 0h access RW ---------------- range 14-4 acronym OPMODS description Operation modifiers: See Table 16-224, Table 16-224, Table 16-227, and Table 16-235 for details sticky N reset 00000000000b [ 000h ] access RW ---------------- range 3-0 acronym OPCODE description OPCODE: "0000" = NOP"0001" = Refresh (SeeTable 16-226) "0010" = Pre-Charge"0011" = MRS/EMRS "0100" = Self-Refresh-Exit (SeeTable 16-226) "0101" = Automatic DQS Delay Calibration"0110"= Reserved"0111" = DLL BIST "1100" = Automatic Receive Enable Calibration "1101" = Self-Refresh Entry (SeeTable 16-226) "1110" = Error Monitor/Read DDRIO FIFO "1111" = ZQ Calibration All other settings are reserved sticky N reset [ 0000b ] 0h access RW ============================================================ 44h DCALADDR table_ref 16-229 offset 44h reg_name DCALADDR recurring None reg_base_name DCALADDR title_desc DCAL Address Register description DCALADDR - DCAL Address Register view PCI bar SMRBASE offset_start 44h offset_end 47h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DCALADDR description DCAL Address and Other Information based on DCALCSR.OPCODE. See Table 16-230. sticky N reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 48h DCALDATA[0-71] table_ref 16-231 offset 48h reg_name DCALDATA[0-71] recurring 72 reg_base_name DCALDATA title_desc DRAM Calibration Data Register description DCALData - DRAM Calibration Data Registers view PCI bar SMRBASE offset_start 48h at 1h offset_end 48h at 1h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-0 acronym DCALDATA description DCAL Data and other information based on DCALCSR.OPCODE. See Table 16-232. sticky N reset 00000000b [ 00h ] access RW ============================================================ 94h RCVENAC table_ref 16-233 offset 94h reg_name RCVENAC recurring None reg_base_name RCVENAC title_desc Receiver Enable Algorithm Control Register description RCVENAC: Receiver Enable Algorithm Control view PCI bar SMRBASE offset_start 94h offset_end 96h power_well Core size 24 default 180810h bus_device_function 0:0:0 ---------------- range 23-16 acronym PWIDTH description Minimum preamble width limit, used to detect if a low pulse in a DQS waveform is wide enough to be a valid preamble. The default corresponds to 3/4 of a DRAM clock cycle sticky Y reset 00011000b [ 18h ] access RW ---------------- range 15-14 acronym Reserved description Reserved sticky reset [ 00b ] 0h access RO ---------------- range 13-8 acronym HWIDTH description Minimum high pulse width limit, used to detect if a high pulse in a DQS waveform is wide enough to indicate a strobe is toggling in a valid manner. The default corresponds to 1/4 of a DRAM clock cycle. sticky Y reset 001000b [ 08h ] access RW ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access RO ---------------- range 5-0 acronym POFFSET description Preamble center offset from first rising edge, used to position the DQS receiver enable relative to the preamble edge location recorded in the DCALDATA registers. The default value corresponds to 1/2 of a DRAM clock cycle. sticky Y reset 010000b [ 10h ] access RW ============================================================ 98h DSRETC table_ref 16-234 offset 98h reg_name DSRETC recurring None reg_base_name DSRETC title_desc DRAM Self-Refresh (SR) Extended Timing and Control Register description DSRETC: DRAM Self-Refresh (SR) Extended Timing and Control Register view PCI bar SMRBASE offset_start 98h offset_end 9bh power_well Core size 32 default 5c141400h bus_device_function 0:0:0 ---------------- range 31-24 acronym TXSNR description Exit self-refresh to non-read command timing. Number of Controller cycles for which accesses to the DIMMs need to be blocked by memory controller. sticky Y reset [ 01011100b ] 5ch access RW ---------------- range 23-16 acronym DRSRENT description Dual rank self-refresh (SR) entry and exit timing - stagger of self refresh commands between ranks. Staggering of the SR commands result is in the power intensive refresh operations to be staggered between the 2 ranks. sticky Y reset [ 00010100b ] 14h access RW ---------------- range 15-8 acronym DRARTIM description Dual rank auto-refresh timing - stagger of commands between ranks prior to self-refresh entry. sticky Y reset [ 00010100b ] 14h access RW ---------------- range 7-1 acronym Reserved description Reserved sticky N reset [ 0000000b ] 00h access RO ---------------- range 0 acronym ENSREXIT description Enable Self-refresh (SR) exit state machine. This bit needs to be set by BIOS upon power-up from an S3 event. sticky N reset [ 0b ] 0h access RW ============================================================ 9ch DQSFAIL1 table_ref 16-235 offset 9ch reg_name DQSFAIL1 recurring None reg_base_name DQSFAIL1 title_desc DQS Failure Configuration Register 1 description DQSFAIL1: DQS Failure Configuration Register view PCI bar SMRBASE offset_start 9ch offset_end 9ch power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3 acronym Reserved_R1DQS17 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 2 acronym R1DQS08 description Rank 1 DQS08 sticky Y reset [ 0b ] 0h access RW ---------------- range 1 acronym Reserved_R1DQS16 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 0 acronym R1DQS07 description Rank 1 DQS07 sticky Y reset [ 0b ] 0h access RW ============================================================ a0h DQSFAIL0 table_ref 16-236 offset a0h reg_name DQSFAIL0 recurring None reg_base_name DQSFAIL0 title_desc DQS Failure Configuration Register 0 description DQSFAIL0: DQS Failure Configuration Register view PCI bar SMRBASE offset_start a0h offset_end a3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31 acronym Reserved_R1DQS15 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 30 acronym R1DQS06 description Rank 1 DQS06 sticky Y reset [ 0b ] 0h access RW ---------------- range 29 acronym Reserved_R1DQS14 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 28 acronym R1DQS05 description Rank 1 DQS05 sticky Y reset [ 0b ] 0h access RW ---------------- range 27 acronym Reserved_R1DQS13 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 26 acronym R1DQS04 description Rank 1 DQS04 sticky Y reset [ 0b ] 0h access RW ---------------- range 25 acronym Reserved_R1DQS12 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 24 acronym R1DQS03 description Rank 1 DQS03 sticky Y reset [ 0b ] 0h access RW ---------------- range 23 acronym Reserved_R1DQS11 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 22 acronym R1DQS02 description Rank 1 DQS02 sticky Y reset [ 0b ] 0h access RW ---------------- range 21 acronym Reserved_R1DQS10 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 20 acronym R1DQS01 description Rank 1 DQS01 sticky Y reset [ 0b ] 0h access RW ---------------- range 19 acronym Reserved_R1DQS09 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 18 acronym R1DQS00 description Rank 1 DQS00 sticky Y reset [ 0b ] 0h access RW ---------------- range 17 acronym Reserved_R0DQS17 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 16 acronym R0DQS08 description Rank 0 DQS08 sticky Y reset [ 0b ] 0h access RW ---------------- range 15 acronym Reserved_R0DQS16 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 14 acronym R0DQS07 description Rank 0 DQS07 sticky Y reset [ 0b ] 0h access RW ---------------- range 13 acronym Reserved_R0DQS15 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 12 acronym R0DQS06 description Rank 0 DQS06 sticky Y reset [ 0b ] 0h access RW ---------------- range 11 acronym Reserved_R0DQS14 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 10 acronym R0DQS05 description Rank 0 DQS05 sticky Y reset [ 0b ] 0h access RW ---------------- range 9 acronym Reserved_R0DQS13 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 8 acronym R0DQS04 description Rank 0 DQS04 sticky Y reset [ 0b ] 0h access RW ---------------- range 7 acronym Reserved_R0DQS12 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 6 acronym R0DQS03 description Rank 0 DQS03 sticky Y reset [ 0b ] 0h access RW ---------------- range 5 acronym Reserved_R0DQS11 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 4 acronym R0DQS02 description Rank 0 DQS02 sticky Y reset [ 0b ] 0h access RW ---------------- range 3 acronym Reserved_R0DQS10 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 2 acronym R0DQS01 description Rank 0 DQS01 sticky Y reset [ 0b ] 0h access RW ---------------- range 1 acronym Reserved_R0DQS09 description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 0 acronym R0DQS00 description Rank 0 DQS00 sticky Y reset [ 0b ] 0h access RW ============================================================ a4h DRRTC00 table_ref 16-237 offset a4h reg_name DRRTC00 recurring None reg_base_name DRRTC00 title_desc Receive Enable Reference Output Timing Control Register description DRRTC00: Receive Enable Reference Output Timing Control Register view PCI bar SMRBASE offset_start a4h offset_end a7h power_well Core size 32 default 06060606h bus_device_function 0:0:0 ---------------- range 31-24 acronym RCVEN03 description Receiver enable delay for DQS3 sticky Y reset 00000110b [ 06h ] access RW ---------------- range 23-16 acronym RCVEN02 description Receiver enable delay for DQS2 sticky Y reset 00000110b [ 06h ] access RW ---------------- range 15-8 acronym RCVEN01 description Receiver enable delay for DQS1 sticky Y reset 00000110b [ 06h ] access RW ---------------- range 7-0 acronym RCVEN00 description Receiver enable delay for DQS0 sticky Y reset 00000110b [ 06h ] access RW ============================================================ a8h DRRTC01 table_ref 16-238 offset a8h reg_name DRRTC01 recurring None reg_base_name DRRTC01 title_desc Receive Enable Reference Output Timing Control Register description DRRTC01: Receive Enable Reference Output Timing Control Register view PCI bar SMRBASE offset_start a8h offset_end abh power_well Core size 32 default 06060606h bus_device_function 0:0:0 ---------------- range 31-24 acronym RCVEN07 description Receiver enable delay for DQS7 sticky Y reset 00000110b [ 06h ] access RW ---------------- range 23-16 acronym RCVEN06 description Receiver enable delay for DQS6 sticky Y reset 00000110b [ 06h ] access RW ---------------- range 15-8 acronym RCVEN05 description Receiver enable delay for DQS5 sticky Y reset 00000110b [ 06h ] access RW ---------------- range 7-0 acronym RCVEN04 description Receiver enable delay for DQS4 sticky Y reset 00000110b [ 06h ] access RW ============================================================ c4h DRRTC02 table_ref 16-239 offset c4h reg_name DRRTC02 recurring None reg_base_name DRRTC02 title_desc Receive Enable Reference Output Timing Control Register description DRRTC02: Receive Enable Reference Output Timing Control Register view PCI bar SMRBASE offset_start c4h offset_end c4h power_well Core size 8 default 06h bus_device_function 0:0:0 ---------------- range 7-0 acronym RCVEN08 description Receiver enable delay for DQS8 sticky Y reset 00000110b [ 06h ] access RW ============================================================ b4h DQSOFCS00 table_ref 16-240 offset b4h reg_name DQSOFCS00 recurring None reg_base_name DQSOFCS00 title_desc DQS Calibration Register description DQSOFCS00: DQS Calibration Register view PCI bar SMRBASE offset_start b4h offset_end b7h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-28 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 27-24 acronym DQS03 description Rank 0 DQS03: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 23-20 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 19-16 acronym DQS02 description Rank 0 DQS02: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 15-12 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 11-8 acronym DQS01 description Rank 0 DQS01: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS00 description Rank 0 DQS00: Fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ b8h DQSOFCS01 table_ref 16-241 offset b8h reg_name DQSOFCS01 recurring None reg_base_name DQSOFCS01 title_desc DQS Calibration Register description DQSOFCS01: DQS Calibration Register view PCI bar SMRBASE offset_start b8h offset_end bbh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-28 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 27-24 acronym DQS07 description Rank 0 DQS07: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 23-20 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 19-16 acronym DQS06 description Rank 0 DQS06: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 15-12 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 11-8 acronym DQS05 description Rank 0 DQS05: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS04 description Rank 0 DQS04: Fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ c6h DQSOFCS02 table_ref 16-242 offset c6h reg_name DQSOFCS02 recurring None reg_base_name DQSOFCS02 title_desc DQS Calibration Register description DQSOFCS02: DQS Calibration Register view PCI bar SMRBASE offset_start c6h offset_end c6h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS08 description Rank 0 DQS08: Fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ bch DQSOFCS10 table_ref 16-243 offset bch reg_name DQSOFCS10 recurring None reg_base_name DQSOFCS10 title_desc DQS Calibration Register description DQSOFCS10: DQS Calibration Register view PCI bar SMRBASE offset_start bch offset_end bfh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-28 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 27-24 acronym DQS03 description Rank 1 DQS03: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 23-20 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 19-16 acronym DQS02 description Rank 1 DQS02: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 15-12 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 11-8 acronym DQS01 description Rank 1 DQS01: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS00 description Rank 1 DQS00: Fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ c0h DQSOFCS11 table_ref 16-244 offset c0h reg_name DQSOFCS11 recurring None reg_base_name DQSOFCS11 title_desc DQS Calibration Register description DQSOFCS11: DQS Calibration Register view PCI bar SMRBASE offset_start c0h offset_end c3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-28 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 27-24 acronym DQS07 description Rank 1 DQS07: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 23-20 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 19-16 acronym DQS06 description Rank 1 DQS06: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 15-12 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 11-8 acronym DQS05 description Rank 1 DQS05: Fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS04 description Rank 1 DQS04: Fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ c7h DQSOFCS12 table_ref 16-245 offset c7h reg_name DQSOFCS12 recurring None reg_base_name DQSOFCS12 title_desc DQS Calibration Register description DQSOFCS12: DQS Calibration Register view PCI bar SMRBASE offset_start c7h offset_end c7h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-4 acronym Reserved description Reserved sticky N reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS08 description Rank 1 DQS08: Fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ cch WPTRTC0 table_ref 16-246 offset cch reg_name WPTRTC0 recurring None reg_base_name WPTRTC0 title_desc Write Pointer Timing Control Register description WPTRTC0: Write pointer timing control view PCI bar SMRBASE offset_start cch offset_end cfh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-28 acronym DQS07 description DQS7 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 27-24 acronym DQS06 description DQS6 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 23-20 acronym DQS05 description DQS5 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 19-16 acronym DQS04 description DQS4 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 15-12 acronym DQS03 description DQS3 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 11-8 acronym DQS02 description DQS2 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 7-4 acronym DQS01 description DQS1 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ---------------- range 3-0 acronym DQS00 description DQS0 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ d0h WPTRTC1 table_ref 16-247 offset d0h reg_name WPTRTC1 recurring None reg_base_name WPTRTC1 title_desc Write Pointer Timing Control 1 Register description WPTRTC1: Write pointer timing control view PCI bar SMRBASE offset_start d0h offset_end d0h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-4 acronym Reserved description Reserved sticky reset 0000b [ 0h ] access RO ---------------- range 3-0 acronym DQS08 description DQS8 write pointer fine delay sticky Y reset 0000b [ 0h ] access RW ============================================================ d4h DDQSCVDP0 table_ref 16-248 offset d4h reg_name DDQSCVDP0 recurring None reg_base_name DDQSCVDP0 title_desc DQS Delay Calibration Victim Pattern 0 Register description DDQSCVDP0: DQS Delay Cal Pattern view PCI bar SMRBASE offset_start d4h offset_end d7h power_well Core size 32 default aaaa0a05h bus_device_function 0:0:0 ---------------- range 31-0 acronym VP0 description Victim pattern 0 sticky reset 10101010101010100000101000000101b [ aaaa0a05h ] access RW ============================================================ d8h DDQSCVDP1 table_ref 16-249 offset d8h reg_name DDQSCVDP1 recurring None reg_base_name DDQSCVDP1 title_desc DQS Delay Calibration Victim Pattern 1 Register description DDQSCVDP1: DQS Delay Cal Pattern view PCI bar SMRBASE offset_start d8h offset_end dbh power_well Core size 32 default 5b339c5dh bus_device_function 0:0:0 ---------------- range 31-0 acronym VP1 description Victim pattern 1 sticky reset 01011011001100111001110001011101b [ 5b339c5dh ] access RW ============================================================ dch DDQSCADP0 table_ref 16-250 offset dch reg_name DDQSCADP0 recurring None reg_base_name DDQSCADP0 title_desc DQS Delay Calibration Aggressor Pattern 0 Register description DDQSCADP0: DQS Delay Cal Pattern view PCI bar SMRBASE offset_start dch offset_end dfh power_well Core size 32 default aaabffffh bus_device_function 0:0:0 ---------------- range 31-0 acronym AP0 description Aggressor pattern 0 sticky reset 10101010101010111111111111111111b [ aaabffffh ] access RW ============================================================ e0h DDQSCADP1 table_ref 16-251 offset e0h reg_name DDQSCADP1 recurring None reg_base_name DDQSCADP1 title_desc DQS Delay Calibration Aggressor Pattern 1 Register description DDQSCADP1: DQS Delay Cal Pattern view PCI bar SMRBASE offset_start e0h offset_end e3h power_well Core size 32 default db339ce1h bus_device_function 0:0:0 ---------------- range 31-0 acronym AP1 description Aggressor pattern 1 sticky reset 11011011001100111001110011100001b [ db339ce1h ] access RW ============================================================ f0h DIOMON table_ref 16-252 offset f0h reg_name DIOMON recurring None reg_base_name DIOMON title_desc DDR I/O Monitor Register description DIOMON: DDR I/O Monitor view PCI bar SMRBASE offset_start f0h offset_end f3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-25 acronym Reserved description Reserved sticky N reset [ 0000000b ] 00h access RO ---------------- range 24 acronym DSAMP description Causes the analog to digital converter to sample the analog input selected by biasssel sticky Y reset [ 0b ] 0h access RW ---------------- range 23-16 acronym VRESULT description A/D converter output of DDR I/O sticky Y reset [ 00000000b ] 00h access RO ---------------- range 15 acronym ENABLE description Enable A/D converter for the DDR IO Bias logic. Also enables updates to the following fields of this CSR: VRESULT, DQLEGSELOUT, DIOPWR, CALEGSELOUT sticky N reset [ 0b ] 0h access RW ---------------- range 14-11 acronym BIASSEL description A/D converter input selection sticky Y reset [ 0000b ] 0h access RW ---------------- range 10-7 acronym DQLEGSELOUT description DQ legsel output of DDR I/O. Sets the driver strength for DQ IO buffers. sticky Y reset [ 0000b ] 0h access RO ---------------- range 6 acronym DIOPWR description Nopwr = 0 if Vccddr is off OR in burnin mode. During normal operation it's set to 1. sticky Y reset [ 0b ] 0h access RO ---------------- range 5-4 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 3-0 acronym CALEGSELOUT description cmd/addr legsel output of DDR I/O Sets the driver strength for cmd/addr IO buffers. sticky Y reset [ 0000b ] 0h access RO ============================================================ f8h DRAMISCTL table_ref 16-253 offset f8h reg_name DRAMISCTL recurring None reg_base_name DRAMISCTL title_desc Miscellaneous DRAM DDR Cluster Control Register description DRAMISCTL: Miscellaneous DRAM DDR Cluster Control Register view PCI bar SMRBASE offset_start f8h offset_end fbh power_well Core size 32 default 00001011h bus_device_function 0:0:0 ---------------- range 31-13 acronym Reserved description Reserved sticky N reset [ 0000000000000000000b ] 00000h access RO ---------------- range 12 acronym Reserved description Reserved sticky Y reset [ 1b ] 1h access RW ---------------- range 11 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RW ---------------- range 10-8 acronym Reserved_RW description Reserved for future use. These bits are RW but SW should not change the default reset value of these bits. sticky N reset [ 000b ] 0h access RW ---------------- range 7-0 acronym VREFSEL description Vref selection: Adjustable VREF voltage at receivers. The threshold voltage at receiver can be raised or lowered to allow the noise margin on the data from memory be skewed. Vref is estimated with the following equation Vref = (SQU * VCCDDR + (SQD - SQU) * 0.45) / (SQU + SQD) + VOFF where, SQU = SQRT(4*VREFSEL<7> + 2*VREFSEL<6> + VREFSEL<5> + 8*VREFSEL<4>) SQD = SQRT(4*VREFSEL<3> + 2*VREFSEL<2> + VREFSEL<1> + 8*VREFSEL<0>) VOFF = offset, varying for each chip, nominal value is 0 but can be up to +/- 0.1V Examples with VCCDDR=1.8V and VOFF=0 .VREFSEL. Vref (V) 00010001 0.9 00010011 0.887 00010101 0.875 00011001 0.855 11101001 0.840 11001001 0.823 10001001 0.779 00110001 0.913 01010001 0.925 10010001 0.945 10011110 0.960 10011100 0.977 10011000 1.021 sticky Y reset 00010001b [ 11h ] access RW ============================================================ c8h DRAMDLLC table_ref 16-254 offset c8h reg_name DRAMDLLC recurring None reg_base_name DRAMDLLC title_desc DDR I/O DLL Control Register description DRAMDLLC: DDR I/O DLL Control view PCI bar SMRBASE offset_start c8h offset_end cah power_well Core size 24 default 0db6c0h bus_device_function 0:0:0 ---------------- range 23-22 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 21 acronym SLVBYP description DQS delay bypass sticky Y reset [ 0b ] 0h access RW ---------------- range 20-18 acronym SLVLEN4 description dqs 8 coarse DQS delay sticky Y reset [ 011b ] 3h access RW ---------------- range 17-15 acronym SLVLEN3 description dqs 7 & 6 coarse DQS delay sticky Y reset [ 011b ] 3h access RW ---------------- range 14-12 acronym SLVLEN2 description dqs 5 & 4 coarse DQS delay sticky Y reset [ 011b ] 3h access RW ---------------- range 11-9 acronym SLVLEN1 description dqs 3 & 2 coarse DQS delay sticky Y reset [ 011b ] 3h access RW ---------------- range 8-6 acronym SLVLEN0 description dqs1 & 0 coarse DQS delay sticky Y reset [ 011b ] 3h access RW ---------------- range 5-0 acronym Reserved description Reserved sticky N reset [ 000000b ] 00h access RO ============================================================ e8h FIVESREG table_ref 16-255 offset e8h reg_name FIVESREG recurring None reg_base_name FIVESREG title_desc Fixed 5s Pattern Register description FIVESREG: Fixed 5s Pattern view PCI bar SMRBASE offset_start e8h offset_end ebh power_well Core size 32 default 55555555h bus_device_function 0:0:0 ---------------- range 31-0 acronym FIVES description Hardwired to 5s for read-return sticky N reset 01010101010101010101010101010101b [ 55555555h ] access RO ============================================================ ech AAAAREG table_ref 16-256 offset ech reg_name AAAAREG recurring None reg_base_name AAAAREG title_desc Fixed A Pattern Register description AAAAREG: Fixed A Pattern view PCI bar SMRBASE offset_start ech offset_end efh power_well Core size 32 default aaaaaaaah bus_device_function 0:0:0 ---------------- range 31-0 acronym AAAA description Hardwired to As for read-return sticky N reset 10101010101010101010101010101010b [ aaaaaaaah ] access RO ============================================================ 140h MBCSR table_ref 16-257 offset 140h reg_name MBCSR recurring None reg_base_name MBCSR title_desc MemBIST Control Register description MBCSR: Top level control register for DDR MemBIST. view PCI bar SMRBASE offset_start 140h offset_end 143h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31 acronym START description Start operation: 1 => Set this bit to begin MemBIST execution. 0 => Hardware will clear this bit when MemBIST execution is completed. sticky N reset [ 0b ] 0h access RWS ---------------- range 30 acronym PF description Fail/Pass indicator: Write to 0 when start MemBIST. Hardware will set to 1 when a failure is detected. 0 => Pass 1 => Fail sticky N reset [ 0b ] 0h access RW ---------------- range 29 acronym HALT description Halt on Error: 0 => Operation will not halt due to a detected error. 1 => Operation will halt after read-compare data error is detected. MemBIST will complete the current transaction before halting. This may result in multiple errors being logged. sticky N reset [ 0b ] 0h access RW ---------------- range 28 acronym ABORT description MemBIST test abort. When test abort bit is set, MBCSR bit 31 (Start operation, RWS) needs to be set to "0" at the same time to avoid restarting MemBIST. 0 => Normal operation. 1 => Need to abort the test during MemBIST operation. If there is any following Membist test after the abort test, bit [28] needs to be cleared. The Write to set MBCSR.abort must occur at least tRFC after the Write to set MBCSR.start. Otherwise subsequent MemBIST operations may fail. sticky N reset [ 0b ] 0h access RW ---------------- range 27 acronym SPARE description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 26-24 acronym ALGO description 000b: only support setting sticky N reset [ 000b ] 0h access RW ---------------- range 23-22 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 21-20 acronym CS description Chip Select[1:0] selection in MemBIST mode 01: select Rank 0 10: select Rank 1 00: Reserved 11: Reserved sticky N reset [ 00b ] 0h access RW ---------------- range 19 acronym INV description 0b: only supported setting sticky N reset 0b [ 0h ] access RW ---------------- range 18-16 acronym FX description FIXED: Fixed data pattern selection for MemBIST operation 000 => 0 001 => F 010 => A 011 => 5 100 => C 101 => 3 110 => 9 111 => 6 sticky N reset [ 000b ] 0h access RW ---------------- range 15 acronym EN288 description 0b: only supported setting sticky N reset [ 0b ] 0h access RW ---------------- range 14 acronym MBDATA description MBDATA: Selects use of MBDATA for error log field for LFSR, Circular Shift and user defined data modes. This field has no effect on fixed data patterns. 0 => use MBDATA0/1/2/3/8 for failure data bit location accumulator. 1 => use MBDATA0/1/2/3/8 to log 5 failure addresses. sticky N reset [ 0b ] 0h access RW ---------------- range 13 acronym ABAR description 0: only supported setting sticky N reset [ 0b ] 0h access RW ---------------- range 12 acronym ADIR description ADIR: Address decode direction 0 => Address increments 1 => Address decrements sticky N reset [ 0b ] 0h access RW ---------------- range 11-10 acronym FAST description FAST Address sequencing 00: only supported setting sticky N reset [ 00b ] 0h access RW ---------------- range 9-8 acronym DTYPE description Data type selection: 00 => Fixed data pattern, selected by MBCSR bits 18:16 01 => 144 bits user defined data 10 => Circular shift data based on Seed in MBLFSRSED 11 => LFSR data, seeded from 32 bit LFSR seed register. Note: Circular shift data and LFSR data type should not be used for single address operation (ATYPE = 01). Note: Circular shift data and LFSR data type only for 72-bit mode sticky N reset [ 00b ] 0h access RW ---------------- range 7-6 acronym ATYPE description Address type: 00 => Reserved 01 => Single physical address operation, contained in MBADDR row/column/bank. 10 => start/end physical address range defined in MB_START_ADDR & MB_END_ADDR registers. 11 => full address range of the DIMM as defined in DRA/DRB registers which specifies the number of banks, rows, and columns. ? sticky N reset [ 00b ] 0h access RW ---------------- range 5-4 acronym CMD description Command execution: 00 => Read only without data comparison 01 => Write only 10 => Read with data comparison 11 => Write followed by Read with data comparison sticky N reset [ 00b ] 0h access RW ---------------- range 3-0 acronym Reserved description Reserved sticky N reset [ 0000b ] 0h access RO ============================================================ 144h MBADDR table_ref 16-258 offset 144h reg_name MBADDR recurring None reg_base_name MBADDR title_desc Memory Test Address Register description MBADDR: Memory Test Address view PCI bar SMRBASE offset_start 144h offset_end 147h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-16 acronym ROW description Row Address 15:0 sticky Y reset 0000000000000000b [ 0000h ] access RW ---------------- range 15 acronym SPARE description Reserved. Must write as '0' sticky Y reset [ 0b ] 0h access RW ---------------- range 14-3 acronym COL description Column Address BL8[14:3] <==> DRAM Column Address 15:11,9:3BL4[14:3] <==> DRAM Column Address 14:11,9:2 sticky Y reset 000000000000b [ 000h ] access RW ---------------- range 2-0 acronym BA description Bank Address 2:0 sticky Y reset [ 000b ] 0h access RW ============================================================ 148h MBDATA[0:9] table_ref 16-259 offset 148h reg_name MBDATA[0:9] recurring 10 reg_base_name MBDATA title_desc Memory Test Data Register description MBADDR[0:9]: Memory Test Data view PCI bar SMRBASE offset_start 148h at 4h offset_end 14ch at 4h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym MBDATA description Usage varies by mode, refer to table below for details sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 19ch MB_START_ADDR table_ref 16-263 offset 19ch reg_name MB_START_ADDR recurring None reg_base_name MB_START_ADDR title_desc Memory Test Start Address Register description MB_START_ADDR: Memory Test Start Address view PCI bar SMRBASE offset_start 19ch offset_end 19fh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-16 acronym ROW description MemBIST Start Row Address 15:0 sticky Y reset 0000000000000000b [ 0000h ] access RW ---------------- range 15 acronym RESERVED description Reserved sticky reset [ 0b ] 0h access RO ---------------- range 14-3 acronym COL description MemBIST Start Column Address BL8[14:3] <==> DRAM Column Address 15:11,9:3 BL4[14:3] <==> DRAM Column Address 14:11,9:2 sticky Y reset 000000000000b [ 000h ] access RW ---------------- range 2-0 acronym BA description MemBIST Start Bank Address 2:0 sticky Y reset [ 000b ] 0h access RW ============================================================ 1a0h MB_END_ADDR table_ref 16-264 offset 1a0h reg_name MB_END_ADDR recurring None reg_base_name MB_END_ADDR title_desc Memory Test End Address Register description MB_END_ADDR: Memory Test End Address view PCI bar SMRBASE offset_start 1a0h offset_end 1a3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-16 acronym ROW description MemBIST End Row Address 15:0 sticky Y reset 0000000000000000b [ 0000h ] access RW ---------------- range 15 acronym RESERVED description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 14-3 acronym COL description MemBIST End Column Address BL8[14:3] <==> DRAM Column Address 15:11,9:3 BL4[14:3] <==> DRAM Column Address 14:11,9:2 sticky Y reset 000000000000b [ 000h ] access RW ---------------- range 2-0 acronym BA description MemBIST End Bank Address 2:0 sticky Y reset [ 000b ] 0h access RW ============================================================ 1a4h MBLFSRSED table_ref 16-265 offset 1a4h reg_name MBLFSRSED recurring None reg_base_name MBLFSRSED title_desc Memory Test Circular Shift and LFSR Seed Register description MBLFSRSED: Memory Test Circular Shift and LFSR Seed view PCI bar SMRBASE offset_start 1a4h offset_end 1a7h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym MBLFSRSED description MemBIST LFSR Seed This 32 bit register will be used as the initial data seed for LFSR or Circular shift data pattern. sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1a8h MBFADDRPTR table_ref 16-266 offset 1a8h reg_name MBFADDRPTR recurring None reg_base_name MBFADDRPTR title_desc Memory Test Failure Address Pointer Register description MBFADDRPTR: Memory Test Failure Address Pointer Register view PCI bar SMRBASE offset_start 1a8h offset_end 1abh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym MBFADDRPTR description This 32 bit register designates which MemBIST failures to log in the available failure address locations. The default value of this register is zero. It means MemBIST always logs beginning with the first failure. If it is programmed to hex A (10 in decimal), MemBIST will log failures starting from the11th failure. The corresponding MB_ERR_DATA0/1/2/3 registers will log corrupted data in the first through fourth designated failure addresses. Note: this register does not affect the MBDATA failure bit location accumulators. sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1b0h MB_ERR_DATA00 table_ref 16-267 offset 1b0h reg_name MB_ERR_DATA00 recurring None reg_base_name MB_ERR_DATA00 title_desc Memory Test Error Data 0 description MB_ERR_DATA00 view PCI bar SMRBASE offset_start 1b0h offset_end 1b3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1b4h MB_ERR_DATA01 table_ref 16-268 offset 1b4h reg_name MB_ERR_DATA01 recurring None reg_base_name MB_ERR_DATA01 title_desc Memory Test Error Data 0 description MB_ERR_DATA01 view PCI bar SMRBASE offset_start 1b4h offset_end 1b7h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1b8h MB_ERR_DATA02 table_ref 16-269 offset 1b8h reg_name MB_ERR_DATA02 recurring None reg_base_name MB_ERR_DATA02 title_desc Memory Test Error Data 0 description MB_ERR_DATA02 view PCI bar SMRBASE offset_start 1b8h offset_end 1bbh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1bch MB_ERR_DATA03 table_ref 16-270 offset 1bch reg_name MB_ERR_DATA03 recurring None reg_base_name MB_ERR_DATA03 title_desc Memory Test Error Data 0 description MB_ERR_DATA03 view PCI bar SMRBASE offset_start 1bch offset_end 1bfh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1c0h MB_ERR_DATA04 table_ref 16-271 offset 1c0h reg_name MB_ERR_DATA04 recurring None reg_base_name MB_ERR_DATA04 title_desc Memory Test Error Data 0 description MB_ERR_DATA04 view PCI bar SMRBASE offset_start 1c0h offset_end 1c1h power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym DATA description Late failure data [71:64] & Early failure data [71:64] sticky Y reset 0000000000000000b [ 0000h ] access RW ============================================================ 1c4h MB_ERR_DATA10 table_ref 16-272 offset 1c4h reg_name MB_ERR_DATA10 recurring None reg_base_name MB_ERR_DATA10 title_desc Memory Test Error Data 1 description MB_ERR_DATA10 view PCI bar SMRBASE offset_start 1c4h offset_end 1c7h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1c8h MB_ERR_DATA11 table_ref 16-273 offset 1c8h reg_name MB_ERR_DATA11 recurring None reg_base_name MB_ERR_DATA11 title_desc Memory Test Error Data 1 description MB_ERR_DATA11 view PCI bar SMRBASE offset_start 1c8h offset_end 1cbh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1cch MB_ERR_DATA12 table_ref 16-274 offset 1cch reg_name MB_ERR_DATA12 recurring None reg_base_name MB_ERR_DATA12 title_desc Memory Test Error Data 1 description MB_ERR_DATA12 view PCI bar SMRBASE offset_start 1cch offset_end 1cfh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1d0h MB_ERR_DATA13 table_ref 16-275 offset 1d0h reg_name MB_ERR_DATA13 recurring None reg_base_name MB_ERR_DATA13 title_desc Memory Test Error Data 1 description MB_ERR_DATA13 view PCI bar SMRBASE offset_start 1d0h offset_end 1d3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1d4h MB_ERR_DATA14 table_ref 16-276 offset 1d4h reg_name MB_ERR_DATA14 recurring None reg_base_name MB_ERR_DATA14 title_desc Memory Test Error Data 1 description MB_ERR_DATA14 view PCI bar SMRBASE offset_start 1d4h offset_end 1d5h power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym DATA description Late failure data [71:64] & Early failure data [71:64] sticky Y reset 0000000000000000b [ 0000h ] access RW ============================================================ 1d8h MB_ERR_DATA20 table_ref 16-277 offset 1d8h reg_name MB_ERR_DATA20 recurring None reg_base_name MB_ERR_DATA20 title_desc Memory Test Error Data 2 description MB_ERR_DATA20 view PCI bar SMRBASE offset_start 1d8h offset_end 1dbh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1dch MB_ERR_DATA21 table_ref 16-278 offset 1dch reg_name MB_ERR_DATA21 recurring None reg_base_name MB_ERR_DATA21 title_desc Memory Test Error Data 2 description MB_ERR_DATA21 view PCI bar SMRBASE offset_start 1dch offset_end 1dfh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1e0h MB_ERR_DATA22 table_ref 16-279 offset 1e0h reg_name MB_ERR_DATA22 recurring None reg_base_name MB_ERR_DATA22 title_desc Memory Test Error Data 2 description MB_ERR_DATA22 view PCI bar SMRBASE offset_start 1e0h offset_end 1e3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1e4h MB_ERR_DATA23 table_ref 16-280 offset 1e4h reg_name MB_ERR_DATA23 recurring None reg_base_name MB_ERR_DATA23 title_desc Memory Test Error Data 2 description MB_ERR_DATA23 view PCI bar SMRBASE offset_start 1e4h offset_end 1e7h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1e8h MB_ERR_DATA24 table_ref 16-281 offset 1e8h reg_name MB_ERR_DATA24 recurring None reg_base_name MB_ERR_DATA24 title_desc Memory Test Error Data 2 description MB_ERR_DATA24 view PCI bar SMRBASE offset_start 1e8h offset_end 1e9h power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym DATA description Late failure data [71:64] & Early failure data [71:64] sticky Y reset 0000000000000000b [ 0000h ] access RW ============================================================ 1ech MB_ERR_DATA30 table_ref 16-282 offset 1ech reg_name MB_ERR_DATA30 recurring None reg_base_name MB_ERR_DATA30 title_desc Memory Test Error Data 3 description MB_ERR_DATA30 view PCI bar SMRBASE offset_start 1ech offset_end 1efh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1f0h MB_ERR_DATA31 table_ref 16-283 offset 1f0h reg_name MB_ERR_DATA31 recurring None reg_base_name MB_ERR_DATA31 title_desc Memory Test Error Data 3 description MB_ERR_DATA31 view PCI bar SMRBASE offset_start 1f0h offset_end 1f4h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Early failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1f4h MB_ERR_DATA32 table_ref 16-284 offset 1f4h reg_name MB_ERR_DATA32 recurring None reg_base_name MB_ERR_DATA32 title_desc Memory Test Error Data 3 description MB_ERR_DATA32 view PCI bar SMRBASE offset_start 1f4h offset_end 1f7h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [31:0] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1f8h MB_ERR_DATA33 table_ref 16-285 offset 1f8h reg_name MB_ERR_DATA33 recurring None reg_base_name MB_ERR_DATA33 title_desc Memory Test Error Data 3 description MB_ERR_DATA33 view PCI bar SMRBASE offset_start 1f8h offset_end 1fbh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-0 acronym DATA description Late failure data [63:32] sticky Y reset 00000000000000000000000000000000b [ 00000000h ] access RW ============================================================ 1fch MB_ERR_DATA34 table_ref 16-286 offset 1fch reg_name MB_ERR_DATA34 recurring None reg_base_name MB_ERR_DATA34 title_desc Memory Test Error Data 3 description MB_ERR_DATA34 view PCI bar SMRBASE offset_start 1fch offset_end 1fdh power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym DATA description Late failure data [71:64] & Early failure data [71:64] sticky Y reset 0000000000000000b [ 0000h ] access RW ============================================================ 260h DDRIOMC0 table_ref 16-287 offset 260h reg_name DDRIOMC0 recurring None reg_base_name DDRIOMC0 title_desc DDRIO Mode Register Control Register description None view PCI bar SMRBASE offset_start 260h offset_end 263h power_well Core size 32 default 00000078h bus_device_function 0:0:0 ---------------- range 31-13 acronym Reserved description Reserved sticky N reset [ 0000000000000000000b ] 00000h access RO ---------------- range 12-9 acronym DQVOXADJ description Bits to configure DQ buffer tco balancing sticky Y reset [ 0000b ] 0h access RW ---------------- range 8 acronym DDRVOXCTL1 description Combine this bit with DDRVOXCTL0 (defined below) Encodings: 00 : DQ and CA buffers are in VOX Cross Reference Mode 01: Bypass DQ and CA VOX Cross Reference Mode (default) 10: VOX Bypass Mode 11: Reset VOX Mode sticky Y reset [ 0b ] 0h access RW ---------------- range 7 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 6-4 acronym Reserved description Reserved sticky N reset [ 111b ] 7h access RW ---------------- range 3 acronym DDRVOXCTL0 description This is the least significant bit of DDRVOXCTL. For encoding details, see DDRVOXCTL1 above sticky Y reset [ 1b ] 1h access RW ---------------- range 2-0 acronym Reserved description Reserved sticky Y reset [ 000b ] 0h access RW ============================================================ 264h DDRIOMC1 table_ref 16-288 offset 264h reg_name DDRIOMC1 recurring None reg_base_name DDRIOMC1 title_desc DDRIO Mode Register Control Register 1 description DDRIOMC1: DDRIO Mode Control Register 1 view PCI bar SMRBASE offset_start 264h offset_end 267h power_well Core size 32 default 52520000h bus_device_function 0:0:0 ---------------- range 31-24 acronym CASLEW description CASLEW: The digital slew override 8-bit control allow for balancing of pull-up and pull-down slew rates T for CA/CLK buffers. The format of these controls and recommended reset value is given below: BitsFunction DDR2Selection. 7DDR2 = 0 Fast Corner falling 6:5slew rate trim Slow Corner falling 4:2slew rate trim Fast corner rising 1:0slew rate trim sticky Y reset [ 01010010b ] 52h access RW ---------------- range 23-16 acronym DQSLEW description DQSLEW: The digital slew override 8-bit control allow for balancing of pull-up and pull-down slew rates T for CA/CLK buffers. The format of these controls and recommended reset value is given below: BitsFunction DDR2 Selection. 7DDR2 = 0 Fast Corner falling 6:5slew rate trim Slow Corner falling 4:2slew rate trim Fast corner rising 1:0slew rate trim sticky Y reset [ 01010010b ] 52h access RW ---------------- range 15-7 acronym Reserved description Reserved sticky N reset [ 000000000b ] 000h access RO ---------------- range 6-5 acronym DEMPDQ description De-emphasis mode select bit for DQ/DQS pins. This mode can be used to reduce power and enhance data eyes. When de-emphasis is enable for a given group of I/Os, subsequent driver values that are the same have their strength reduced by half It is recommended that this be controllable by the BIOS in case there are unwanted side effects of this feature. EncodingDescription 00Disabled 01Weakly Enabled 10Full Enabled OthersReserved sticky Y reset [ 00b ] 0h access RW ---------------- range 4-3 acronym DEMPCA description De-emphasis mode select bit for command/clock pins. This mode can be used to reduce power and enhance data eyes. When de-emphasis is enable for a given group of I/Os, subsequent driver values that are the same have their strength reduced by half. It is recommended that this be controllable by the BIOS in case there are unwanted side effects of this feature. For instance, de-emphasis should be off before entering self-refresh mode of the DRAM to prevent the CKE from exceeding the JEDEC threshold once self-refresh is entered. EncodingDescription 00Disabled 01Weakly Enabled 10Full Enabled OthersReserved sticky Y reset [ 00b ] 0h access RW ---------------- range 2 acronym Reserved description Reserved sticky Y reset [ 0b ] 0h access RW ---------------- range 1-0 acronym FASTSLEW description bit[0] controls the control bits bit[1] controls the data bits sticky Y reset [ 00b ] 0h access RW ============================================================ 268h DDRIOMC2 table_ref 16-291 offset 268h reg_name DDRIOMC2 recurring None reg_base_name DDRIOMC2 title_desc DDRIO Mode Control Register 2 description DDRIOMC2: DDRIO Mode Control Register 2 view PCI bar SMRBASE offset_start 268h offset_end 26bh power_well Core size 32 default 039e6000h bus_device_function 0:0:0 ---------------- range 31-28 acronym Reserved description Reserved sticky N reset [ 0000b ] 0h access RO ---------------- range 27-26 acronym PHSEL description Core phase to Command/Address relationship. sticky Y reset [ 00b ] 0h access RW ---------------- range 25-16 acronym LEGOVERRIDE description Digital Impedance Control for RCOMP of DDR pads. See Legoverride table above. Do not use the Default setting Please refer to Section 11.4.6, "RCOMP" for more details. sticky Y reset [ 1110011110b ] 39eh access RW ---------------- range 15 acronym FIFOWPTRCLR description This bit clears the DDRIO Receive FIFO read and write pointers. The write pointer of this FIFO is generated by the DDRIO logic based on DQS while the read pointer is generated by the memory controller. The DDRIO receive FIPO read/write pointers need to be cleared after DCAL or Mbist operations are completed and before issuing any functional DRAM R/W operations. Unlike SDRC.DDRRFRS this register will reset only the read/write pointers of the DDRIO receive FIFO. It will not reset the DLL's. Please see Section 16.1.1.45, "Offset 88h: SDRC - DDR SDRAM Secondary Control Register" for more details. sticky N reset [ 0b ] 0h access RW ---------------- range 14-12 acronym MASTCNTL description Coarse delay of DQS Master DLL sticky Y reset [ 110b ] 6h access RW ---------------- range 11-0 acronym Reserved description Reserved sticky N reset [ 000000000000b ] 000h access RO ============================================================ 284h WL_CNTL[4:0] table_ref 16-293 offset 284h reg_name WL_CNTL[4:0] recurring 5 reg_base_name WL_CNTL title_desc Write Levelization Control Register description WL_CNTL[4:0]: Write Levelization Control Register view PCI bar SMRBASE offset_start 284h at 4h offset_end 294h at 4h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-16 acronym Reserved description Reserved sticky N reset 0000000000000000b [ 0000h ] access RO ---------------- range 15-14 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RW ---------------- range 13-12 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 11-8 acronym WL_CNTRL description Delay Select See Table 16-294 sticky Y reset [ 0000b ] 0h access RW ---------------- range 7-2 acronym WDLL_CNTL description Length controls for Slave Write DLL (WDLL). A delay of 0 up to 3/8 of clk1x can be programmed using this CSR. sticky Y reset [ 000000b ] 00h access RW ---------------- range 1 acronym WDLL_CLKG description Control bit for Clock gating of DQ/DQS. 0- Disable clock gating for DQ/DQS 1- Enable clock gating for DQ/DQS Note: for WL_CNTL[4], WDLL_CLKG must be equal to 0 sticky Y reset [ 0b ] 0h access RW ---------------- range 0 acronym BYP_WDLL description Bypass Write DLL. This bit is used only for centering DQS to the DQ eye. For write leveling, see Table 16-294. 0 - Bypass DLL 1 - Output with WDLL Before enabling/setting this bit to 1, software needs to first program the appropriate values in DRAMDLLC.SLVLEN & WL_CNTL[x].WDLL_CNTL. sticky Y reset [ 0b ] 0h access RW ============================================================ 298h WDLL_MISC table_ref 16-295 offset 298h reg_name WDLL_MISC recurring None reg_base_name WDLL_MISC title_desc DLL Miscellaneous Control description WDLL_MISC- DLL Miscellaneous Control view PCI bar SMRBASE offset_start 298h offset_end 29bh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-25 acronym Reserved description Reserved sticky N reset [ 0000000b ] 00h access RO ---------------- range 24 acronym WLCKDLY description 0: delay ECC/DQS[8]/DQS_L[8] only, clocks not delayed 1: delay ECC/DQS[8]/DQS_L[8] and CK[2:0]/CK_L[2:0] (Normal setting for DDR2) sticky Y reset [ 0b ] 0h access RW ---------------- range 23 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 22-16 acronym WL_PHSEL_MODE description See Table 16-294 for DQ/DQS Connectivity: [22] CS, ODT, CKE [21] CK[5:3], CK_L[5:3] [20] WL_CNTL[0] (DQ[15:0], DQS/DQS_L[1:0]) [19] WL_CNTL[1] (DQ[31:16], DQS/DQS_L[3:2]) [18] WL_CNTL[4] (ECC[7:0], DQS/DQS_L[8],CK[2:0], CK_L[2:0]) [17] WL_CNTL[2] (DQ[47:32], DQS/DQS_L[5:4]) [16] WL_CNTL[3] (DQ[63:48], DQS/DQS_L[7:6]) sticky Y reset [ 0000000b ] 00h access RW ---------------- range 15-12 acronym Reserved description Reserved sticky N reset [ 0000b ] 0h access RO ---------------- range 11-8 acronym WL_CNTRL description Delay select for CK[5:3] and CK_L[5:3]: 0xxx: no delay 1001: delay 1/4 clk1x 1000: delay 1/2 clk1x 1011: delay 3/4 clk1x 1100: delay 1 clk1x OthersReserved sticky Y reset [ 0000b ] 0h access RW ---------------- range 7-4 acronym WL_CNTRL_A description Delay select for CS, ODT and CKE 0xxx: no delay 1001: delay 1/4 clk1x 1000: delay 1/2 clk1x 1011: delay 3/4 clk1x 1100: delay 1 clk1x OthersReserved sticky Y reset [ 0000b ] 0h access RW ---------------- range 3 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 2-0 acronym WL_CMD_DLY description Reserved to Intel Encoded additional delay for CS, CKE, ODT Delay introduced = (~100ps * WL_CMD_DLY) sticky Y reset [ 000b ] 0h access RW