============================================================ 0h VID table_ref 16-2 offset 0h reg_name VID recurring None reg_base_name VID title_desc Vendor Identification Register description None view PCI bar Configuration offset_start 0h offset_end 1h power_well Core size 16 default 8086h bus_device_function 0:0:0 ---------------- range 15-0 acronym VID description Vendor Identification: This register field contains the PCI standard identification for Intel 8086h. sticky reset 1000000010000110b [ 8086h ] access RO ============================================================ 2h DID table_ref 16-3 offset 2h reg_name DID recurring None reg_base_name DID title_desc Device Identification Register description None view PCI bar Configuration offset_start 2h offset_end 3h power_well Core size 16 default 5020h bus_device_function 0:0:0 ---------------- range 15-0 acronym DID description Device Identification Number: This is a 16-bit value assigned to the IMCH Host-NSI Bridge Function 0. sticky reset 0101000000100000b [ 5020h ] access RO ============================================================ 4h PCICMD table_ref 16-4 offset 4h reg_name PCICMD recurring None reg_base_name PCICMD title_desc PCI Command Register description None view PCI bar Configuration offset_start 4h offset_end 5h power_well Core size 16 default 0006h bus_device_function 0:0:0 ---------------- range 15-10 acronym Reserved description Reserved sticky reset 000000b [ 00h ] access ---------------- range 9 acronym FB2B description Fast Back-to-Back Enable: This bit is hardwired to 0. sticky reset [ 0b ] 0h access RO ---------------- range 8 acronym SERRE description SERR Enable: This bit is a global enable bit for Device 0 SERR messaging. The IMCH does not have a SERR signal. The IMCH communicates the SERR condition by sending a SERR message over NSI to the IICH. 0 = Disable. The SERR message is not generated by the IMCH for Device 0.1 = Enable. The IMCH enables generation of SERR messages over NSI for specific Device 0, Function 0 error conditions that are enabled via the PCICMD register. The error status is reported in the PCISTS registers. The only error event enabled through Device 0, Function 0 is Detected Parity Error which is essentially a NSI poisoned TLP, and is enabled by the parity error enable bit (PERRE).Note:This bit only controls SERR messaging for Device 0, Function 0. Device 0, Function 1, and Devices 1-7 have their own SERR bits to control error reporting for error conditions occurring on their respective devices. The control bits are used in a logical OR manner to enable the SERR NSI message mechanism. sticky reset [ 0b ] 0h access RW ---------------- range 7 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 6 acronym PERRE description Parity Error Enable: 0 = Disable. The IMCH does not take any action when it detects data corruption on NSI.1 = Enable. The IMCH generates an SERR message over the NSI to the IICH when a poisoned TLP is detected by the IMCH on NSI (DPE set in PCISTS) and SERRE is set to 1. sticky reset [ 0b ] 0h access RW ---------------- range 5-3 acronym Reserved description Reserved sticky reset 000b [ 0h ] access ---------------- range 2 acronym BME description Bus Master Enable: The IMCH is always enabled as a master on NSI. This bit is hardwired to 1. Writes to this bit position have no effect. sticky reset [ 1b ] 1h access RO ---------------- range 1 acronym MAE description Memory Access Enable: This bit is hardwired to 1. sticky reset [ 1b ] 1h access RO ---------------- range 0 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ============================================================ 6h PCISTS table_ref 16-5 offset 6h reg_name PCISTS recurring None reg_base_name PCISTS title_desc PCI Status Register description None view PCI bar Configuration offset_start 6h offset_end 7h power_well Core size 16 default 0010h bus_device_function 0:0:0 ---------------- range 15 acronym DPE description Detected Parity Error: This bit is set to 1 whenever it receives a poisoned TLP regardless of the state of the parity error response bit. Software may clear this by writing a 1 to this bit. sticky reset [ 0b ] 0h access RWC ---------------- range 14 acronym SSE description Signaled System Error: 0 = Software clears this bit by writing a 1 to the bit location.1 = IMCH Device 0, Function 0 generates a SERR message over NSI for any enabled Device 0, Function 0 error condition. Device 0 error conditions are enabled in the PCICMD register. Device 0 error flags are read/reset from the PCISTS register. The only error that can be enabled to signal system error through Device 0, Function 0 is the detected parity error which is essentially a NSI poisoned TLP. Software may clear this by writing a 1 to this bit. sticky reset [ 0b ] 0h access RWC ---------------- range 13 acronym RMAS description Received Master Abort Status: This bit is set if the IMCH generates a NSI request that receives a completion with unsupported request completion status. Software may clear this by writing a 1 to this bit. sticky reset [ 0b ] 0h access RWC ---------------- range 12 acronym RTAS description Received Target Abort Status: Set to 1 by hardware if the IMCH generated a request that received a completion with Completer Abort status. Software clears this bit by writing a 1 to this bit location. sticky reset [ 0b ] 0h access RWC ---------------- range 11 acronym STAS description Signaled Target Abort Status: The IMCH does not generate a Completer Abort on the NSI completion packet. This bit is hardwired to w10. Writes to this bit position have no effect. sticky reset [ 0b ] 0h access RO ---------------- range 10-9 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 8 acronym DPD description Master Data Parity Error Detected: This bit is hardwired to 0. sticky reset [ 0b ] 0h access RWC ---------------- range 7 acronym FB2B description Fast Back-to-Back: Reserved. sticky reset [ 0b ] 0h access ---------------- range 6-5 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 4 acronym CLIST description Capability List: This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. sticky reset [ 1b ] 1h access RO ---------------- range 3-0 acronym Reserved description Reserved sticky reset 0000b [ 0h ] access ============================================================ 8h RID table_ref 16-6 offset 8h reg_name RID recurring None reg_base_name RID title_desc Revision Identification Register description None view PCI bar Configuration offset_start 8h offset_end 8h power_well Core size 8 default Variable bus_device_function 0:0:0 ---------------- range 7-0 acronym RID description Revision Identification Number: This value indicates the revision identification number for the IMCH Device 0. sticky reset None access RO ============================================================ ah SUBC table_ref 16-7 offset ah reg_name SUBC recurring None reg_base_name SUBC title_desc Sub-Class Code Register description None view PCI bar Configuration offset_start ah offset_end ah power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-0 acronym SUBC description Sub-Class Code: This value indicates the Sub Class Code into which the IMCH Device 0 falls. 00h = Host Bridge sticky reset 00000000b [ 00h ] access RO ============================================================ bh BCC table_ref 16-8 offset bh reg_name BCC recurring None reg_base_name BCC title_desc Base Class Code Register description None view PCI bar Configuration offset_start bh offset_end bh power_well Core size 8 default 06h bus_device_function 0:0:0 ---------------- range 7-0 acronym BASEC description Base Class Code: This value indicates the Base Class Code for the IMCH Device 0. 06h = Bridge device sticky reset 00000110b [ 06h ] access RO ============================================================ eh HDR table_ref 16-9 offset eh reg_name HDR recurring None reg_base_name HDR title_desc Header Type Register description None view PCI bar Configuration offset_start eh offset_end eh power_well Core size 8 default 80h bus_device_function 0:0:0 ---------------- range 7-0 acronym HDR description Note:PCI Header: The header type of the IMCH Device 0.80h = multi-function device with standard header layout.This register should return a 00h indicating a single function device, when both functions 1 and 2 are disabled. sticky reset 10000000b [ 80h ] access RO ============================================================ 14h SMRBASE table_ref 16-10 offset 14h reg_name SMRBASE recurring None reg_base_name SMRBASE title_desc System Memory RCOMP Base Address Register description None view PCI bar Configuration offset_start 14h offset_end 17h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-12 acronym UPBITS description Upper Programmable Base Address: These bits are part of the SM MMR region, normally set by configuration software to locate the base address of the region. The actual behavior of this field depends on the SM MMR Enable bit in the IMCH TST2 register (bit 6) as defined above. When IMCH TST2[6] = 1 these bits are Read/Write. When IMCH TST2[6] = 0 these bits are Read-Only as zeros. sticky reset 00000000000000000000b [ 00000h ] access RW or RO ---------------- range 11-4 acronym LOWBITS description Lower Bits: These bits are hardwired to 0. This forces the size of the memory region to be 4 Kbyte. sticky reset 00000000b [ 00h ] access RO ---------------- range 3 acronym PF description Prefetchable: This bit is hardwired to 0 to indicate that the System Memory MMR region is NON-Prefetchable. sticky reset [ 0b ] 0h access RO ---------------- range 2-1 acronym TYPE description Addressing Type: These bits determine addressing type and they are hardwired to 00 to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space in order to comply with the PCI specification for base address registers. sticky reset [ 00b ] 0h access RO ---------------- range 0 acronym MSPACE description Memory Space Indicator: Hardwired to 0 to identify the MMR range as a memory range as per the specification for PCI base address registers. sticky reset [ 0b ] 0h access RO ============================================================ 2ch SVID table_ref 16-11 offset 2ch reg_name SVID recurring None reg_base_name SVID title_desc Subsystem Vendor Identification Register description None view PCI bar Configuration offset_start 2ch offset_end 2dh power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym SUBVID description Subsystem Vendor ID: This field must be programmed during boot-up to indicate the vendor of the system board. sticky reset 0000000000000000b [ 0000h ] access RWO ============================================================ 2eh SID table_ref 16-12 offset 2eh reg_name SID recurring None reg_base_name SID title_desc Subsystem Identification Register description None view PCI bar Configuration offset_start 2eh offset_end 2fh power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym SUBID description Subsystem ID: This field must be programmed during BIOS initialization. After it has been written once it becomes Read-Only. When any byte or combination of bytes of this register is written, the register value locks and cannot be further updated. sticky reset 0000000000000000b [ 0000h ] access RWO ============================================================ 4ch NSIBAR table_ref 16-14 offset 4ch reg_name NSIBAR recurring None reg_base_name NSIBAR title_desc Root Complex Block Address Register description None view PCI bar Configuration offset_start 4ch offset_end 4fh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-12 acronym NSI_BA description NSI Base Address: The BIOS programs this register resulting in a base address for a 4 Kbyte block of contiguous memory address space. This register ensures that a naturally aligned 4 Kbyte space is allocated within total addressable memory space of 4 Gbyte. System Software uses this base address to program the NSI register set. When IMCH TST2[5] = 1, the NSI Memory Mapped Register space is visible and memory mapped accesses are claimed and decoded appropriately. When IMCH TST2[5] = 0, the NSI Memory Mapped Register space is disabled and does not claim any memory. (THE NSIBAR register is still read/write accessible.) sticky reset 00000000000000000000b [ 00000h ] access RW or RO ---------------- range 11-0 acronym Reserved description Hardwired to 0 sticky reset 000000000000b [ 000h ] access ============================================================ 50h CFG0 table_ref 16-15 offset 50h reg_name CFG0 recurring None reg_base_name CFG0 title_desc IMCH Configuration 0 Register description None view PCI bar Configuration offset_start 50h offset_end 50h power_well Core size 8 default 0ch bus_device_function 0:0:0 ---------------- range 7-3 acronym Reserved description Reserved sticky reset 00000b [ 00h ] access ---------------- range 2 acronym IOQD description In-Order Queue Depth: This bit reflects the value sampled on HA[7]# on the de-assertion of the CPURST#. It indicates the depth of the CPU bus in-order queue. 0 = HA[7]# has been sampled asserted (e.g., logic one, or electrical low). The depth of the IOQ is set to one (e.g., no pipelining on the processor bus). HA[7]# may be driven low during CPURST# by an external source.1 = HA[7]# was sampled as deasserted (e.g. logic zero or electrical high). The depth of the processor bus in-order queue is configured to the maximum (e.g., 12). sticky reset [ 1b ] 1h access RO ---------------- range 1 acronym DRFD description Deferred Resource Fairness Disable: 0 = Clearing the bit allows the fairness logic to start working again. 1 = Setting this bit clears the fairness logic for deferred resources and hold it in reset. Note:This bit should only be changed in the event that there is some issue with the fairness logic. sticky reset [ 0b ] 0h access RW ---------------- range 0 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ============================================================ 51h IMCH_CFG1 table_ref 16-16 offset 51h reg_name IMCH_CFG1 recurring None reg_base_name IMCH_CFG1 title_desc IMCH Configuration 1 Register description None view PCI bar Configuration offset_start 51h offset_end 51h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-5 acronym NSG description Number of Stop Grant Cycles: Number of Stop Grant transactions expected on the FSB bus before a Req_C2 packet is sent to the IICH. This field is programmed by the BIOS after it has enumerated the processors and before it has enabled Stop Clock generation in the IICH. Once this field has been set, it must not be modified. Note that each enabled thread within each CPU generates Stop Grant Acknowledge transactions.Note:This register is read/write and not write-once as in some implementations. Encoding Description 0 0 0 NSI Stop Grant generated after 1 FSB Stop Grant 0 0 1 NSI Stop Grant generated after 2 FSB Stop Grant 0 1 0 NSI Stop Grant generated after 3 FSB Stop Grant 0 1 1 NSI Stop Grant generated after 4 FSB Stop Grant 1 0 0 NSI Stop Grant generated after 5 FSB Stop Grant 1 0 1 NSI Stop Grant generated after 6 FSB Stop Grant 1 1 0 NSI Stop Grant generated after 7 FSB Stop Grant 1 1 1 NSI Stop Grant generated after 8 FSB Stop Grant sticky reset [ 000b ] 0h access RW ---------------- range 4-0 acronym Reserved description Reserved sticky reset [ 00000b ] 00h access ============================================================ 53h CFGNS1 table_ref 16-17 offset 53h reg_name CFGNS1 recurring None reg_base_name CFGNS1 title_desc Configuration 1 (Non-Sticky) Register description None view PCI bar Configuration offset_start 53h offset_end 53h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-2 acronym Reserved description Reserved sticky reset [ 000000b ] 00h access ---------------- range 1 acronym THWO description Throttled-Write Occurred: 0 = Writing a zero clears this bit.1 = This bit is set by hardware when a write is throttled. This happens when the maximum allowed number of writes has been reached during a time-slice and there is at least one more write to be completed. sticky reset [ 0b ] 0h access RW0C ---------------- range 0 acronym THRO description Throttled-Read Occurred: 0 = Writing a zero clears this bit.1 = This bit is set by hardware when a read is throttled. This happens when the maximum allowed number of reads has been reached during a time-slice and there is at least one more read to be done. sticky reset [ 0b ] 0h access RW0C ============================================================ 58h FDHC table_ref 16-18 offset 58h reg_name FDHC recurring None reg_base_name FDHC title_desc Fixed DRAM Hole Control Register description None view PCI bar Configuration offset_start 58h offset_end 58h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7 acronym HEN description Hole Enable: This field enables a memory hole in DRAM space. The DRAM that lies "behind" this space is not remapped. 0 = No memory hole1 = Memory hole from 15-16 Mbytes. Accesses in this range are sent to NSI. sticky reset [ 0b ] 0h access RW ---------------- range 6-0 acronym Reserved description Reserved sticky reset 0000000b [ 00h ] access ============================================================ 59h PAM0 table_ref 16-19 offset 59h reg_name PAM0 recurring None reg_base_name PAM0 title_desc Programmable Attribute Map 0 Register description None view PCI bar Configuration offset_start 59h offset_end 59h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register: This field controls the steering of read and write cycles that address the BIOS area from 0F0000 to 0FFFFF. Encoding Description: 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. Allwrites are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads areserviced by NSI. 1 1 Normal DRAM Operation - All reads and writes areserviced by DRAM. sticky reset [ 00b ] 0h access RW ---------------- range 3-0 acronym Reserved description Reserved sticky reset 0000b [ 0h ] access ============================================================ 5ah PAM1 table_ref 16-20 offset 5ah reg_name PAM1 recurring None reg_base_name PAM1 title_desc Programmable Attribute Map 1 Register description None view PCI bar Configuration offset_start 5ah offset_end 5ah power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register 0C4000-0C7FFF: This field controls the steering of read and write cycles that address the BIOS area from 0C4000 to 0C7FFF Encoding Description 0 0DRAM Disabled - All accesses are directed to NSI. 0 1Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0Write-Only - All writes are sent to DRAM.Reads are serviced by NSI. 1 1Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 1-0 acronym LOENABLE description Attribute Register 0C0000-0C3FFF: This field controls the steering of read and write cycles that address the BIOS area from 0C0000 to 0C3FFF. Encoding Description 0 0DRAM Disabled - All accesses are directed to NSI. 0 1Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ============================================================ 5bh PAM2 table_ref 16-21 offset 5bh reg_name PAM2 recurring None reg_base_name PAM2 title_desc Programmable Attribute Map 2 Register description None view PCI bar Configuration offset_start 5bh offset_end 5bh power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register 0CC000-0CFFFF: Encoding Description 0 0DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 1-0 acronym LOENABLE description Attribute Register 0C8000-0CBFFF: This field controls the steering of read and write cycles that address the BIOS area from 0C8000 to 0CBFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. A writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ============================================================ 5ch PAM3 table_ref 16-22 offset 5ch reg_name PAM3 recurring None reg_base_name PAM3 title_desc Programmable Attribute Map 3 Register description None view PCI bar Configuration offset_start 5ch offset_end 5ch power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register 0D4000-0D7FFF: This field controls the steering of read and write cycles that address the BIOS area from 0D4000 to 0D7FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 1-0 acronym LOENABLE description Attribute Register 0D0000-0D3FFF: This field controls the steering of read and write cycles that address the BIOS area from 0D0000 to 0D3FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ============================================================ 5dh PAM4 table_ref 16-23 offset 5dh reg_name PAM4 recurring None reg_base_name PAM4 title_desc Programmable Attribute Map 4 Register description None view PCI bar Configuration offset_start 5dh offset_end 5dh power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register 0DC000-0DFFFF: This field controls the steering of read and write cycles that address the BIOS area from 0DC000 to 0DFFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 1-0 acronym LOENABLE description Attribute Register 0D8000-0DBFFF: This field controls the steering of read and write cycles that address the BIOS area from 0D8000 to 0DBFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ============================================================ 5eh PAM5 table_ref 16-24 offset 5eh reg_name PAM5 recurring None reg_base_name PAM5 title_desc Programmable Attribute Map 5 Register description None view PCI bar Configuration offset_start 5eh offset_end 5eh power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register 0E4000-0E7FFF: This field controls the steering of read and write cycles that address the BIOS area from 0E4000 to 0E7FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 1-0 acronym LOENABLE description Attribute Register 0E0000-0E3FFF: This field controls the steering of read and write cycles that address the BIOS area from 0E0000 to 0E3FFF. Encoding Description 0 0DRAM Disabled - All accesses are directed to NSI. 0 1Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1Normal DRAM Operation - All reads and writes are serviced by DRAM. sticky reset [ 00b ] 0h access RW ============================================================ 5fh PAM6 table_ref 16-25 offset 5fh reg_name PAM6 recurring None reg_base_name PAM6 title_desc Programmable Attribute Map 6 Register description None view PCI bar Configuration offset_start 5fh offset_end 5fh power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5-4 acronym HIENABLE description Attribute Register 0EC000-0EFFFF: This field controls the steering of read and write cycles that address the BIOS area from 0EC000 to 0EFFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM sticky reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 1-0 acronym LOENABLE description Attribute Register 0E8000-0EBFFF: This field controls the steering of read and write cycles that address the BIOS area from 0E8000 to 0EBFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM sticky reset [ 00b ] 0h access RW ============================================================ 9ch DEVPRES table_ref 16-26 offset 9ch reg_name DEVPRES recurring None reg_base_name DEVPRES title_desc Device Present Register description None view PCI bar Configuration offset_start 9ch offset_end 9ch power_well Core size 8 default 33h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky reset [ 00b ] 0h access ---------------- range 5 acronym Reserved description Reserved sticky reset [ 1b ] 1h access RW ---------------- range 4 acronym Device_4_Present description 0 = PCI-to-PCI Bridge is disabled.1 = PCI-to-PCI Bridge is enabled. sticky reset [ 1b ] 1h access RW ---------------- range 3 acronym Device_3_Present description 0 = PCI Express* port A1 (x4) is disabled. In this state, port A (Device 2) can operate with a maximum x8 link width. 1 = PCI Express port A1 is enabled. In this state, port A can operate with a maximum x4 link width.When the SKU value is cleared, this field is read/write. When the SKU value is set, this field becomes a read-only '0' sticky reset [ 0b ] 0h access RWO or RO ---------------- range 2 acronym Device_2_Present description 0 = PCI Express port A is disabled. 1 = PCI Express port A is enabled.When the SKU value is cleared, this field is read/write. When the SKU value is set, this field becomes a read-only '0' sticky reset [ 0b ] 0h access RWO or RO ---------------- range 1 acronym Device_1_Present description 0 = EDMA Controller is disabled.1 = EDMA Controller is enabled. sticky reset [ 1b ] 1h access RWO ---------------- range 0 acronym Reserved description Reserved sticky reset [ 1b ] 1h access ============================================================ 9dh EXSMRC table_ref 16-27 offset 9dh reg_name EXSMRC recurring None reg_base_name EXSMRC title_desc Extended System Management RAM Control Register description None view PCI bar Configuration offset_start 9dh offset_end 9dh power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7 acronym H_SMRAME description Enable High SMRAM: Controls the SMM memory space location (above 1 MByte or below 1 MByte) 0 = High SMRAM memory space is disabled.1 = And G_SMRAME is 1, the high SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA_0000h to 0FEDB_FFFFh are remapped to DRAM addresses within the range 000A0000h to 000BFFFFh. Once D_LCK (See Table 35) has been set, this bit becomes Read-Only. sticky reset [ 0b ] 0h access RWL ---------------- range 6 acronym MDAP description MDA Present: This bit works with the VGA Enable bits in the BCTRL registers of Devices 2-3 to control the routing of CPU initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if none of the VGA Enable bits are set. If none of the VGA enable bits are set, then accesses to IO address range x3BCh-x3BFh are forwarded to NSI. If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are treated just like any other IO accesses. For example, the cycles are forwarded to PEA[0:1] if the address is within the corresponding IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to NSI. Note:Since the logic performs the address decoding on a DW boundary, the DW that includes the address 3BF also includes addresses 3BC, 3BD, and 3BE, and accesses to any of these byte addresses are handled as MDA references. MDA resources are defined as the following: Memory: 0B0000h - 0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (Including ISA address aliases, A[15:10] are not used in decode)Note:The VGA region includes I/O space ranges 3B0-3BBh, and 3C0-3DFh, so there is an overlap between these two I/O regions. Any I/O reference that includes the I/O locations listed above, or their aliases, are forwarded to NSI even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGA MDA Behavior 0 0 All References to MDA and VGA go to NSI01 Illegal Combination (DO NOT USE)10All References to VGA go to device with VGAenable set. MDA- only references (I/O address3BF and aliases) go to NSI.11VGA-only references go to the PCI Express portwhich has its VGA Enable bit set. MDAreferences go to the NSI. sticky reset [ 0b ] 0h access RW ---------------- range 5 acronym APICDIS description APIC Memory Range Disable: 0 = The IMCH send cycles between 0_FEC0_0000 and 0_FEC7_FFFF to NSI, accesses between 0_FEC8_0000 and 0_FEC8_0FFF are sent to PEA0, between 0_FEC8_1000 and 0_FEC8_1FFF are sent to PEA1B. 1 = The IMCH forwards all accesses to the IOAPIC regions to NSI. sticky reset [ 0b ] 0h access RW ---------------- range 4 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 3 acronym G_SMRAME description Global SMRAM Enable: 0 = The Compatible SMRAM functions are disabled.1 = The Compatible SMRAM functions are enabled, providing 128 Kbyte of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to Section 16.1.1.26, "Offset 9Eh: SMRAM - System Management RAM Control Register" for more details. Once D_LCK (See Table 16-28) is set, this bit becomes read-only. sticky reset [ 0b ] 0h access RWL ---------------- range 2-1 acronym TSEG_SZ description TSEG Size: Selects the size of the TSEG memory block if enabled. Memory from the top of DRAM space (TOLM - TSEG_SZ) to TOLM is partitioned away so that it may only be accessed by the processor interface and only then when the SMM bit is set in the request packet. Non-SMM accesses to this memory region are specially terminated when the TSEG memory block is enabled. Note that once D_LCK (See Table 16-28) is set, these bits become Read-Only. 0 0 (TOLM - 128 k) to TOLM 0 1 (TOLM - 256 k) to TOLM 1 0 (TOLM - 512 k) to TOLM 1 1 (TOLM - 1 M) to TOLM sticky reset [ 00b ] 0h access RWL ---------------- range 0 acronym T_EN description TSEG Enable: Enabling of SMRAM memory for Extended SMRAM space only. 0 = SMRAM memory for Extended SMRAM space disabled.1 = And G_SMRAME =1 and T_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK (See Table 16-28) is set, this bit becomes Read-Only. sticky reset [ 0b ] 0h access RWL ============================================================ 9eh SMRAM table_ref 16-28 offset 9eh reg_name SMRAM recurring None reg_base_name SMRAM title_desc System Management RAM Control Register description None view PCI bar Configuration offset_start 9eh offset_end 9eh power_well Core size 8 default 02h bus_device_function 0:0:0 ---------------- range 7 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 6 acronym D_OPEN description SMM Space Open: 0 = The SMM space DRAM is not visible1 = And D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software must ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. This bit becomes RO when D_LCK is set to 1. sticky reset [ 0b ] 0h access RWL ---------------- range 5 acronym D_CLS description SMM Space Closed: 0 = SMM space DRAM is accessible to data references1 = SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DRAM. This allows SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range. Software must ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note:The D_CLS bit only applies to Compatible SMM space. sticky reset [ 0b ] 0h access RW ---------------- range 4 acronym D_LCK description SMM Space Locked: 0 = SMM space unlocked1 = And then D_OPEN is reset to 0 and D_LCK, D_OPEN, H_SMRAME, TSEG_SZ and T_EN become Read-Only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to lock SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. sticky reset [ 0b ] 0h access RWS ---------------- range 3 acronym Reserved description Reserved. sticky reset [ 0b ] 0h access ---------------- range 2-0 acronym C_BASE_SEG description Compatible SMM Space Base Segment: This field indicates the location of SMM space. SMM DRAM is not remapped. It is simply made visible if the conditions are right to access SMM space, otherwise the access is treated as a VGA access. Since the IMCH supports only the SMM space between A0000 and BFFFF, this field is hardwired to 010. sticky reset [ 010b ] 2h access RO ============================================================ 9fh EXSMRAMC table_ref 16-29 offset 9fh reg_name EXSMRAMC recurring None reg_base_name EXSMRAMC title_desc Expansion System Management RAM Control Register description None view PCI bar Configuration offset_start 9fh offset_end 9fh power_well Core size 8 default 07h bus_device_function 0:0:0 ---------------- range 7 acronym E_SMERR description Invalid SMRAM Access: 0 = CPU has not accessed the defined memory ranges in Extended SMRAM.1 = This bit is set when CPU has accessed the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software's responsibility to clear this bit. This bit is cleared by software writing a 1 to the bit location. sticky reset [ 0b ] 0h access RWC ---------------- range 6-3 acronym Reserved description Reserved sticky reset 0000b [ 0h ] access ---------------- range 2 acronym SM_CACHE description SMRAM Cacheable: This bit is forced to 1 by IMCH. (Moved from ESMRAMC bit 5) sticky reset [ 1b ] 1h access RO ---------------- range 1 acronym SM_L1 description L1 Cache Enable for SMRAM: This bit is forced to 1 by IMCH. (Moved from ESMRAMC bit 4) sticky reset [ 1b ] 1h access RO ---------------- range 0 acronym SM_L2 description L2 Cache Enable for SMRAM: This bit is forced to 1 by IMCH. (Moved from ESMRAMC bit 3) sticky reset [ 1b ] 1h access RO ============================================================ b8h IMCH_MENCBASE table_ref 16-30 offset b8h reg_name IMCH_MENCBASE recurring None reg_base_name IMCH_MENCBASE title_desc IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Base Address Register description None view PCI bar Configuration offset_start b8h offset_end bbh power_well Core size 32 default 000fffffh bus_device_function 0:0:0 ---------------- range 31-20 acronym Reserved description Reserved sticky reset 000000000000b [ 000h ] access ---------------- range 19-0 acronym MENCBASE description IA/ASU Shared Non-Coherent Memory Base Address Bits[31:12]: Specifies the address of the lower boundary of the IA/ASU shared non-coherent window in 32-bit system address space. The window is 4KB-aligned and inclusive of this address. This register field specifies bits[31:12] of the address; bits[11:0] are assumed zeros given 4KB alignment. sticky reset 11111111111111111111b [ fffffh ] access RW ============================================================ bch IMCH_MENCLIMIT table_ref 16-31 offset bch reg_name IMCH_MENCLIMIT recurring None reg_base_name IMCH_MENCLIMIT title_desc IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Limit Address Register description None view PCI bar Configuration offset_start bch offset_end bfh power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-20 acronym Reserved description Reserved sticky reset 000000000000b [ 000h ] access ---------------- range 19-0 acronym MENCLIMIT description IA/ASU Shared Non-Coherent Memory Limit Address Bits[31:12]: Specifies the address of the upper boundary of the IA/ASU shared non-coherent window in 32-bit system address space. The window is 4KB-aligned and inclusive of this address. This register field specifies bits[31:12] of the address; bits[11:0] are assumed ones. Setting IMCH_MENCLIMIT less than IMCH_MENCBASE indicates a zero-sized window and thus that all memory is coherent. sticky reset 00000000000000000000b [ 00000h ] access RW ============================================================ c4h TOLM table_ref 16-32 offset c4h reg_name TOLM recurring None reg_base_name TOLM title_desc Top of Low Memory Register description None view PCI bar Configuration offset_start c4h offset_end c5h power_well Core size 16 default 0800h bus_device_function 0:0:0 ---------------- range 15-11 acronym TOLM description Top of Low Memory: This register corresponds to bits 31 to 27 of the system address which is 1 greater than the maximum DRAM location below 4 Gbyte. Configuration software must set this value to either the maximum amount of memory in the system or to the minimum address allocated for PCI memory or the graphics aperture, whichever is smaller. Address bits 26:00 are assumed to be 0 for the purposes of address comparison. Addresses equal to or greater than the TOLM, and less than 4 G, are treated as non-memory accesses. All accesses less than the TOLM are treated as DRAM accesses (except for the 15-16 Mbyte or PAM gaps). This register must be set to at least 0800h, for a minimum of 128 Mbyte of DRAM. There is also a minimum of 128 Mbyte of PCI space, since this register is on a 128 Mbyte boundary. Configuration software must set this value to either the maximum amount of memory in the system (same as DRB3), or to the lower 128 Mbyte boundary of the Memory Mapped IO range, whichever is smaller. Programming example: 1100_0b = 3 Gbyte (assuming that DBR7 is set > 4 Gbyte): An access to 0_C000_0000h or above (but <4 Gbyte) is considered above the TOLM and therefore not to DRAM. It may go to one of the PEA ports or NSI or be subtracted and decoded to NSI. An access to 0_BFFF_FFFFh and below is considered below the TOLM and go to DRAM. sticky reset [ 00001b ] 01h access RW ---------------- range 10-0 acronym Reserved description Reserved sticky reset 00000000000b [ 000h ] access ============================================================ c6h REMAPBASE table_ref 16-33 offset c6h reg_name REMAPBASE recurring None reg_base_name REMAPBASE title_desc Remap Base Address Register description None view PCI bar Configuration offset_start c6h offset_end c7h power_well Core size 16 default 03ffh bus_device_function 0:0:0 ---------------- range 15-10 acronym Reserved description Reserved sticky reset 000000b [ 00h ] access ---------------- range 9-0 acronym REMAPBASE description Remap Base Address Bits [35:26]: The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:0] of the Remap Base Address are assumed to be 0s. Thus the bottom of the defined memory range is aligned to a 64 Mbyte boundary. When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled. This field defaults to 3FF. sticky reset 1111111111b [ 3ffh ] access RW ============================================================ c8h REMAPLIMIT table_ref 16-34 offset c8h reg_name REMAPLIMIT recurring None reg_base_name REMAPLIMIT title_desc Remap Limit Address Register description None view PCI bar Configuration offset_start c8h offset_end c9h power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-10 acronym Reserved description Reserved sticky reset 000000b [ 00h ] access ---------------- range 9-0 acronym REMAPLIMIT description Remap Limit Address Bits [35:26]: The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:00] of the Remap Limit Address are assumed to be Fs. Thus the top of the defined range is one less than a 64 Mbyte boundary. When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled. sticky reset 0000000000b [ 000h ] access RW ============================================================ cah REMAPOFFSET table_ref 16-35 offset cah reg_name REMAPOFFSET recurring None reg_base_name REMAPOFFSET title_desc Remap Offset Register description None view PCI bar Configuration offset_start cah offset_end cbh power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-10 acronym Reserved description Reserved sticky reset 000000b [ 00h ] access ---------------- range 9-0 acronym REMAPOFFST description Remap Offset: This register contains the difference between the REMAPBASE and TOLM. This register value corresponds to address bits 35:26. It is used to translate the physical FSB address to the system memory address for accesses to the remap region. sticky reset 0000000000b [ 000h ] access RW ============================================================ cch TOM table_ref 16-36 offset cch reg_name TOM recurring None reg_base_name TOM title_desc Top Of Memory Register description None view PCI bar Configuration offset_start cch offset_end cdh power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-9 acronym Reserved description Reserved sticky reset 0000000b [ 00h ] access ---------------- range 8-0 acronym TOM description Top of Memory: This register reflects the effective size of memory. These bits correspond to address bits 35:27. (128 Mbyte granularity) Bits 26:00 are assumed to be 0. sticky reset 000000000b [ 000h ] access RW ============================================================ ceh HECBASE table_ref 16-37 offset ceh reg_name HECBASE recurring None reg_base_name HECBASE title_desc PCI Express Port A (PEA) Enhanced Configuration Base Address Register description None view PCI bar Configuration offset_start ceh offset_end cfh power_well Core size 16 default e000h bus_device_function 0:0:0 ---------------- range 15-12 acronym HECBASE description PEA Enhanced Configuration Base: This register contains the address that corresponds to bits 31 to 28 of the base address for PEA enhanced configuration space below 4 Gbyte. Configuration software reads this register to determine where the 256 Mbyte range of addresses resides for this particular host bridge. BIOS needs to write this register at boot time. Settings 0 and F are not valid. When any byte or combination of bytes of this register is written, the register value locks down and cannot be further updated. sticky reset [ 1110b ] eh access RWO ---------------- range 11-0 acronym Reserved description Reserved. sticky reset 000000000000b [ 000h ] access ============================================================ d8h CACHECTL0 table_ref 16-38 offset d8h reg_name CACHECTL0 recurring None reg_base_name CACHECTL0 title_desc Write Cache Control 0 Register description None view PCI bar Configuration offset_start d8h offset_end d8h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-1 acronym Reserved description Reserved for other customer visible features. sticky reset 0000000b [ 00h ] access RO ---------------- range 0 acronym WCFLUSH description Write Cache Flush: 0 = Cleared by hardware when flush is complete.1 = All entries in the write cache are flushed to DRAM with high priority. The arbiter no longer accepts requests until the write cache has been flushed. Software can poll this bit to determine when the flush is complete. sticky reset [ 0b ] 0h access RWS ============================================================ deh SKPD table_ref 16-39 offset deh reg_name SKPD recurring None reg_base_name SKPD title_desc Scratchpad Data Register description None view PCI bar Configuration offset_start deh offset_end dfh power_well Core size 16 default 0000h bus_device_function 0:0:0 ---------------- range 15-0 acronym SCRTCH description Scratchpad: These bits are simply Read/Write storage bits that have no effect on the IMCH functionality. BIOS typically programs this register to the revision ID of the Memory Reference Code. sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ f6h IMCH_TST2 table_ref 16-40 offset f6h reg_name IMCH_TST2 recurring None reg_base_name IMCH_TST2 title_desc IMCH Test Byte 2 Register description None view PCI bar Configuration offset_start f6h offset_end f6h power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 6 acronym SYSMMREN description System Memory MMR Enable: 0 = This BAR is hardwired to all zeros (effectively disabling this memory space).1 = The SM Memory Mapped Register space and corresponding Base Address Register (B:D:F:R 0,0,0,14H) is visible. Section 16.1.1.9, "Offset 14h: SMRBASE - System Memory RCOMP Base Address Register" sticky reset [ 0b ] 0h access RW ---------------- range 5 acronym NSIMMREN description NSI MMR Enable: 0 = The NSI Memory Mapped Register space is disabled, and does not claim any memory. (THE NSIBAR register is still read/write accessible.)1 = The NSI Memory Mapped Register space is visible, and memory mapped accesses are claimed and decoded appropriately. (B:D:F:R 0,0,0,4CH) Section 16.1.1.12, "Offset 4Ch: NSIBAR - Root Complex Block Address Register" sticky reset [ 0b ] 0h access RW ---------------- range 4 acronym Reserved description Reserved. sticky reset [ 0b ] 0h access ---------------- range 3 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 2 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 1 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ---------------- range 0 acronym Reserved description Reserved sticky reset [ 0b ] 0h access ============================================================ 60h DRB[0-3] table_ref 16-42 offset 60h reg_name DRB[0-3] recurring 4 reg_base_name DRB title_desc DRAM Row [3:0] Boundary Register description None view PCI bar Configuration offset_start 60h at 1h offset_end 60h at 1h power_well Core size 8 default ffh bus_device_function 0:0:0 ---------------- range 7-0 acronym DRAM_RBA description DRAM Row Boundary Address: This 8 bit value defines the upper address for each row of DRAM rows. This 8 bit value is compared against a set of address lines to determine the upper address limit of a particular row. This field corresponds to bits 33:26of the system address. sticky N reset 11111111b [ ffh ] access RW ============================================================ 70h DRA[0-1] table_ref 16-44 offset 70h reg_name DRA[0-1] recurring 2 reg_base_name DRA title_desc DRAM Row [0:1] Attribute Register description None view PCI bar Configuration offset_start 70h at 4h offset_end 73h at 4h power_well Core size 32 default 00000515h bus_device_function 0:0:0 ---------------- range 31-29 acronym NR_ODD description Number of Rows for odd numbered row. Functionality and encoding is exactly the same as NR_EVEN sticky N reset [ 000b ] 0h access RW ---------------- range 28-26 acronym NC_ODD description Number of Columns for odd numbered row. Functionality and encoding is exactly the same as NC_EVEN sticky N reset [ 000b ] 0h access RW ---------------- range 25-23 acronym NR_EVEN description Number of Rows for even numbered row: This information is used by the Mbist engine. Note that this field should be programmed to be consistent with the DIMMTECH fields of the DRA register. 0008192 00116,384 01032,768 01165,536 OthersReserved sticky N reset [ 000b ] 0h access RW ---------------- range 22-20 acronym NC_EVEN description Number of Columns for even numbered row. This information is used by the Mbist engine. 0001024 0012048 0104096 0118192 OthersReserved Note that this field should be programmed to be consistent with the DIMMTECH fields of the DRA register. sticky N reset [ 000b ] 0h access RW ---------------- range 19-18 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 17-14 acronym DTYPE description Device Type: Bios sets these bits according to information read pertaining to the DIMMs installed bit 17: single or dual rank DIMM (0=single rank per DIMM) bit 16: DDR2 (0=DDR2) bit 15: 32 or 64 bit DDR populated (0=64bits) bit 14: unbuffered or registered DIMM (0=unbuffered) sticky N reset [ 0000b ] 0h access RW ---------------- range 13-12 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 11-10 acronym DWODD description Device Width for odd-numbered row: Functionality and encoding is exactly the same as DWEVEN. This value should be set to exactly the same as DWEVEN. sticky N reset [ 01b ] 1h access RW ---------------- range 9-6 acronym DIMMTECH_ODD description DIMM technology for odd-numbered row. Functionality and encoding is exactly the same as DIMMTECH_EVEN (bits 3:0) sticky N reset [ 0100b ] 4h access RW ---------------- range 5-4 acronym DWEVEN description Device Width for even-numbered row: BIOS sets this bit according to the width of the DDR2 SDRAM devices populated in this row. This is used to determine the page size and the DQS to DQ signal mapping. 00 = Reserved 01 = x8 DDR2 (1 strobe pair per byte) 10 = Reserved 11 = Reserved sticky N reset [ 01b ] 1h access RW ---------------- range 3-0 acronym DIMMTECH_EVEN description DIMM technology for even-numbered row: BIOS sets this bit according to the density of the DDR devices populated in this row. This is used along with the device width and the DTYPE to determine the page size and the DQS to DQ signal mapping. 0000 = reserved 0011 = 2Gb DIMM 0100 = 1Gb DIMM 0101 = 512Mb DIMM 0110 = 256Mb DIMM others - reserved sticky N reset [ 0101b ] 5h access RW ============================================================ 78h DRT0 table_ref 16-45 offset 78h reg_name DRT0 recurring None reg_base_name DRT0 title_desc DRAM Timing Register 0 description None view PCI bar Configuration offset_start 78h offset_end 7bh power_well Core size 32 default 242ad280h bus_device_function 0:0:0 ---------------- range 31-29 acronym BTBRWTA description Back-To-Back Read-Write Turn Around: This field determines the minimum number of CMDCLK on the DQ bus between Read-Write commands. It applies to RD-WR pairs to any destinations (in same or different rows). The purpose of this bit is to control the turnaround time on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK's that will be inserted between read write commands. Command EncodingClocks per Frequency 0000 0011 0102 0113 1004 1015 1106 1117 sticky N reset [ 001b ] 1h access RW ---------------- range 28-26 acronym BTBRTA description Back To Back Read Turn Around: This field determines the minimum number of CMDCLK on the DQ bus between two reads destined to different ranks. The purpose of these bits is to control the turnaround time on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK's that will be inserted between read write commands. Command EncodingClocks per Frequency 0000 0011 0102 0113 1004 1015 1106 1117 sticky N reset [ 001b ] 1h access RW ---------------- range 25-23 acronym BBWRTA description Back to Back Write-Read turn around: This field determines the minimum number of CMDCLK on the DQ bus between Write-Read commands. The purpose of these 3 bits are to control the turnaround time on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK's that will be inserted between read write commands. Command clocks apart based on the following encoding: Command EncodingClocks per Frequency 0000 0011 0102 0113 1004 1015 1106 1117 sticky N reset [ 000b ] 0h access RW ---------------- range 22-20 acronym Trrd description Row Delay: The required row delay period between two activate commands accessing the same cs of a DIMM in tCK cycles. JEDEC recommendation for this parameter is based on the device width. x8 devices = 7.5ns Number of CMDCLK Encodingdelays 000No delay 0011 0102 0113 1004 1015 1106 1117 sticky N reset [ 010b ] 2h access RW ---------------- range 19-17 acronym Twr description Write Recovery Delay: The required write recovery delay before being able to issue a precharge to the same page accessing the same cs/bank of a DIMM in tCK cycles. JEDEC recommendation for this parameter is 15ns min. Number of CMDCLK Encodingdelays 0002 0013 0104 0115 1006 1017 1108 1119 sticky N reset [ 101b ] 5h access RW ---------------- range 16-12 acronym Trc description This bit controls the number of DRAM clocks to enforce as the RAS cycle time. Number of CMDCLK Encodingdelays 0000011 0000112 0001013 0001114 0010015 0010116 0011017 0011118 0100019 0100120 0101021 0101122 0110023 0110124 0111025 0111126 1000027 1000128 1001029 OthersReserved sticky N reset [ 01101b ] 0dh access RW ---------------- range 11-9 acronym Trcd description DRAM RAS# to CAS# delay: This bits controls the number of clocks inserted between a row activate command and a read or write command to that row Number of EncodingCMDCLK delays 0003 0014 0105 0116 OthersReserved sticky N reset [ 001b ] 1h access RW ---------------- range 8-6 acronym Trp description DRAM RAS# Precharge: Time: the number of clock cycles needed to terminate access (precharge) to an open row of memory, and open access (activate) to the next row. Number of EncodingCMDCLK delays 0003 0014 0105 0116 OthersReserved sticky N reset [ 010b ] 2h access RW ---------------- range 5-3 acronym CL description CAS# Latency: The number of clocks between the rising edge used by DRAMS to sample the Read Command and the rising edge that is used by the DRAM to drive read data. DDR2 JEDEC Spec: Write latency (WL) is defined by a read latency (RL) minus one. Please refer to the DDR2 JEDEC Spec for more details. Number of EncodingCMDCLK delays 0003 0014 0105 0116 OthersReserved sticky N reset [ 000b ] 0h access RW ---------------- range 2-0 acronym PRGRPD description Programmable Read Pointer Delay: This bit field determines the read delay, which is based on both DIMM topology and technology. The round trip timing budget has been estimated to be about 11.5 ns. Since an encoding of "000" means less than one command clock, the encoding values in this table refer to additional delays beyond one command clock. Note that the PRGRPD encoding shown below is for 4 bits. The 4 bits are formed by concatenating DRT1[0] and DRT0[2:0]. Please refer to Section 16.1.1.42 for details on the DRT1 register. PRGRPD[3:0] EncodingNumber of CMDCLK delaysDRT1[0], DRT0[2:0] 00000 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 Others Reserved sticky N reset [ 000b ] 0h access RW ============================================================ 64h DRT1 table_ref 16-46 offset 64h reg_name DRT1 recurring None reg_base_name DRT1 title_desc DRAM timing Register 1 description None view PCI bar Configuration offset_start 64h offset_end 67h power_well Core size 32 default 12110000h bus_device_function 0:0:0 ---------------- range 31-28 acronym tRAS description (Time for activation / RAS Active Strobe): time to activate a row of a bank (minimum time bank stays open before it can be closed/precharged again) SW needs to program this parameter based on the DDR speed as shown in the table below. Note however that the HW will use a different tRAS value when the DDR commands are generated by the Mbist Engine. During all other modes the controller will use the tRAS value programmed in this field. DDR # of CMD Tras value EncodingSpeedclksused by Mbist 40000008 (40ns)12 40000019 (45ns)12 533010012 (45ns)12 667011115 (45ns)15 800100016 (40ns)18 800101018 (40ns)18 sticky N reset [ 0001b ] 1h access RW ---------------- range 27-25 acronym tRTP description RAS to Precharge (needed to calculate Read AutoPrecharge delay) Number of EncodingCMDCLK delays 0002 0013 0104 0115 OthersReserved sticky N reset [ 001b ] 1h access RW ---------------- range 24-20 acronym tFAW description 8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW(ns) by tCK(ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command. This field is not valid for 4 banks device technologies like 256Mb x8 and 512 x8. JEDEC recommendations: 1KB Page size = 37.5ns 2KB Page size = 50ns Number of CMDCLK Encodingdelays 00000No restriction 000017 000108 000119 0010010 0010111 0011012 0011113 0100014 0100115 0101016 0101117 0110018 0110119 0111020 OthersReserved sticky N reset [ 00001b ] 01h access RW ---------------- range 19-18 acronym tCCD description CAS to CAS Delay Number of EncodingCMDCLK delays 002 104 OthersReserved Note: set tCCD to 2 clock delay for Burst of 4 (64 bit wide data interface) or set tCCD to 4 clock delay for Burst of 8 (32 bit wide data interface). sticky N reset [ 00b ] 0h access RW ---------------- range 17-15 acronym tWTR description Internal Write to Read command delay, at least 2 x tCK and independent of operating frequency JEDEC recommendations for DDR2 400MTS = 10ns Others = 7.5ns Number of EncodingCMDCLK delays 000No Delay 0011 0102 0113 1004 1015 Others Reserved sticky N reset [ 010b ] 2h access RW ---------------- range 14-13 acronym BLEN description Burst length EncodingBurst Length 4 00(DDR2 64 bit data width) 8 (DDR2 32 bit data 01width) sticky N reset [ 00b ] 0h access RW ---------------- range 12 acronym 2Tor1T description 2T or 1T timing on the command bus to DRAM devices. EncodingTiming 01T 12T sticky N reset [ 0b ] 0h access RW ---------------- range 11-4 acronym NOPCNT description Programmable NOP insertion: Number of NOPs will be inserted between read/write commands to slow down Membist activities in the same page. Up to 255 clocks NOPs can be programmed to insert delay between read/write commands. If NOPs delay is programmable less than the required DRAM timing, Overall NOP delay from command to command will not be seen. sticky N reset 00000000b [ 00h ] access RW ---------------- range 3-1 acronym BTBWTA description Back-To-Back Write Turn Around: This field determines the data bubble duration between write data bursts. It applies to WR-WR pairs to different ranks, and is only expected to be used in DDR2 mode with ODT enabled in the event that ODT selections must change between ranks. The purpose of this field is to control the data burst spacing on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK's that will be inserted between read write commands. Number of CMDCLK Encodingdelays 0000 0011 0102 0113 1004 1015 1106 1117 sticky N reset [ 000b ] 0h access RW ---------------- range 0 acronym PRGRPD_4 description Bit[3] of the Programmable Read Pointer Delay field. Please refer to DRT0[2:0] for more details on this bit field (Section 16.1.1.41). sticky N reset [ 0b ] 0h access RW ============================================================ 7ch DRC table_ref 16-47 offset 7ch reg_name DRC recurring None reg_base_name DRC title_desc DRAM Controller Mode Register description None view PCI bar Configuration offset_start 7ch offset_end 7fh power_well Core size 32 default 00000002h bus_device_function 0:0:0 ---------------- range 31 acronym CKE1 description This bit controls the value that will be driven on the CKE[1] pin. Note however that CKEPNM bit in this CSR can override and force low the state of both CKE[1:0] pins regardless of the state of this bit. BIOS can write to this CSR bit to directly control the state of the CKE pin. HW will update the state of this bit based on self-refresh exit command. 0 Drive CKE[1] low, de-activates DRAM devices 1 Drive CKE[1] asserted, activates DRAM devices sticky Y reset [ 0b ] 0h access RW ---------------- range 30 acronym CKE0 description This bit controls the value that will be driven on the CKE[0] pin. Note however that CKEPNM bit in this CSR can override and force low the state of both CKE[1:0] pins regardless of the state of this bit. BIOS can write to this CSR bit to directly control the state of the CKE pin. HW will update the state of this bit based on self-refresh exit command. 0 Drive CKE[0] low, de-activates DRAM devices 1 Drive CKE[0] asserted, activates DRAM devices sticky Y reset [ 0b ] 0h access RW ---------------- range 29 acronym IC description 0 = Initialization Complete: This bit is used for communication of software state between the memory controller and the BIOS. DRAM interface has not been initialized.1 = DRAM interface has been initialized. sticky N reset [ 0b ] 0h access RW ---------------- range 28-22 acronym Reserved description Reserved sticky N reset [ 0000000b ] 00h access RO ---------------- range 21-20 acronym DDIM description DRAM Data Integrity Mode: These bits select DRAM data integrity modes. When in non-ECC mode no ECC correction is done and no ECC errors are logged in the FERR/NERR registers. 00 Non-ECC mode 01 ECC enabled 10 Reserved 11 Reserved sticky N reset [ 00b ] 0h access RW ---------------- range 19-14 acronym Reserved description Reserved sticky N reset [ 000000b ] 00h access RO ---------------- range 13 acronym HLDDIS description Command/address hold disable Disabling hold will allow the address and bank address pins to revert to all zeros during idle cycles. When hlddis is clear, the addresses retain the value of the last non-idle command cycle in order to reduce switching on the bus. 0 = disabled, 1 enabled sticky Y reset [ 0b ] 0h access RW ---------------- range 12 acronym CADIS description DDR Command/address pin output disable: This bit controls Address, bank address, CAS, RAS, WE. 0 = Enabled1 = Disabled sticky Y reset [ 0b ] 0h access RW ---------------- range 11-10 acronym CSDIS description DDR Chip select output disable bit[11] = CS[1] bit[10] = CS[0] 0 = Enabled1 = Disabled sticky Y reset [ 00b ] 0h access RW ---------------- range 9 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 8-7 acronym Reserved_2 description Reserved_RW_Sticky sticky Y reset [ 00b ] 0h access RW ---------------- range 6-5 acronym ODTDIS description DRAM ODT Disable: bit[5] = ODT[0] bit[6] = ODT[1] 0 = Enables the use of ODT when running1 = Disables (tristates) the use of ODT when running sticky Y reset [ 00b ] 0h access RW ---------------- range 4 acronym CKEPNM description CKE pin mode: 0 = Force low. Forces the state of CKE[1:0] low. When this bit is cleared it over-rides all functionality that drives the CKE pin and forces it low. SW needs to set this bit for normal operation 1 = Enable CKE[1:0]. BIOS will set this bit to a 1 for normal operating mode. sticky Y reset [ 0b ] 0h access RW ---------------- range 3-0 acronym DS description The PLL only supports one update of ratio (the lower nibble of this register). This register defaults to DDR2-400 This field reflects BIOS selection of DDR speed, which may have been "down-binned" due to fuse settings (see SDRC.FUSESPEED) DDR DDR CMDData EncodingSpeed Freq (MT/s)(Mhz) 0x10400200Default 0x00533266 0111667333 0101800400 ReserveOthersd sticky Y reset [ 0010b ] 2h access RWO ============================================================ 84h ECCDIAG table_ref 16-48 offset 84h reg_name ECCDIAG recurring None reg_base_name ECCDIAG title_desc ECC Detection/Correction Diagnostic Register description None view PCI bar Configuration offset_start 84h offset_end 87h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-21 acronym Reserved description Reserved sticky N reset [ 00000000000b ] 000h access RO ---------------- range 20 acronym FECCDT description Flip ECC on all data transfers: Flip the designated ECC bits (bits 15:00) on all data transfers to DRAM. If a cacheline is in progress when this register is written, wait until the start of the next cacheline to flip parity bits. Note that if FECCDT and MEMPEN is set and a bad parity is detected, the M_unit will poison and flip the ECC bits. sticky N reset [ 0b ] 0h access RW ---------------- range 19 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 18 acronym MEMPEN description Memory Poison Enable: Allows for propagation of data errors not initiated by this feature to DRAM. Error injection via bit 20 is possible regardless of this bit setting. The setting of this bit has no effect on the reporting or logging of data errors. 0 = Error poisoning is disabled, data errors are not propagated, meaning that only good ECC is generated ECC mode even when bad parity is detected on its interface.1 = Error poisoning enabled when in ECC mode. The memory controller will poison the write data to DRAM when it detects a parity error on its interface. sticky N reset [ 0b ] 0h access RW ---------------- range 17-16 acronym DPRSL description Data pair selector: This two-bit field selects which pair of quad-words in a cache line the inversion vector is applied against. Regardless of what operational mode the memory subsystem is in, this field always applies to the same QW pair. QW0 corresponds to data bits 63:00, QW1 to [127:64] ? and QW7 corresponds to [511:448] 00QW0 and QW1 01QW2 and QW3 10QW4 and QW5 11QW6 and QW7 sticky N reset [ 00b ] 0h access RW ---------------- range 15-0 acronym ECCBIN description ECC bit invert vector: This vector operates individually for every ECC bit in the selected High or Low ECC block, during writes to DRAM. For all k between 0 and 15, when bit (k) set to 1, the value of the k ECC bit (which corresponds with the k data byte lane) is inverted. Otherwise, the value the k ECC bit is not affected. In other words, bits 15:08 are applied to the ECC vector of the high Qword in the selected pair, and bits 07:00 are applied to the ECC vector of the low Qword in the selected pair. For Example: Data Pair Selector bits 17:16 = 00ECC bit invert vector bits 15:08 are applied to the ECC vector for QW1ECC bit invert vector bits 07:00 are applied to the ECC vector for QW0 sticky N reset 0000000000000000b [ 0000h ] access RW ============================================================ 88h SDRC table_ref 16-49 offset 88h reg_name SDRC recurring None reg_base_name SDRC title_desc DDR SDRAM Secondary Control Register description None view PCI bar Configuration offset_start 88h offset_end 8bh power_well Core size 32 default 00000002h bus_device_function 0:0:0 ---------------- range 31-30 acronym ODTZENA1 description On Die Termination Enable: These bits enable the EP80579 on die termination. ODT control for the DQ[71:64]/DQS[8] (ECC byte) buffers on the inbound read path. EncodingODT 00Disabled 0160 ohms 10120 ohms OthersReserved sticky Y reset [ 00b ] 0h access RW ---------------- range 29-28 acronym ODTZENA description On Die Termination Enable: These bits enable the EP80579 on die termination. ODT for the DQ[63:0]/DQS[7:0] buffers on the inbound read path EncodingODT 00Disabled 0160 ohms 10120 ohms OthersReserved sticky Y reset [ 00b ] 0h access RW ---------------- range 27-26 acronym Reserved description Reserved sticky Y reset [ 00b ] 0h access ---------------- range 25-22 acronym Reserved description Reserved sticky N reset None access RW ---------------- range 21-20 acronym FUSESPEED description Fuse Speed - Read only copy of the DDR speed fuse setting 00b - DDR-800 MTS 01b - DDR-667 MTS 10b - DDR-533 MTS 11b - DDR-400 MTS sticky N reset None access RO ---------------- range 19-17 acronym DRRIRR description Demand Scrub Retry (DRR) Injection Rate Regulator: This field determines the minimum rate at which DRRs will be scheduled to the DRAM. If multiple DRR's are pending in the MC, they will be issued to the DRAM spaced apart by at least DRRIRR by the hardware. 000b - 4 DDR controller clock cycles (Default) Others - Reserved The only supported/validated value is 000b. Note:This feature should not be confused with DED retry feature that is not support by the EP80579. sticky N reset [ 000b ] 0h access RW ---------------- range 16 acronym DDRDIS description Demand Scrub Retry (DRR) Disable: This bit by default is set to 0 to enable the demand scrub retry feature. When enabled any demand scrub writes that do not get scheduled to DRAM will be retried. When this bit is set, demand scrubs that are dropped will not be retried. Note:This feature should not be confused with DED retry feature that is not support by the EP80579. sticky N reset [ 0b ] 0h access RW ---------------- range 15-12 acronym SCH_WGT description Controls for weighted round robin scheduling when both IA and AIOC requests are posted for accessing the same bank. Selects the number of IA transfers consecutively selected instead of AIOC transfers when requests are posted from both, and from the same bank. Works in conjunction with eight 2 bit counter, one for each bank, which indicates how many IA transfers, from each bank, have been selected since the last AIOC transfer was selected form that bank. xx00 = choose AIOC command if AIOC and IA are both present, and the last 1 command selected was IA. If no IA commands are present, choose AIOC and reset 2 bit bank count of IA transfers for the selected bank. xx01 = choose AIOC command if AIOC and IA are both present, and the last 2 commands selected were IA. If no IA commands are present, choose AIOC and reset 2 bit bank count of IA transfers for the selected bank xx11 = choose AIOC command if AIOC and IA are both present, and the last 3 commands selected were IA. If no IA commands are present, choose AIOC and reset 2 bit bank count of IA transfers for the selected bank Otherwise = reserved sticky N reset [ 0000b ] 0h access RW ---------------- range 11 acronym mu_enable_aioccmd description Enable scheduler to pass AIOC transfers to DDR sticky N reset [ 0b ] 0h access RW ---------------- range 10 acronym mu_enable_bcmd description Enable scheduler to pass IMCH transfers to DDR sticky N reset [ 0b ] 0h access RW ---------------- range 9 acronym mu_enable_eccrrwcmd description Enable scheduler to pass internally generated demand scrubs (upon detection of single bit ECC error) transfers to DDR. Please also refer SDRC.DDRDIS for the Demand Scrub Retry Feature. In order to ensure that no demand scrubs are dropped, the DRR feature should be enabled. sticky N reset [ 0b ] 0h access RW ---------------- range 8 acronym mu_enable_bscrubcmd description Enable scheduler to pass internally generated background scrub transfers to DDR sticky N reset [ 0b ] 0h access RW ---------------- range 7-0 acronym ASU_CMDQSIZE description Size of command queue available to ASU The Scheduler implements a shared Command Queue which is nominally 64 entries deep. This queue is shared between ASU and IA traffic. In order to reserve some queue entries for IA commands only, software is able to set an upper limit on the number of ASU commands that can occupy this queue. If the number of ASU commands exceeds this programmed value, subsequent AIOC commands may be backed off by the memory controller, until ASU commands drain to DDR, and the number in the command queue, once again, falls below the programmed value. Recommended value is 0x30. Do not set this field to 0. sticky N reset [ 00000010b ] 02h access RW ============================================================ 8ch CKDIS table_ref 16-50 offset 8ch reg_name CKDIS recurring None reg_base_name CKDIS title_desc CK/CK# Clock Disable Register description None view PCI bar Configuration offset_start 8ch offset_end 8ch power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-6 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 5-0 acronym CKDIS description CK/CK# Disable (Sticky) Each bit corresponds to a pair of CK pins. Default is enabled.0 = Enable CK signals 1 = Disable CK signals. When disabled, the CK/CK# signals are tristated. Bit 5: Enable/Disable CK[5]/CK#[5] Bit 4: Enable/Disable CK[4]/CK#[4] Bit 3: Enable/Disable CK[3]/CK#[3] Bit 2: Enable/Disable CK[2]/CK#[2] Bit 1: Enable/Disable CK[1]/CK#[1] Bit 0: Enable/Disable CK[0]/CK#[0] sticky Y reset [ 000000b ] 00h access RW ============================================================ 8dh CKEDIS table_ref 16-51 offset 8dh reg_name CKEDIS recurring None reg_base_name CKEDIS title_desc CKE Clock Enable Register description None view PCI bar Configuration offset_start 8dh offset_end 8dh power_well Core size 8 default 00h bus_device_function 0:0:0 ---------------- range 7-3 acronym Reserved description Reserved sticky N reset [ 00000b ] 00h access RO ---------------- range 2 acronym CKE1DIS description CKE1 Disable (Sticky) Bit corresponds CKE[1] pin. Default is enabled. 1 = Disable CKE[1] signals 0 = Enable CKE[1] signals. When disabled, the CKE[1] pin is tristated. sticky Y reset [ 0b ] 0h access RW ---------------- range 1 acronym Reserved description Reserved sticky N reset [ 0b ] 0h access RO ---------------- range 0 acronym CKE0DIS description CKE0 Disable (Sticky) Bit controls CKE[0] pin. Default is enabled. 1 = Disable CKE[0] signals 0 = Enable CKE[0] signals. When disabled, the CKE[0] pin is tristated. sticky Y reset [ 0b ] 0h access RW ============================================================ 90h SPARECTL table_ref 16-52 offset 90h reg_name SPARECTL recurring None reg_base_name SPARECTL title_desc SPARE Control Register description None view PCI bar Configuration offset_start 90h offset_end 93h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-24 acronym DEDEPV description DED error prescale value: Prescale value ranges from 0-255. sticky Y reset 00000000b [ 00h ] access RW ---------------- range 23-16 acronym SECEPV description SEC error prescale value: Prescale value ranges from 0-255. sticky Y reset 00000000b [ 00h ] access RW ---------------- range 15-12 acronym DEDEPU description DED error prescale unit: 0000 Never 0001 1 ?s 0010 1 ms 0011 1 s 0100 1 minute 0101 1 hour 0110 1 day 0111 1 week 1XXX Never sticky Y reset [ 0000b ] 0h access RW ---------------- range 11-8 acronym SECEPU description SEC error prescale unit: 0000 Never 0001 1 ?s 0010 1 ms 0011 1 s 0100 1 minute 0101 1 hour 0110 1 day 0111 1 week 1XXX Never sticky Y reset [ 0000b ] 0h access RW ---------------- range 7-0 acronym Reserved description Reserved sticky N reset 00000000b [ 00h ] access RO ============================================================ b0h DDR2ODTC table_ref 16-53 offset b0h reg_name DDR2ODTC recurring None reg_base_name DDR2ODTC title_desc DDR2 ODT Control Register description None view PCI bar Configuration offset_start b0h offset_end b3h power_well Core size 32 default 00000000h bus_device_function 0:0:0 ---------------- range 31-14 acronym Reserved description Reserved sticky N reset 000000000000000000b [ 00000h ] access RO ---------------- range 13-12 acronym R1ODTWR description R1ODTWR: Value for logical ODT[1:0] for the case of write access to logical rank 1. sticky N reset [ 00b ] 0h access RW ---------------- range 11-10 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 9-8 acronym R1ODTRD description R1ODTRD:Value for logical ODT[1:0] for the case of read access to logical rank 1. sticky N reset [ 00b ] 0h access RW ---------------- range 7-6 acronym Reserved description Reserved sticky N reset [ 00b ] 0h access RO ---------------- range 5-4 acronym R0ODTWR description R0ODTWR. Value for logical ODT[1:0] for the case of write access to logical rank 0. sticky N reset [ 00b ] 0h access RW ---------------- range 3-2 acronym Reserved description sticky N reset [ 00b ] 0h access RO ---------------- range 1-0 acronym R0ODTRD description R0ODTRD. Value for logical ODT[1:0] for the case of read access to logical rank 0. sticky N reset [ 00b ] 0h access RW