WWW unhandled (1438, TE_Id(text=u'GbE0: Aux ', top=332, left=488, width=40, height=8)) ### ('37-25', 'CTRL',
) WWW unhandled (1438, TE_Id(text=u'Core', top=346, left=488, width=16, height=8)) ### ('37-25', 'CTRL',
) WWW unhandled (1439, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-25', 'CTRL',
) WWW unhandled (1439, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-25', 'CTRL',
) WWW unhandled (1440, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-25', 'CTRL',
) WWW unhandled (1440, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-25', 'CTRL',
) WWW unhandled (1441, TE_Id(text=u'GbE0: Aux ', top=268, left=496, width=40, height=8)) ### ('37-26', 'STATUS',
) WWW unhandled (1441, TE_Id(text=u'Core', top=282, left=496, width=16, height=8)) ### ('37-26', 'STATUS',
) WWW unhandled (1442, TE_Id(text=u'GbE0: Aux ', top=268, left=489, width=40, height=8)) ### ('37-27', 'CTRL_EXT',
) WWW unhandled (1442, TE_Id(text=u'Core', top=282, left=489, width=16, height=8)) ### ('37-27', 'CTRL_EXT',
) WWW unhandled (1443, TE_Id(text=u'GbE0: Aux ', top=211, left=497, width=40, height=8)) ### ('37-27', 'CTRL_EXT',
) WWW unhandled (1443, TE_Id(text=u'Core', top=225, left=497, width=16, height=8)) ### ('37-27', 'CTRL_EXT',
) WWW unhandled (1444, TE_Id(text=u'GbE0: Aux ', top=268, left=488, width=40, height=8)) ### ('37-28', 'CTRL_AUX',
) WWW unhandled (1444, TE_Id(text=u'Core', top=282, left=488, width=16, height=8)) ### ('37-28', 'CTRL_AUX',
) WWW unhandled (1445, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-28', 'CTRL_AUX',
) WWW unhandled (1445, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-28', 'CTRL_AUX',
) WWW unhandled (1446, TE_Id(text=u'GbE0: Aux ', top=247, left=488, width=40, height=8)) ### ('37-29', 'EEPROM_CTRL',
) WWW unhandled (1446, TE_Id(text=u'Core', top=261, left=488, width=16, height=8)) ### ('37-29', 'EEPROM_CTRL',
) WWW unhandled (1447, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-29', 'EEPROM_CTRL',
) WWW unhandled (1447, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-29', 'EEPROM_CTRL',
) WWW unhandled (1448, TE_Id(text=u'GbE0: Aux ', top=247, left=488, width=40, height=8)) ### ('37-30', 'EEPROM_RR',
) WWW unhandled (1448, TE_Id(text=u'Core', top=261, left=488, width=16, height=8)) ### ('37-30', 'EEPROM_RR',
) WWW unhandled (1449, TE_Id(text=u'GbE0: Aux ', top=431, left=496, width=40, height=8)) ### ('37-31', 'FCAL',
) WWW unhandled (1449, TE_Id(text=u'Core', top=445, left=496, width=16, height=8)) ### ('37-31', 'FCAL',
) WWW unhandled (1450, TE_Id(text=u'0x00000100.', top=340, left=130, width=47, height=8)) ### ('37-32', 'FCAH',
) WWW unhandled (1450, TE_Id(text=u'GbE0: Aux ', top=434, left=488, width=40, height=8)) ### ('37-32', 'FCAH',
) WWW unhandled (1450, TE_Id(text=u'Core', top=448, left=488, width=16, height=8)) ### ('37-32', 'FCAH',
) WWW unhandled (1450, TE_Id(text=u'This register must be programmed with ', top=333, left=130, width=142, height=8)) ### ('37-32', 'FCAH', ) WWW unhandled (1451, TE_Id(text=u'GbE0: Aux ', top=390, left=496, width=40, height=8)) ### ('37-33', 'FCT', <HEADER>) WWW unhandled (1451, TE_Id(text=u'Core', top=404, left=496, width=16, height=8)) ### ('37-33', 'FCT', <HEADER>) WWW unhandled (1452, TE_Id(text=u'GbE0: Aux ', top=268, left=488, width=40, height=8)) ### ('37-34', 'VET', <HEADER>) WWW unhandled (1452, TE_Id(text=u'Core', top=282, left=488, width=16, height=8)) ### ('37-34', 'VET', <HEADER>) WWW unhandled (1452, TE_Id(text=u'GbE0: Aux ', top=585, left=488, width=40, height=8)) ### ('37-35', 'FCTTV', <HEADER>) WWW unhandled (1452, TE_Id(text=u'Core', top=599, left=488, width=16, height=8)) ### ('37-35', 'FCTTV', <HEADER>) WWW unhandled (1453, TE_Id(text=u'GbE0: Core ', top=339, left=496, width=43, height=8)) ### ('37-36', 'PBA', <HEADER>) WWW unhandled (1453, TE_Id(text=u'Core', top=353, left=496, width=16, height=8)) ### ('37-36', 'PBA', <HEADER>) WWW unhandled (1454, TE_Id(text=u'GbE0: Aux ', top=343, left=488, width=40, height=8)) ### ('37-37', 'ICR0', <HEADER>) WWW unhandled (1454, TE_Id(text=u'Core', top=357, left=488, width=16, height=8)) ### ('37-37', 'ICR0', <HEADER>) WWW unhandled (1455, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-37', 'ICR0', <HEADER>) WWW unhandled (1455, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-37', 'ICR0', <HEADER>) WWW unhandled (1456, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-37', 'ICR0', <HEADER>) WWW unhandled (1456, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-37', 'ICR0', <HEADER>) WWW unhandled (1457, TE_Id(text=u'GbE0: Aux ', top=288, left=496, width=40, height=8)) ### ('37-38', 'ITR0', <HEADER>) WWW unhandled (1457, TE_Id(text=u'Core', top=302, left=496, width=16, height=8)) ### ('37-38', 'ITR0', <HEADER>) WWW unhandled (1458, TE_Id(text=u'GbE0: Aux ', top=288, left=488, width=40, height=8)) ### ('37-39', 'ICS0', <HEADER>) WWW unhandled (1458, TE_Id(text=u'Core', top=302, left=488, width=16, height=8)) ### ('37-39', 'ICS0', <HEADER>) WWW unhandled (1459, TE_Id(text=u'GbE0: Aux ', top=347, left=496, width=40, height=8)) ### ('37-40', 'IMS0', <HEADER>) WWW unhandled (1459, TE_Id(text=u'Core', top=361, left=496, width=16, height=8)) ### ('37-40', 'IMS0', <HEADER>) WWW unhandled (1460, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-40', 'IMS0', <HEADER>) WWW unhandled (1460, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-40', 'IMS0', <HEADER>) WWW unhandled (1460, TE_Id(text=u'GbE0: Aux ', top=561, left=488, width=40, height=8)) ### ('37-41', 'IMC0', <HEADER>) WWW unhandled (1460, TE_Id(text=u'Core', top=575, left=488, width=16, height=8)) ### ('37-41', 'IMC0', <HEADER>) WWW unhandled (1461, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-41', 'IMC0', <HEADER>) WWW unhandled (1461, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-41', 'IMC0', <HEADER>) WWW unhandled (1462, TE_Id(text=u'GbE0: Aux ', top=319, left=488, width=40, height=8)) ### ('37-42', 'ICR1', <HEADER>) WWW unhandled (1462, TE_Id(text=u'Core', top=333, left=488, width=16, height=8)) ### ('37-42', 'ICR1', <HEADER>) WWW unhandled (1463, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-42', 'ICR1', <HEADER>) WWW unhandled (1463, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-42', 'ICR1', <HEADER>) WWW unhandled (1464, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-42', 'ICR1', <HEADER>) WWW unhandled (1464, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-42', 'ICR1', <HEADER>) WWW unhandled (1464, TE_Id(text=u'GbE0: Aux ', top=564, left=488, width=40, height=8)) ### ('37-43', 'ICS1', <HEADER>) WWW unhandled (1464, TE_Id(text=u'Core', top=578, left=488, width=16, height=8)) ### ('37-43', 'ICS1', <HEADER>) WWW unhandled (1465, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-43', 'ICS1', <HEADER>) WWW unhandled (1465, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-43', 'ICS1', <HEADER>) WWW unhandled (1466, TE_Id(text=u'GbE0: Aux ', top=347, left=488, width=40, height=8)) ### ('37-44', 'IMS1', <HEADER>) WWW unhandled (1466, TE_Id(text=u'Core', top=361, left=488, width=16, height=8)) ### ('37-44', 'IMS1', <HEADER>) WWW unhandled (1467, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-44', 'IMS1', <HEADER>) WWW unhandled (1467, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-44', 'IMS1', <HEADER>) WWW unhandled (1467, TE_Id(text=u'GbE0: Aux ', top=573, left=496, width=40, height=8)) ### ('37-45', 'IMC1', <HEADER>) WWW unhandled (1467, TE_Id(text=u'Core', top=587, left=496, width=16, height=8)) ### ('37-45', 'IMC1', <HEADER>) WWW unhandled (1468, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-45', 'IMC1', <HEADER>) WWW unhandled (1468, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-45', 'IMC1', <HEADER>) WWW unhandled (1469, TE_Id(text=u'GbE0: Aux ', top=319, left=496, width=40, height=8)) ### ('37-46', 'ICR2', <HEADER>) WWW unhandled (1469, TE_Id(text=u'Core', top=333, left=496, width=16, height=8)) ### ('37-46', 'ICR2', <HEADER>) WWW unhandled (1470, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-46', 'ICR2', <HEADER>) WWW unhandled (1470, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-46', 'ICR2', <HEADER>) WWW unhandled (1471, TE_Id(text=u'GbE0: Aux ', top=288, left=496, width=40, height=8)) ### ('37-47', 'ICS2', <HEADER>) WWW unhandled (1471, TE_Id(text=u'Core', top=302, left=496, width=16, height=8)) ### ('37-47', 'ICS2', <HEADER>) WWW unhandled (1472, TE_Id(text=u'GbE0: Aux ', top=347, left=488, width=40, height=8)) ### ('37-48', 'IMS2', <HEADER>) WWW unhandled (1472, TE_Id(text=u'Core', top=361, left=488, width=16, height=8)) ### ('37-48', 'IMS2', <HEADER>) WWW unhandled (1473, TE_Id(text=u'GbE0: Aux ', top=318, left=496, width=40, height=8)) ### ('37-49', 'IMC2', <HEADER>) WWW unhandled (1473, TE_Id(text=u'Core', top=332, left=496, width=16, height=8)) ### ('37-49', 'IMC2', <HEADER>) WWW unhandled (1474, TE_Id(text=u'GbE0: Aux ', top=297, left=488, width=40, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1474, TE_Id(text=u'Core', top=311, left=488, width=16, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1475, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1475, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1476, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1476, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1477, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1477, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-50', 'RCTL', <HEADER>) WWW unhandled (1478, TE_Id(text=u'GbE0: Core ', top=339, left=488, width=43, height=8)) ### ('37-51', 'FCRTL', <HEADER>) WWW unhandled (1478, TE_Id(text=u'Core', top=353, left=488, width=16, height=8)) ### ('37-51', 'FCRTL', <HEADER>) WWW unhandled (1479, TE_Id(text=u'GbE0: Core ', top=349, left=496, width=43, height=8)) ### ('37-52', 'FCRTH', <HEADER>) WWW unhandled (1479, TE_Id(text=u'Core', top=363, left=496, width=16, height=8)) ### ('37-52', 'FCRTH', <HEADER>) WWW unhandled (1480, TE_Id(text=u'GbE0: Core ', top=278, left=488, width=43, height=8)) ### ('37-53', 'RDBAL', <HEADER>) WWW unhandled (1480, TE_Id(text=u'Core', top=292, left=488, width=16, height=8)) ### ('37-53', 'RDBAL', <HEADER>) WWW unhandled (1480, TE_Id(text=u'GbE0: Core ', top=537, left=488, width=43, height=8)) ### ('37-54', 'RDBAH', <HEADER>) WWW unhandled (1480, TE_Id(text=u'Core', top=551, left=488, width=16, height=8)) ### ('37-54', 'RDBAH', <HEADER>) WWW unhandled (1481, TE_Id(text=u'GbE0: Core ', top=268, left=496, width=43, height=8)) ### ('37-55', 'RDLEN', <HEADER>) WWW unhandled (1481, TE_Id(text=u'Core', top=282, left=496, width=16, height=8)) ### ('37-55', 'RDLEN', <HEADER>) WWW unhandled (1481, TE_Id(text=u'GbE0: Core ', top=561, left=496, width=43, height=8)) ### ('37-56', 'RDH', <HEADER>) WWW unhandled (1481, TE_Id(text=u'Core', top=575, left=496, width=16, height=8)) ### ('37-56', 'RDH', <HEADER>) WWW unhandled (1482, TE_Id(text=u'GbE0: Core ', top=278, left=488, width=43, height=8)) ### ('37-57', 'RDT', <HEADER>) WWW unhandled (1482, TE_Id(text=u'Core', top=292, left=488, width=16, height=8)) ### ('37-57', 'RDT', <HEADER>) WWW unhandled (1483, TE_Id(text=u'GbE0: Core ', top=228, left=496, width=43, height=8)) ### ('37-58', 'RDTR', <HEADER>) WWW unhandled (1483, TE_Id(text=u'Core', top=242, left=496, width=16, height=8)) ### ('37-58', 'RDTR', <HEADER>) WWW unhandled (1483, TE_Id(text=u'GbE0: Core ', top=614, left=496, width=43, height=8)) ### ('37-59', 'RXDCTL', <HEADER>) WWW unhandled (1483, TE_Id(text=u'Core', top=628, left=496, width=16, height=8)) ### ('37-59', 'RXDCTL', <HEADER>) WWW unhandled (1484, TE_Id(text=u'GbE0: Core ', top=211, left=488, width=43, height=8)) ### ('37-59', 'RXDCTL', <HEADER>) WWW unhandled (1484, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-59', 'RXDCTL', <HEADER>) WWW unhandled (1485, TE_Id(text=u'GbE0: Aux ', top=247, left=496, width=40, height=8)) ### ('37-60', 'RADV', <HEADER>) WWW unhandled (1485, TE_Id(text=u'Core', top=261, left=496, width=16, height=8)) ### ('37-60', 'RADV', <HEADER>) WWW unhandled (1486, TE_Id(text=u'GbE0: Aux ', top=268, left=488, width=40, height=8)) ### ('37-61', 'RSRPD', <HEADER>) WWW unhandled (1486, TE_Id(text=u'Core', top=282, left=488, width=16, height=8)) ### ('37-61', 'RSRPD', <HEADER>) WWW unhandled (1487, TE_Id(text=u'GbE0: Aux ', top=298, left=496, width=40, height=8)) ### ('37-62', 'RXCSUM', <HEADER>) WWW unhandled (1487, TE_Id(text=u'Core', top=312, left=496, width=16, height=8)) ### ('37-62', 'RXCSUM', <HEADER>) WWW unhandled (1488, TE_Id(text=u'GbE0: Aux ', top=297, left=488, width=40, height=8)) ### ('37-63', 'MTA[0-127]', <HEADER>) WWW unhandled (1488, TE_Id(text=u'Core', top=311, left=488, width=16, height=8)) ### ('37-63', 'MTA[0-127]', <HEADER>) WWW unhandled (1488, TE_Id(text=u'GbE0: Aux Gbe1/', top=541, left=477, width=62, height=8)) ### ('37-64', 'RAL[0-15]', <HEADER>) WWW unhandled (1488, TE_Id(text=u'2: Core', top=548, left=477, width=26, height=8)) ### ('37-64', 'RAL[0-15]', <HEADER>) WWW unhandled (1489, TE_Id(text=u'GbE0: Aux Gbe1/', top=297, left=484, width=61, height=8)) ### ('37-65', 'RAH[0-15]', <HEADER>) WWW unhandled (1489, TE_Id(text=u'2: Core', top=304, left=484, width=26, height=8)) ### ('37-65', 'RAH[0-15]', <HEADER>) WWW unhandled (1490, TE_Id(text=u'GbE0: Aux ', top=297, left=477, width=40, height=8)) ### ('37-66', 'VFTA[0-127]', <HEADER>) WWW unhandled (1490, TE_Id(text=u'Core', top=311, left=477, width=16, height=8)) ### ('37-66', 'VFTA[0-127]', <HEADER>) WWW unhandled (1491, TE_Id(text=u'GbE0: Aux ', top=292, left=496, width=40, height=8)) ### ('37-67', 'TCTL', <HEADER>) WWW unhandled (1491, TE_Id(text=u'Core', top=306, left=496, width=16, height=8)) ### ('37-67', 'TCTL', <HEADER>) WWW unhandled (1492, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-67', 'TCTL', <HEADER>) WWW unhandled (1492, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-67', 'TCTL', <HEADER>) WWW unhandled (1493, TE_Id(text=u'GbE0: Aux ', top=258, left=496, width=40, height=8)) ### ('37-68', 'TIPG', <HEADER>) WWW unhandled (1493, TE_Id(text=u'Core', top=272, left=496, width=16, height=8)) ### ('37-68', 'TIPG', <HEADER>) WWW unhandled (1494, TE_Id(text=u'GbE0: Aux ', top=211, left=488, width=40, height=8)) ### ('37-68', 'TIPG', <HEADER>) WWW unhandled (1494, TE_Id(text=u'Core', top=225, left=488, width=16, height=8)) ### ('37-68', 'TIPG', <HEADER>) WWW unhandled (1495, TE_Id(text=u'GbE0: Aux ', top=337, left=496, width=40, height=8)) ### ('37-69', 'AIT', <HEADER>) WWW unhandled (1495, TE_Id(text=u'Core', top=351, left=496, width=16, height=8)) ### ('37-69', 'AIT', <HEADER>) WWW unhandled (1496, TE_Id(text=u'GbE0: Core ', top=278, left=488, width=43, height=8)) ### ('37-70', 'TDBAL', <HEADER>) WWW unhandled (1496, TE_Id(text=u'Core', top=292, left=488, width=16, height=8)) ### ('37-70', 'TDBAL', <HEADER>) WWW unhandled (1496, TE_Id(text=u'GbE0: Core ', top=537, left=488, width=43, height=8)) ### ('37-71', 'TDBAH', <HEADER>) WWW unhandled (1496, TE_Id(text=u'Core', top=551, left=488, width=16, height=8)) ### ('37-71', 'TDBAH', <HEADER>) WWW unhandled (1497, TE_Id(text=u'GbE0: Core ', top=268, left=496, width=43, height=8)) ### ('37-72', 'TDLEN', <HEADER>) WWW unhandled (1497, TE_Id(text=u'Core', top=282, left=496, width=16, height=8)) ### ('37-72', 'TDLEN', <HEADER>) WWW unhandled (1497, TE_Id(text=u'GbE0: Core ', top=581, left=496, width=43, height=8)) ### ('37-73', 'TDH', <HEADER>) WWW unhandled (1497, TE_Id(text=u'Core', top=595, left=496, width=16, height=8)) ### ('37-73', 'TDH', <HEADER>) WWW unhandled (1498, TE_Id(text=u'GbE0: Core ', top=288, left=488, width=43, height=8)) ### ('37-74', 'TDT', <HEADER>) WWW unhandled (1498, TE_Id(text=u'Core', top=302, left=488, width=16, height=8)) ### ('37-74', 'TDT', <HEADER>) WWW unhandled (1499, TE_Id(text=u'GbE0: Core ', top=293, left=496, width=43, height=8)) ### ('37-75', 'TIDV', <HEADER>) WWW unhandled (1499, TE_Id(text=u'Core', top=307, left=496, width=16, height=8)) ### ('37-75', 'TIDV', <HEADER>) WWW unhandled (1500, TE_Id(text=u'GbE0: Core ', top=278, left=488, width=43, height=8)) ### ('37-76', 'TXDCTL', <HEADER>) WWW unhandled (1500, TE_Id(text=u'Core', top=292, left=488, width=16, height=8)) ### ('37-76', 'TXDCTL', <HEADER>) WWW unhandled (1501, TE_Id(text=u'GbE0: Core ', top=211, left=496, width=43, height=8)) ### ('37-76', 'TXDCTL', <HEADER>) WWW unhandled (1501, TE_Id(text=u'Core', top=225, left=496, width=16, height=8)) ### ('37-76', 'TXDCTL', <HEADER>) WWW unhandled (1502, TE_Id(text=u'GbE0: Core ', top=328, left=488, width=43, height=8)) ### ('37-77', 'TADV', <HEADER>) WWW unhandled (1502, TE_Id(text=u'Core', top=342, left=488, width=16, height=8)) ### ('37-77', 'TADV', <HEADER>) WWW unhandled (1504, TE_Id(text=u'GbE0: Core ', top=228, left=488, width=43, height=8)) ### ('37-78', 'TSPMT', <HEADER>) WWW unhandled (1504, TE_Id(text=u'Core', top=242, left=488, width=16, height=8)) ### ('37-78', 'TSPMT', <HEADER>) WWW unhandled (1505, TE_Id(text=u'GbE0: Aux ', top=602, left=496, width=40, height=8)) ### ('37-79', 'CRCERRS', <HEADER>) WWW unhandled (1505, TE_Id(text=u'Core', top=616, left=496, width=16, height=8)) ### ('37-79', 'CRCERRS', <HEADER>) WWW unhandled (1506, TE_Id(text=u'GbE0: Aux ', top=308, left=488, width=40, height=8)) ### ('37-80', 'ALGNERRC', <HEADER>) WWW unhandled (1506, TE_Id(text=u'Core', top=322, left=488, width=16, height=8)) ### ('37-80', 'ALGNERRC', <HEADER>) WWW unhandled (1506, TE_Id(text=u'GbE0: Aux ', top=583, left=488, width=40, height=8)) ### ('37-81', 'RXERRC', <HEADER>) WWW unhandled (1506, TE_Id(text=u'Core', top=597, left=488, width=16, height=8)) ### ('37-81', 'RXERRC', <HEADER>) WWW unhandled (1507, TE_Id(text=u'GbE0: Aux ', top=359, left=496, width=40, height=8)) ### ('37-82', 'MPC', <HEADER>) WWW unhandled (1507, TE_Id(text=u'Core', top=373, left=496, width=16, height=8)) ### ('37-82', 'MPC', <HEADER>) WWW unhandled (1507, TE_Id(text=u'GbE0: Aux ', top=624, left=496, width=40, height=8)) ### ('37-83', 'SCC', <HEADER>) WWW unhandled (1507, TE_Id(text=u'Core', top=638, left=496, width=16, height=8)) ### ('37-83', 'SCC', <HEADER>) WWW unhandled (1508, TE_Id(text=u'GbE0: Aux ', top=288, left=488, width=40, height=8)) ### ('37-84', 'ECOL', <HEADER>) WWW unhandled (1508, TE_Id(text=u'Core', top=302, left=488, width=16, height=8)) ### ('37-84', 'ECOL', <HEADER>) WWW unhandled (1508, TE_Id(text=u'GbE0: Aux ', top=553, left=488, width=40, height=8)) ### ('37-85', 'MCC', <HEADER>) WWW unhandled (1508, TE_Id(text=u'Core', top=567, left=488, width=16, height=8)) ### ('37-85', 'MCC', <HEADER>) WWW unhandled (1509, TE_Id(text=u'GbE0: Aux ', top=268, left=496, width=40, height=8)) ### ('37-86', 'LATECOL', <HEADER>) WWW unhandled (1509, TE_Id(text=u'Core', top=282, left=496, width=16, height=8)) ### ('37-86', 'LATECOL', <HEADER>) WWW unhandled (1509, TE_Id(text=u'GbE0: Aux ', top=533, left=496, width=40, height=8)) ### ('37-87', 'COLC', <HEADER>) WWW unhandled (1509, TE_Id(text=u'Core', top=547, left=496, width=16, height=8)) ### ('37-87', 'COLC', <HEADER>) WWW unhandled (1510, TE_Id(text=u'GbE0: Aux ', top=288, left=488, width=40, height=8)) ### ('37-88', 'DC', <HEADER>) WWW unhandled (1510, TE_Id(text=u'Core', top=302, left=488, width=16, height=8)) ### ('37-88', 'DC', <HEADER>) WWW unhandled (1510, TE_Id(text=u'GbE0: Aux ', top=593, left=488, width=40, height=8)) ### ('37-89', 'TNCRS', <HEADER>) WWW unhandled (1510, TE_Id(text=u'Core', top=607, left=488, width=16, height=8)) ### ('37-89', 'TNCRS', <HEADER>) WWW unhandled (1511, TE_Id(text=u'GbE0: Aux ', top=317, left=496, width=40, height=8)) ### ('37-90', 'CEXTERR', <HEADER>) WWW unhandled (1511, TE_Id(text=u'Core', top=331, left=496, width=16, height=8)) ### ('37-90', 'CEXTERR', <HEADER>) WWW unhandled (1511, TE_Id(text=u'GbE0: Aux ', top=602, left=496, width=40, height=8)) ### ('37-91', 'RLEC', <HEADER>) WWW unhandled (1511, TE_Id(text=u'Core', top=616, left=496, width=16, height=8)) ### ('37-91', 'RLEC', <HEADER>) WWW unhandled (1512, TE_Id(text=u'GbE0: Aux ', top=278, left=488, width=40, height=8)) ### ('37-92', 'XONRXC', <HEADER>) WWW unhandled (1512, TE_Id(text=u'Core', top=292, left=488, width=16, height=8)) ### ('37-92', 'XONRXC', <HEADER>) WWW unhandled (1512, TE_Id(text=u'GbE0: Aux ', top=543, left=488, width=40, height=8)) ### ('37-93', 'XONTXC', <HEADER>) WWW unhandled (1512, TE_Id(text=u'Core', top=557, left=488, width=16, height=8)) ### ('37-93', 'XONTXC', <HEADER>) WWW unhandled (1513, TE_Id(text=u'GbE0: Aux ', top=278, left=496, width=40, height=8)) ### ('37-94', 'XOFFRXC', <HEADER>) WWW unhandled (1513, TE_Id(text=u'Core', top=292, left=496, width=16, height=8)) ### ('37-94', 'XOFFRXC', <HEADER>) WWW unhandled (1513, TE_Id(text=u'GbE0: Aux ', top=543, left=496, width=40, height=8)) ### ('37-95', 'XOFFTXC', <HEADER>) WWW unhandled (1513, TE_Id(text=u'Core', top=557, left=496, width=16, height=8)) ### ('37-95', 'XOFFTXC', <HEADER>) WWW unhandled (1514, TE_Id(text=u'GbE0: Aux ', top=298, left=488, width=40, height=8)) ### ('37-96', 'FCRUC', <HEADER>) WWW unhandled (1514, TE_Id(text=u'Core', top=312, left=488, width=16, height=8)) ### ('37-96', 'FCRUC', <HEADER>) WWW unhandled (1514, TE_Id(text=u'GbE0: Aux ', top=593, left=488, width=40, height=8)) ### ('37-97', 'PRC64', <HEADER>) WWW unhandled (1514, TE_Id(text=u'Core', top=607, left=488, width=16, height=8)) ### ('37-97', 'PRC64', <HEADER>) WWW unhandled (1515, TE_Id(text=u'GbE0: Aux ', top=308, left=496, width=40, height=8)) ### ('37-98', 'PRC127', <HEADER>) WWW unhandled (1515, TE_Id(text=u'Core', top=322, left=496, width=16, height=8)) ### ('37-98', 'PRC127', <HEADER>) WWW unhandled (1515, TE_Id(text=u'GbE0: Aux ', top=603, left=496, width=40, height=8)) ### ('37-99', 'PRC255', <HEADER>) WWW unhandled (1515, TE_Id(text=u'Core', top=617, left=496, width=16, height=8)) ### ('37-99', 'PRC255', <HEADER>) WWW unhandled (1516, TE_Id(text=u'GbE0: Aux ', top=308, left=488, width=40, height=8)) ### ('37-100', 'PRC511', <HEADER>) WWW unhandled (1516, TE_Id(text=u'Core', top=322, left=488, width=16, height=8)) ### ('37-100', 'PRC511', <HEADER>) WWW unhandled (1516, TE_Id(text=u'GbE0: Aux ', top=610, left=488, width=40, height=8)) ### ('37-101', 'PRC1023', <HEADER>) WWW unhandled (1516, TE_Id(text=u'Core', top=624, left=488, width=16, height=8)) ### ('37-101', 'PRC1023', <HEADER>) WWW unhandled (1517, TE_Id(text=u'GbE0: Aux ', top=380, left=496, width=40, height=8)) ### ('37-102', 'PRC1522', <HEADER>) WWW unhandled (1517, TE_Id(text=u'Core', top=394, left=496, width=16, height=8)) ### ('37-102', 'PRC1522', <HEADER>) WWW unhandled (1518, TE_Id(text=u'GbE0: Aux ', top=318, left=488, width=40, height=8)) ### ('37-103', 'GPRC', <HEADER>) WWW unhandled (1518, TE_Id(text=u'Core', top=332, left=488, width=16, height=8)) ### ('37-103', 'GPRC', <HEADER>) WWW unhandled (1518, TE_Id(text=u'GbE0: Aux ', top=583, left=488, width=40, height=8)) ### ('37-104', 'BPRC', <HEADER>) WWW unhandled (1518, TE_Id(text=u'Core', top=597, left=488, width=16, height=8)) ### ('37-104', 'BPRC', <HEADER>) WWW unhandled (1519, TE_Id(text=u'GbE0: Aux ', top=288, left=496, width=40, height=8)) ### ('37-105', 'MPRC', <HEADER>) WWW unhandled (1519, TE_Id(text=u'Core', top=302, left=496, width=16, height=8)) ### ('37-105', 'MPRC', <HEADER>) WWW unhandled (1519, TE_Id(text=u'GbE0: Aux ', top=573, left=496, width=40, height=8)) ### ('37-106', 'GPTC', <HEADER>) WWW unhandled (1519, TE_Id(text=u'Core', top=587, left=496, width=16, height=8)) ### ('37-106', 'GPTC', <HEADER>) WWW unhandled (1520, TE_Id(text=u'GbE0: Aux ', top=328, left=488, width=40, height=8)) ### ('37-107', 'GORCL', <HEADER>) WWW unhandled (1520, TE_Id(text=u'Core', top=342, left=488, width=16, height=8)) ### ('37-107', 'GORCL', <HEADER>) WWW unhandled (1521, TE_Id(text=u'GbE0: Aux ', top=328, left=496, width=40, height=8)) ### ('37-108', 'GORCH', <HEADER>) WWW unhandled (1521, TE_Id(text=u'Core', top=342, left=496, width=16, height=8)) ### ('37-108', 'GORCH', <HEADER>) WWW unhandled (1522, TE_Id(text=u'GbE0: Aux ', top=228, left=488, width=40, height=8)) ### ('37-109', 'GOTCL', <HEADER>) WWW unhandled (1522, TE_Id(text=u'Core', top=242, left=488, width=16, height=8)) ### ('37-109', 'GOTCL', <HEADER>) WWW unhandled (1522, TE_Id(text=u'GbE0: Aux ', top=563, left=488, width=40, height=8)) ### ('37-110', 'GOTCH', <HEADER>) WWW unhandled (1522, TE_Id(text=u'Core', top=577, left=488, width=16, height=8)) ### ('37-110', 'GOTCH', <HEADER>) WWW unhandled (1523, TE_Id(text=u'GbE0: Aux ', top=298, left=496, width=40, height=8)) ### ('37-111', 'RNBC', <HEADER>) WWW unhandled (1523, TE_Id(text=u'Gbe1/2: Core', top=305, left=496, width=48, height=8)) ### ('37-111', 'RNBC', <HEADER>) WWW unhandled (1523, TE_Id(text=u'GbE0: Aux ', top=566, left=492, width=40, height=8)) ### ('37-112', 'RUC', <HEADER>) WWW unhandled (1523, TE_Id(text=u'Gbe1/2: Core', top=573, left=492, width=48, height=8)) ### ('37-112', 'RUC', <HEADER>) WWW unhandled (1524, TE_Id(text=u'GbE0: Aux ', top=298, left=488, width=40, height=8)) ### ('37-113', 'RFC', <HEADER>) WWW unhandled (1524, TE_Id(text=u'Gbe1/2: Core', top=305, left=488, width=48, height=8)) ### ('37-113', 'RFC', <HEADER>) WWW unhandled (1524, TE_Id(text=u'GbE0: Aux ', top=586, left=488, width=40, height=8)) ### ('37-114', 'ROC', <HEADER>) WWW unhandled (1524, TE_Id(text=u'Gbe1/2: Core', top=593, left=488, width=48, height=8)) ### ('37-114', 'ROC', <HEADER>) WWW unhandled (1525, TE_Id(text=u'GbE0: Aux ', top=318, left=496, width=40, height=8)) ### ('37-115', 'RJC', <HEADER>) WWW unhandled (1525, TE_Id(text=u'Gbe1/2: Core', top=325, left=496, width=48, height=8)) ### ('37-115', 'RJC', <HEADER>) WWW unhandled (1526, TE_Id(text=u'GbE0: Aux ', top=228, left=488, width=40, height=8)) ### ('37-116', 'TORL', <HEADER>) WWW unhandled (1526, TE_Id(text=u'Gbe1/2: Core', top=235, left=488, width=48, height=8)) ### ('37-116', 'TORL', <HEADER>) WWW unhandled (1526, TE_Id(text=u'GbE0: Aux ', top=566, left=488, width=40, height=8)) ### ('37-117', 'TORH', <HEADER>) WWW unhandled (1526, TE_Id(text=u'Gbe1/2: Core', top=573, left=488, width=48, height=8)) ### ('37-117', 'TORH', <HEADER>) WWW unhandled (1527, TE_Id(text=u'GbE0: Aux ', top=338, left=493, width=40, height=8)) ### ('37-118', 'TOTL', <HEADER>) WWW unhandled (1527, TE_Id(text=u'Gbe1/2: Core', top=345, left=493, width=48, height=8)) ### ('37-118', 'TOTL', <HEADER>) WWW unhandled (1528, TE_Id(text=u'GbE0: Aux ', top=228, left=488, width=40, height=8)) ### ('37-119', 'TOTH', <HEADER>) WWW unhandled (1528, TE_Id(text=u'Gbe1/2: Core', top=235, left=488, width=48, height=8)) ### ('37-119', 'TOTH', <HEADER>) WWW unhandled (1528, TE_Id(text=u'GbE0: Aux ', top=506, left=488, width=40, height=8)) ### ('37-120', 'TPR', <HEADER>) WWW unhandled (1528, TE_Id(text=u'Gbe1/2: Core', top=513, left=488, width=48, height=8)) ### ('37-120', 'TPR', <HEADER>) WWW unhandled (1529, TE_Id(text=u'GbE0: Aux ', top=288, left=496, width=40, height=8)) ### ('37-121', 'TPT', <HEADER>) WWW unhandled (1529, TE_Id(text=u'Gbe1/2: Core', top=295, left=496, width=48, height=8)) ### ('37-121', 'TPT', <HEADER>) WWW unhandled (1529, TE_Id(text=u'GbE0: Aux ', top=576, left=496, width=40, height=8)) ### ('37-122', 'PTC64', <HEADER>) WWW unhandled (1529, TE_Id(text=u'Gbe1/2: Core', top=583, left=496, width=48, height=8)) ### ('37-122', 'PTC64', <HEADER>) WWW unhandled (1530, TE_Id(text=u'GbE0: Aux ', top=350, left=488, width=40, height=8)) ### ('37-123', 'PTC255', <HEADER>) WWW unhandled (1530, TE_Id(text=u'Gbe1/2: Core', top=357, left=488, width=48, height=8)) ### ('37-123', 'PTC255', <HEADER>) WWW unhandled (1530, TE_Id(text=u'GbE0: Aux ', top=625, left=488, width=40, height=8)) ### ('37-124', 'PTC511', <HEADER>) WWW unhandled (1530, TE_Id(text=u'Gbe1/2: Core', top=632, left=488, width=48, height=8)) ### ('37-124', 'PTC511', <HEADER>) WWW unhandled (1531, TE_Id(text=u'GbE0: Aux ', top=288, left=496, width=40, height=8)) ### ('37-125', 'PTC1023', <HEADER>) WWW unhandled (1531, TE_Id(text=u'Gbe1/2: Core', top=295, left=496, width=48, height=8)) ### ('37-125', 'PTC1023', <HEADER>) WWW unhandled (1531, TE_Id(text=u'GbE0: Aux ', top=563, left=496, width=40, height=8)) ### ('37-126', 'PTC1522', <HEADER>) WWW unhandled (1531, TE_Id(text=u'Gbe1/2: Core', top=570, left=496, width=48, height=8)) ### ('37-126', 'PTC1522', <HEADER>) WWW unhandled (1532, TE_Id(text=u'GbE0: Aux ', top=268, left=488, width=40, height=8)) ### ('37-127', 'MPTC', <HEADER>) WWW unhandled (1532, TE_Id(text=u'Gbe1/2: Core', top=275, left=488, width=48, height=8)) ### ('37-127', 'MPTC', <HEADER>) WWW unhandled (1532, TE_Id(text=u'GbE0: Aux ', top=516, left=488, width=40, height=8)) ### ('37-128', 'BPTC', <HEADER>) WWW unhandled (1532, TE_Id(text=u'Gbe1/2: Core', top=523, left=488, width=48, height=8)) ### ('37-128', 'BPTC', <HEADER>) WWW unhandled (1533, TE_Id(text=u'GbE0: Aux ', top=308, left=496, width=40, height=8)) ### ('37-129', 'TSCTC', <HEADER>) WWW unhandled (1533, TE_Id(text=u'Gbe1/2: Core', top=315, left=496, width=48, height=8)) ### ('37-129', 'TSCTC', <HEADER>) WWW unhandled (1533, TE_Id(text=u'GbE0: Aux ', top=596, left=496, width=40, height=8)) ### ('37-130', 'TSCTFC', <HEADER>) WWW unhandled (1533, TE_Id(text=u'Gbe1/2: Core', top=603, left=496, width=48, height=8)) ### ('37-130', 'TSCTFC', <HEADER>) WWW unhandled (1534, TE_Id(text=u'GbE0: Aux ', top=271, left=488, width=40, height=8)) ### ('37-131', 'WUC', <HEADER>) WWW unhandled (1534, TE_Id(text=u'Gbe1/2: Core', top=278, left=488, width=48, height=8)) ### ('37-131', 'WUC', <HEADER>) WWW unhandled (1535, TE_Id(text=u'GbE0: Aux ', top=298, left=492, width=40, height=8)) ### ('37-132', 'WUFC', <HEADER>) WWW unhandled (1535, TE_Id(text=u'Gbe1/2: Core', top=305, left=492, width=48, height=8)) ### ('37-132', 'WUFC', <HEADER>) WWW unhandled (1536, TE_Id(text=u'GbE0: Aux ', top=336, left=488, width=40, height=8)) ### ('37-133', 'WUS', <HEADER>) WWW unhandled (1536, TE_Id(text=u'Gbe1/2: Core', top=343, left=488, width=48, height=8)) ### ('37-133', 'WUS', <HEADER>) WWW unhandled (1537, TE_Id(text=u'GbE0: Aux ', top=268, left=496, width=40, height=8)) ### ('37-134', 'IPAV', <HEADER>) WWW unhandled (1537, TE_Id(text=u'Gbe1/2: Core', top=275, left=496, width=48, height=8)) ### ('37-134', 'IPAV', <HEADER>) WWW unhandled (1539, TE_Id(text=u'GbE0: Aux ', top=238, left=496, width=40, height=8)) ### ('37-136', 'IPV6_ADDR0BYTES_1_4', <HEADER>) WWW unhandled (1539, TE_Id(text=u'Gbe1/2: Core', top=245, left=496, width=48, height=8)) ### ('37-136', 'IPV6_ADDR0BYTES_1_4', <HEADER>) WWW unhandled (1539, TE_Id(text=u'GbE0: Aux ', top=552, left=496, width=40, height=8)) ### ('37-137', 'IPV6_ADDR0BYTES_5_8', <HEADER>) WWW unhandled (1539, TE_Id(text=u'Gbe1/2: Core', top=559, left=496, width=48, height=8)) ### ('37-137', 'IPV6_ADDR0BYTES_5_8', <HEADER>) WWW unhandled (1540, TE_Id(text=u'GbE0: Aux ', top=334, left=483, width=40, height=8)) ### ('37-138', 'IPV6_ADDR0BYTES_9_12', <HEADER>) WWW unhandled (1540, TE_Id(text=u'Gbe1/2: Core', top=341, left=483, width=48, height=8)) ### ('37-138', 'IPV6_ADDR0BYTES_9_12', <HEADER>) WWW unhandled (1541, TE_Id(text=u'GbE0: Aux ', top=223, left=496, width=40, height=8)) ### ('37-139', 'IPV6_ADDR0BYTES_13_16', <HEADER>) WWW unhandled (1541, TE_Id(text=u'Gbe1/2: Core', top=230, left=496, width=48, height=8)) ### ('37-139', 'IPV6_ADDR0BYTES_13_16', <HEADER>) WWW unhandled (1542, TE_Id(text=u'GbE0: Aux ', top=228, left=488, width=40, height=8)) ### ('37-140', 'FFLT[0-3]', <HEADER>) WWW unhandled (1542, TE_Id(text=u'Gbe1/2: Core', top=235, left=488, width=48, height=8)) ### ('37-140', 'FFLT[0-3]', <HEADER>) WWW unhandled (1543, TE_Id(text=u'GbE0: Aux ', top=228, left=496, width=40, height=8)) ### ('37-142', 'FFMT[0-127]', <HEADER>) WWW unhandled (1543, TE_Id(text=u'Gbe1/2: Core', top=235, left=496, width=48, height=8)) ### ('37-142', 'FFMT[0-127]', <HEADER>) WWW unhandled (1544, TE_Id(text=u'GbE0: Aux ', top=228, left=488, width=40, height=8)) ### ('37-144', 'FFVT[0-127]', <HEADER>) WWW unhandled (1544, TE_Id(text=u'Gbe1/2: Core', top=235, left=488, width=48, height=8)) ### ('37-144', 'FFVT[0-127]', <HEADER>) WWW unhandled (1544, TE_Id(text=u'GbE0: Aux ', top=606, left=488, width=40, height=8)) ### ('37-145', 'INTBUS_ERR_STAT', <HEADER>) WWW unhandled (1544, TE_Id(text=u'Gbe1/2: Core', top=613, left=488, width=48, height=8)) ### ('37-145', 'INTBUS_ERR_STAT', <HEADER>) WWW unhandled (1545, TE_Id(text=u'GbE0: Aux ', top=211, left=496, width=40, height=8)) ### ('37-145', 'INTBUS_ERR_STAT', <HEADER>) WWW unhandled (1545, TE_Id(text=u'Gbe1/2: Core', top=218, left=496, width=48, height=8)) ### ('37-145', 'INTBUS_ERR_STAT', <HEADER>) WWW unhandled (1546, TE_Id(text=u'GbE0: Aux ', top=308, left=480, width=40, height=8)) ### ('37-146', 'MEM_TST', <HEADER>) WWW unhandled (1546, TE_Id(text=u'Gbe1/2: Core', top=315, left=480, width=48, height=8)) ### ('37-146', 'MEM_TST', <HEADER>) WWW unhandled (1547, TE_Id(text=u'GbE0: Aux ', top=243, left=489, width=40, height=8)) ### ('37-147', 'MEM_STS', <HEADER>) WWW unhandled (1547, TE_Id(text=u'Gbe1/2: Core', top=250, left=489, width=48, height=8)) ### ('37-147', 'MEM_STS', <HEADER>) WWW unhandled (1548, TE_Id(text=u'GbE0: Aux ', top=211, left=481, width=40, height=8)) ### ('37-147', 'MEM_STS', <HEADER>) WWW unhandled (1548, TE_Id(text=u'Gbe1/2: Core', top=218, left=481, width=48, height=8)) ### ('37-147', 'MEM_STS', <HEADER>) ============================================================ 0h CTRL table_ref 37-25 offset 0h reg_name CTRL recurring None reg_base_name CTRL title_desc Device Control Register description None view PCI 3 bar CSRBAR offset_start 0h offset_end 3h power_well Gbe1/2: size 32 default 00000a09h bus_device_function M:2:0 ---------------- range 31 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 30 acronym VME description VLAN Mode Enable. 0 = VLAN Mode Disabled.1 = VLAN Mode Enabled. All packets transmitted have an 802.1q header added to the packet. The contents of the header come from the transmit descriptor and from the VLAN type register. On receive, VLAN information is stripped from 802.1q packets. See "802.1q VLAN Support" on page 1400 for more details. sticky reset 0b [ 0h ] access RW ---------------- range 29 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 28 acronym TFCE description Transmit Flow Control Enable. 0 = Transmit Flow Control Disabled.1 = Transmit Flow Control Enabled. Flow control packets (XON & XOFF frames) will be transmitted based on receiver fullness. If Auto-Negotiation is enabled, this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more information about Auto-Negotiation. sticky reset 0b [ 0h ] access RW ---------------- range 27 acronym RFCE description Receive Flow Control Enable. 0 = Receive Flow Control Disabled.1 = Receive Flow Control Enabled. Indicates the device will respond to the reception of flow control packets. Reception of flow control packets requires the correct loading of the FCAH/FCAL & FCT registers. If Auto-Negotiation is enabled, this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more information about Auto-Negotiation. sticky reset 0b [ 0h ] access RW ---------------- range 26 acronym RST description Device Reset, also referred to as a "Soft Reset". Normally 0, writing 1 initiates the reset. This bit is self clearing. CTRL.RST may be used to globally reset the entire GbE hardware. This register is provided primarily as a last-ditch software mechanism to recover from an indeterminate or suspected hung hardware state. Most registers (receive, transmit, interrupt, statistics, etc.), and state machines will be set to their power-on reset values, approximating the state following a power-on or Unit Reset. However, the Packet Buffer Allocation Register (PBA) retains its value through a global reset.Note:Software must first disable both transmit & receive operation using the TCTL.EN and RCTL.EN register bits before asserting CTRL.RST. To ensure that the global device reset has fully completed and that the controller will respond to subsequent accesses, software must wait a minimum of 5 milliseconds after setting CTRL.RST before attempting to check if the bit has cleared or to access any other GbE device register. sticky reset 0b [ 0h ] access RW ---------------- range 25-21 acronym Rsvd description Reserved sticky reset 00000b [ 00h ] access RV ---------------- range 20 acronym ADVD3WUC description D3Cold WakeUp Capability Advertisement Enable. When set, D3Cold wakeup capability may be advertised based on whether the AUX_PWR pin advertises presence of auxiliary power (see section 2.13.3 for details). When 0, D3Cold wakeup capability will not be advertised even if AUX_PWR presence is indicated. Formerly used as SDP2 pin data value, initial value is EEPROM-configurable *Note that this bit is loaded from the EEPROM, if present sticky reset 0b [ 0h ] access RW ---------------- range 19-13 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 12 acronym FRCDPLX description Force Duplex. 0 = Mode is Full-Duplex, regardless of the FD setting.1 =CTRL.FD bit sets duplex mode. sticky reset 0b [ 0h ] access RW ---------------- range 11 acronym FRCSPD description Force Speed. 0 = Default of 1Gbps is used to set the MAC speed. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more details.1 =CTRL.SPEED bits set the MAC speed.Note:This bit is superseded by the CTRL_EXT.SPD_BYPS bit which has a similar function.Note:*Note that this bit is loaded from the EEPROM, if present sticky reset [ 1b ] 1h access RW ---------------- range 10 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 9-8 acronym SPEED description Speed selection. These bits are written by software (assuming, after reading the PHY registers through the MDIO interface) to set the MAC speed configuration. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for details. ? 00 => 10 Mbps ? 01 => 100 Mbps ? 10 => 1000 Mbps ? 11 => reservedNote:These bits affect the MAC speed setting only if CTRL_EXT.SPD_BYPS or CTRL.FRCSPD are used. sticky reset [ 10b ] 2h access RW ---------------- range 7 acronym Reserved description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 6 acronym SLU description Set Link Up. SLU must be set to '1' to enable the MAC. This bit may also be initialized by the APME bit in the EEPROM Initialization Control Word3, if an EEPROM is used. sticky reset 0b [ 0h ] access RW ---------------- range 5 acronym Rsvd description Reserved. Must be set to 0. sticky reset 0b [ 0h ] access RW ---------------- range 4 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 3 acronym Rsvd description Reserved sticky reset [ 1b ] 1h access RW ---------------- range 2 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym Rsvd description Reserved. Must write '0' to this bit.1 = sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym FD description Full Duplex. Controls the MAC duplex setting. 0 = Half Duplex1 = Full Duplex In half-duplex mode, EP80579's GbE transmits carrier extended packets and can receive both carrier extended packets, and packets transmitted with bursting. *Note that this bit is loaded from the EEPROM, if present sticky reset [ 1b ] 1h access RW ============================================================ 8h STATUS table_ref 37-26 offset 8h reg_name STATUS recurring None reg_base_name STATUS title_desc Device Status Register description None view PCI 3 bar CSRBAR offset_start 8h offset_end bh power_well Gbe1/2: size 32 default 0000XXXXh bus_device_function M:2:0 ---------------- range 31-10 acronym Rsvd description Reserved sticky reset 0000000000000000000000b [ 000000h ] access RV ---------------- range 9-8 acronym Reserved description Reserved sticky reset None <warning> access RO ---------------- range 7-6 acronym SPEED description Link Speed Setting: Reflects speed setting of the MAC. In GMII/MII mode, these bits reflect the software CTRL.SPEED setting ? 00 => 10 Mbps ? 01 => 100 Mbps ? 10 => 1000 Mbps ? 11 => 1000 Mbps sticky reset None <warning> access RO ---------------- range 5 acronym LINKMODE description Mode. Based on CTRL_EXT. LINK_MODE. 0 = MAC is operating in GMII/MII mode1 = Reserved sticky reset None <warning> access RO ---------------- range 4 acronym TXOFF description Transmission Off. This bit indicates the state of the transmit function when symmetrical flow control has been enabled and negotiated with the link partner. 0 = Symmetrical flow control is disabled, or transmission is not paused.1 = Symmetrical flow control is enabled, and the transmit function is paused due to the reception of an XOFF frame. It is cleared upon expiration of the pause timer or the receipt of an XON frame. sticky reset None <warning> access RO ---------------- range 3-2 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 1 acronym RSVD description Reserved sticky reset None <warning> access RO ---------------- range 0 acronym FD description Full Duplex. This bit reflects the MAC duplex configuration. Normally, the duplex setting for the link, as it should reflect the duplex configuration negotiated between the PHY and link partner (copper link) or MAC and link partner (fiber link). 0 = Half Duplex mode1 = Full Duplex mode sticky reset None <warning> access RO ============================================================ 18h CTRL_EXT table_ref 37-27 offset 18h reg_name CTRL_EXT recurring None reg_base_name CTRL_EXT title_desc Extended Device Control Register description None view PCI 3 bar CSRBAR offset_start 18h offset_end 1bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-25 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 24 acronym RMII_RX_MODE description RMII gasket receive mode select: 0 = For proper 100mbps receive operation, after assertion of the RMII CRS_DV signal on GBEn_RXCTL, the RMII gasket requires that a minimum of two di-bits of '00' appear on GBEn_RXDATA[1:0] before the preamble appears.1 = For proper 100mbps receive operation, the RMII gasket requires that CRS_DV be asserted on GBEn_RXCTL synchronously with GBE_REFCLK_RMII and on the same cycle in which the first di-bit of the preamble appears on GBEn_RXDATA[1:0]. 0 is the default value of this bit and makes the RMII gasket compatible with RMII PHYs that assert CRS_DV as soon as the receive medium is non-idle, and subsequently drive '00' on RXD[1:0] until proper receive signal decoding has been achieved (per the RMII Specification, Revision 1.2). Setting this bit to a 1 makes the gasket compatible with RMII PHYs that assert CRS_DV simultaneously with the start of the preamble driven on RXD[1:0]. While this CRS_DV signalling mode does not scrictly conform to the RMII specification, it is provided to allow compatibility with PHY devices that use this alternate method of asserting CRS_DV at the start of the packet. This bit must be set to the proper state that corresponds to the CRS_DV behavior of the attached RMII PHY, otherwise 100mbps packets cannot be properly received by the GbE. This bit does not affect transmit operations. sticky reset 0b [ 0h ] access RW ---------------- range 23-22 acronym LINK_MODE description Link Mode. This controls which interface is used to talk to the link. ? 00 => GMII/MII mode ? 01 => reserved ? 10 => reserved ? 11 => reserved ? *Note that this bit is loaded from the EEPROM, if present sticky reset 00b [ 0h ] access RW ---------------- range 21-16 acronym Rsvd description Reserved sticky reset 000000b [ 00h ] access RV ---------------- range 15 acronym SPD_BYPS description Speed Select Bypass. 0 = Normal speed detection mechanisms are used to determine the speed of the MAC.1 = All speed detection mechanisms are bypassed and the MAC is immediately set to the setting of CTRL.SPEED.Note:CTRL_EXT.SPD_BYPS performs a function similar to CTRL.FRCSPD in that the device's speed settings are determined by the value software writes to the CTRL.SPEED bits. However, when using CTRL_EXT.SPD_BYPS the CTRL.SPEED setting takes effect immediately, when using CTRL.FRCSPD the CTRL.SPEED setting waits until after the device's clock switching circuitry performs the change. sticky reset 0b [ 0h ] access RW ---------------- range 14 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 13 acronym EE_RST description EEPROM Reset Initiates a "reset-like" event to the EEPROM function. This causes the EEPROM to be read as if a UNIT_RESET had occurred. All device functions should be disabled prior to setting this bit. This bit is self-clearing. NOTE: this will not cause the controller to detect the EEPROM sticky reset 0b [ 0h ] access RW ---------------- range 12 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 11-0 acronym Rsvd description Reserved sticky reset 000000000000b [ 000h ] access RV ============================================================ e0h CTRL_AUX table_ref 37-28 offset e0h reg_name CTRL_AUX recurring None reg_base_name CTRL_AUX title_desc Auxiliary Device Control Register description None view PCI 3 bar CSRBAR offset_start e0h offset_end e3h power_well Gbe1/2: size 32 default 00000100h bus_device_function M:2:0 ---------------- range 31-18 acronym RSVD description Reserved sticky reset 00000000000000b [ 0000h ] access RO ---------------- range 17 acronym RMII_LOG_FIX description Enable logic change to fix RMII 100mbps TX dropped packet data. To enable this mode of operation, set this bit to a '1'. When enabled, the fix modifies the legacy new-packet signalling logic in the transmit path to prevent the first 8 bytes of packet data from being dropped when operating in RMII mode and a line speed of 100mbps. sticky reset 0b [ 0h ] access RW ---------------- range 16 acronym RMII_FREQ_FIX description Disable DMA frequency change to fix RMII 100mbps TX dropped packet data. This is the default mode of operation. To disable this mode of operation, set this bit to a '1'. This must be disabled if FIX2 is enabled. When enabled, sets the DMA clock frequency to 50MHz when operating in RMII mode. This produces a favorable frequency ratio between DMA and MAC clocks that prevents the first 8 bytes of transmit packet data from being dropped when operating in RMII mode and a line speed of 100mbps. sticky reset 0b [ 0h ] access RW ---------------- range 15-12 acronym RSVD description Reserved sticky reset 0000b [ 0h ] access RO ---------------- range 11-10 acronym END_SEL description Selects whether the descriptor or packet data is controlled by endianness configuration. 00 - descriptor and packet transfers use CTRL_AUX.ENDIANESS 01 - descriptor uses CTL_AUX.ENDIANESS, packet uses default 10 - descriptor uses default, packet uses CTRL_AUX.ENDIANESS 11 - all transfers use CTRL_AUX.ENDIANESS sticky reset 00b [ 0h ] access RW ---------------- range 9-8 acronym ENDIANESS description Endianness: These bits control the endianness of the data in memory. These settings apply to all internal bus transactions, including packet data and descriptors '00' - LW Little--Endian, Byte Big-Endian '01' - LW Little-Endian, Byte Little-Endian (default) '10' - LW Big-Endian, Byte Big-Endian '11' - LW Big-Endian, Byte Little-Endian Refer to Section 37.5.14, "Endianness" for further details. sticky reset 01b [ 1h ] access RW ---------------- range 7-1 acronym RSVD description Reserved sticky reset 0000000b [ 00h ] access RO ---------------- range 0 acronym RGMII_RMII description RGMII/RMII Translation Gasket Select ? '0' - RGMII ? '1' - RMII sticky reset 0b [ 0h ] access RW ============================================================ 10h EEPROM_CTRL table_ref 37-29 offset 10h reg_name EEPROM_CTRL recurring None reg_base_name EEPROM_CTRL title_desc EEPROM Control Register description None view PCI 3 bar CSRBAR offset_start 10h offset_end 13h power_well Gbe1/2: size 32 default 00000X1Xh bus_device_function M:2:0 ---------------- range 31-10 acronym RSVD description Reserved sticky reset 0000000000000000000000b [ 000000h ] access RO ---------------- range 9 acronym EE_SIZE description EEPROM Size. 0 Reserved 1 4096-bit (256 word) NM93C66 compatible EEPROM If an EEPROM is present, this bit indicates its size, based on acknowledges seen during EEPROM scans of different addresses. This bit is read-only. NOTE: this bit will not be updated as a result of anything but a power up reset. sticky reset None <warning> access RO ---------------- range 8 acronym EE_PRES description EEPROM Present This bit attempts to indicate if an EEPROM is present by monitoring the EE_DO input for a active-low "acknowledge" by the serial EEPROM during initial EEPROM scan. If no EEPROM is present, the EE_DO line will remain pulled-high and thus no acknowledge will be seen. 1=EEPROM present; 0=no EEPROM. NOTE: this bit will not be set except as a result of EEPROM detection during power up reset. sticky reset None <warning> access RO ---------------- range 7 acronym EE_GNT description Grant EEPROM Access When this bit is 1 the software can access the EEPROM using the SK, CS, DI, and DO bits. sticky reset 0b [ 0h ] access RO ---------------- range 6 acronym EE_REQ description Request EEPROM Access The software must write a 1 to this bit to get direct EEPROM access. It has access when EE_GNT is 1. When the software completes the access it must write a 0. sticky reset 0b [ 0h ] access RW ---------------- range 5-4 acronym RSVD description Reserved sticky reset 01b [ 1h ] access RO ---------------- range 3 acronym EE_DO description Data Output Bit from the EEPROM. The EE_DO input signal is mapped directly to this bit in the register and contains the EEPROM data output. This bit is read-only from the software perspective - writes to this bit have no effect. sticky reset None <warning> access RO ---------------- range 2 acronym EE_DI description Data Input to the EEPROM. When EE_GNT is 1, the EE_DI output signal is mapped directly to this bit. Software provides data input to the EEPROM via writes to this bit. sticky reset 0b [ 0h ] access RW ---------------- range 1 acronym EE_CS description Chip Select Input to the EEPROM. When EE_GNT is 1, the EE_CS output signal is mapped to the chip select of the EEPROM device. Software enables the EEPROM by writing a 1 to this bit. sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym EE_SK description Clock Input to the EEPROM. When EE_GNT is 1, the EE_SK output signal is mapped to this bit and provides the serial clock input to the EEPROM. Software clocks the EEPROM via toggling this bit with successive writes. sticky reset 0b [ 0h ] access RW ============================================================ 14h EEPROM_RR table_ref 37-30 offset 14h reg_name EEPROM_RR recurring None reg_base_name EEPROM_RR title_desc EEPROM Read Register description None view PCI 3 bar CSRBAR offset_start 14h offset_end 17h power_well Gbe1/2: size 32 default XXXXXX00h bus_device_function M:2:0 ---------------- range 31-16 acronym DATA description Read Data Data returned from the EEPROM read. sticky reset None <warning> access RO ---------------- range 15-8 acronym ADDR description Read Address This field is written by software along with Start Read to indicate the word to read. sticky reset None <warning> access RW ---------------- range 7-5 acronym RSVD description Reserved Reads as 0 sticky reset 000b [ 0h ] access RV ---------------- range 4 acronym DONE description Read Done Set to 1 when the EEPROM read completes. Set to 0 when the EEPROM read is in progress. Writes by software are ignored. sticky reset 0b [ 0h ] access RO ---------------- range 3-1 acronym RSVD description Reserved Reads as 0 sticky reset 000b [ 0h ] access RV ---------------- range 0 acronym START description Start Read Writing a 1 to this bit causes the EEPROM to read a (16-bit) word at the address stored in the EE_ADDR field, storing the result in the EE_DATA field. This bit is self-clearing sticky reset 0b [ 0h ] access RW ============================================================ 28h FCAL table_ref 37-31 offset 28h reg_name FCAL recurring None reg_base_name FCAL title_desc Flow Control Address Low Register description None view PCI 3 bar CSRBAR offset_start 28h offset_end 2bh power_well Gbe1/2: size 32 default 00c28001h bus_device_function M:2:0 ---------------- range 31-0 acronym FCAL description This register must be programmed with 0x00C2_8001. sticky reset 00000000110000101000000000000001b [ 00c28001h ] access RW ============================================================ 2ch FCAH table_ref 37-32 offset 2ch reg_name FCAH recurring None reg_base_name FCAH title_desc Flow Control Address High Register description None view PCI 3 bar CSRBAR offset_start 2ch offset_end 2fh power_well Gbe1/2: size 32 default 00000100h bus_device_function M:2:0 ---------------- range 31-16 acronym RSVD description Reserved sticky reset [ 0000000000000000b ] 0000h access RV ---------------- range 15-0 acronym FCAH description This register must be programmed with 0x00_00_01_00. sticky reset 0000000100000000b [ 0100h ] access RW ============================================================ 30h FCT table_ref 37-33 offset 30h reg_name FCT recurring None reg_base_name FCT title_desc Flow Control Type Register description This register must be programmed with 0x00_00_88_0 view PCI 3 bar CSRBAR offset_start 30h offset_end 33h power_well Gbe1/2: size 32 default 00008808h bus_device_function M:2:0 ---------------- range 31-16 acronym RSVD description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym FCT description This register must be programmed with 0x00_00_88_08. sticky reset 1000100000001000b [ 8808h ] access RW ============================================================ 38h VET table_ref 37-34 offset 38h reg_name VET recurring None reg_base_name VET title_desc VLAN EtherType Register description To be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00 view PCI 3 bar CSRBAR offset_start 38h offset_end 3bh power_well Gbe1/2: size 32 default 00008100h bus_device_function M:2:0 ---------------- range 31-16 acronym RSVD description Reserved sticky reset [ 0000000000000000b ] 0000h access RV ---------------- range 15-0 acronym VET description To be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00. sticky reset 1000000100000000b [ 8100h ] access RW ============================================================ 170h FCTTV table_ref 37-35 offset 170h reg_name FCTTV recurring None reg_base_name FCTTV title_desc Flow Control Transmit Timer Value Register description None view PCI 3 bar CSRBAR offset_start 170h offset_end 173h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym TTV description Transmit Timer Value to be included in XOFF frame. sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 1000h PBA table_ref 37-36 offset 1000h reg_name PBA recurring None reg_base_name PBA title_desc Packet Buffer Allocation Register description None view PCI 3 bar CSRBAR offset_start 1000h offset_end 1003h power_well Gbe1/2: size 32 default 00100030h bus_device_function M:2:0 ---------------- range 31-22 acronym RSVD description Reserved sticky reset 0000000000b [ 000h ] access RO ---------------- range 21-16 acronym TXA description Transmit Packet Buffer Allocation in K bytes. PBA.TXA is read only and calculated based on PBA.RXA. 0010h =>16KB sticky reset 010000b [ 10h ] access RO ---------------- range 15-6 acronym RSVD description Reserved sticky reset 0000000000b [ 000h ] access RO ---------------- range 5-0 acronym RXA description Receive Packet Buffer Allocation in K bytes. PBA.RXA legal values must be 8K aligned. Valid values are (decimal) 8, 16, 24, 32, 40, 48, 56. 0030h => 48KBh sticky reset 110000b [ 30h ] access RW ============================================================ c0h ICR0 table_ref 37-37 offset c0h reg_name ICR0 recurring None reg_base_name ICR0 title_desc Interrupt 0 Cause Read Register description None view PCI 3 bar CSRBAR offset_start c0h offset_end c3h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym RSVD description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Internal Bus Error. This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details. The details of this error are reported in the INTBUS_ERR_STAT register. sticky reset 0b [ 0h ] access RCWC ---------------- range 27 acronym ERR_STAT description Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST) sticky reset 0b [ 0h ] access RCWC ---------------- range 26 acronym ERR_MCFSPF description This bit indicates that either a Multicast Filter Parity Error, Special Packet Filter Parity Error or a Flex Filter Parity Error occurred. These filters use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT register. sticky reset 0b [ 0h ] access RCWC ---------------- range 25-24 acronym RSVD description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PB description DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST) sticky reset 0b [ 0h ] access RCWC ---------------- range 22 acronym RSVD description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST) sticky reset 0b [ 0h ] access RCWC ---------------- range 20 acronym ERR_RXDS description DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST) sticky reset 0b [ 0h ] access RCWC ---------------- range 19-17 acronym RSVD description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Small Receive Packet Detected. Indicates that a packet of size RSRPD.SIZE register has been detected and transferred to host memory. The interrupt is only asserted if RSRPD.SIZE register has a non-zero value sticky reset 0b [ 0h ] access RCWC ---------------- range 15 acronym TXD_LOW description Transmit Descriptor Low Threshold hit. Indicates that the descriptor ring has reached the threshold specified in "TXDCTL - Transmit Descriptor Control Register" on page 1500. sticky reset 0b [ 0h ] access RCWC ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Receiver Timer Interrupt. Set when the timers expire, see "Receive Interrupts" on page 1360 for details. sticky reset 0b [ 0h ] access RCWC ---------------- range 6 acronym RXO description Receiver Overrun. Set on receive data FIFO overrun. Could be caused either because there are no available buffers or because Internal Bus receive bandwidth is inadequate. sticky reset 0b [ 0h ] access RCWC ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Receive Descriptor Minimum Threshold Hit. Indicates that the minimum number of receive descriptors are available and software should load more receive descriptors. sticky reset 0b [ 0h ] access RCWC ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RCWC ---------------- range 2 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Transmit Queue Empty. Set when the last descriptor block for a transmit queue has been used. sticky reset 0b [ 0h ] access RCWC ---------------- range 0 acronym TXDW description Transmit Descriptor Written Back. Set when hardware processes a descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is set in the Transmit Descriptor CMD), the interrupt is delayed until after one of the delayed-timers (TIDV or TADV) expires. sticky reset 0b [ 0h ] access RCWC ============================================================ c4h ITR0 table_ref 37-38 offset c4h reg_name ITR0 recurring None reg_base_name ITR0 title_desc Interrupt 0 Throttling Register description None view PCI 3 bar CSRBAR offset_start c4h offset_end c7h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym MIII description Minimum Inter-interrupt Interval. ? In RGMII mode, the interval is specified in 256ns increments. ? In RMII mode, the interval is specified in 320ns increments ? Zero disables interrupt throttling logic (The following example applies to RGMII mode) To independently validate configuration settings, software can use the following formula to convert the inter-interrupt interval value to the common 'interrupts/sec' performance metric:-9-interrupts/sec = (256 x 10 sec x inter-interrupt interval)1 Inversely, inter-interrupt interval value can be calculated as:-9-inter-interrupt interval = (256 x 10 sec x interrupts/sec)1 For example, if the interval is programmed to 500d, the network controller guarantees the CPU will not be interrupted by the network controller for 128 usec from the last interrupt. The maximum observable interrupt rate from the adapter should never exceed 7813 interrupts/sec. The optimal performance setting for this register is system/configuration specific. A initial suggested range is 651-5580 (28Bh - 15CCh), or, more generally, between 700 and 6000 interrupts per second. sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ c8h ICS0 table_ref 37-39 offset c8h reg_name ICS0 recurring None reg_base_name ICS0 title_desc Interrupt 0 Cause Set Register description None view PCI 3 bar CSRBAR offset_start c8h offset_end cbh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Triggers Internal Bus Error sticky reset 0b [ 0h ] access RW ---------------- range 27 acronym ERR_STAT description Triggers Statistic Register ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 26 acronym ERR_MCFSPF description Triggers Special Packet Filter Parity Error sticky reset 0b [ 0h ] access RW ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Triggers DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Triggers DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 20 acronym ERR_RXDS description Triggers DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 19-17 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Triggers Small Receive Packet Detected and Transferred sticky reset 0b [ 0h ] access RW ---------------- range 15 acronym TXD_LOW description Triggers Transmit Descriptor Low Threshold Hit sticky reset 0b [ 0h ] access RW ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Triggers Receiver Timer Interrupt sticky reset 0b [ 0h ] access RW ---------------- range 6 acronym RXO description Triggers Receiver Overrun. Set on receive data FIFO overrun sticky reset 0b [ 0h ] access RW ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Triggers Receive Descriptor Minimum Threshold hit sticky reset 0b [ 0h ] access RW ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym Rsvd description Reserved. Must be written as '0' sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Triggers Transmit Queue Empty sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym TXDW description Triggers Transmit Descriptor Written Back sticky reset 0b [ 0h ] access RW ============================================================ d0h IMS0 table_ref 37-40 offset d0h reg_name IMS0 recurring None reg_base_name IMS0 title_desc Interrupt 0 Mask Set/Read Register description None view PCI 3 bar CSRBAR offset_start d0h offset_end d3h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Enables Internal Bus Error sticky reset 0b [ 0h ] access RW ---------------- range 27 acronym ERR_STAT description Enables Statistic Register ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 26 acronym ERR_MCFSPF description Enables Special Packet Filter Parity Error sticky reset 0b [ 0h ] access RW ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Enables DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Enables DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 20 acronym ERR_RXDS description Enables DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 19-17 acronym Rsvd description Reserved. Must be written as '0' sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Sets the mask for Small Receive Packet Detected and Transferred sticky reset 0b [ 0h ] access RW ---------------- range 15 acronym TXD_LOW description Sets the mask for Transmit Descriptor Low Threshold Hit sticky reset 0b [ 0h ] access RW ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Sets the mask for Receiver Timer Interrupt sticky reset 0b [ 0h ] access RW ---------------- range 6 acronym RXO description Sets the mask for Receiver Overrun. Set on receive data FIFO overrun sticky reset 0b [ 0h ] access RW ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Sets the mask for Receive Descriptor Minimum Threshold hit sticky reset 0b [ 0h ] access RW ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym Rsvd description Reserved. Must be written as '0' sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Sets the mask for Transmit Queue Empty sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym TXDW description Sets the mask for Transmit Descriptor Written Back sticky reset 0b [ 0h ] access RW ============================================================ d8h IMC0 table_ref 37-41 offset d8h reg_name IMC0 recurring None reg_base_name IMC0 title_desc Interrupt 0 Mask Clear Register description None view PCI 3 bar CSRBAR offset_start d8h offset_end dbh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Clears the mask for Internal Bus Error sticky reset 0b [ 0h ] access WO ---------------- range 27 acronym ERR_STAT description Clears the mask for Statistic Register ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 26 acronym ERR_MCFSPF description Clears the mask for the Filter Memory Errors sticky reset 0b [ 0h ] access WO ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Clears the mask for DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Clears the mask for DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 20 acronym ERR_RXDS description Clears the mask for DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 19-17 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Clears the mask for Small Receive Packet Detected and Transferred sticky reset 0b [ 0h ] access WO ---------------- range 15 acronym TXD_LOW description Clears the mask for Transmit Descriptor Low Threshold Hit sticky reset 0b [ 0h ] access WO ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Clears the mask for Receiver Timer Interrupt sticky reset 0b [ 0h ] access WO ---------------- range 6 acronym RXO description Clears the mask for Receiver Overrun. Set on receive data FIFO overrun sticky reset 0b [ 0h ] access WO ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Clears the mask for Receive Descriptor Minimum Threshold hit sticky reset 0b [ 0h ] access WO ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access WO ---------------- range 2 acronym Rsvd description Reserved. Must be written as '0' sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Clears the mask for Transmit Queue Empty sticky reset 0b [ 0h ] access WO ---------------- range 0 acronym TXDW description Clears the mask for Transmit Descriptor Written Back sticky reset 0b [ 0h ] access WO ============================================================ 8c0h ICR1 table_ref 37-42 offset 8c0h reg_name ICR1 recurring None reg_base_name ICR1 title_desc Interrupt 1Cause Read Register description None view PCI 3 bar CSRBAR offset_start 8c0h offset_end 8c3h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym RSVD description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Internal Bus Error. This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details. The details of this error are reported in the INTBUS_ERR_STAT register. sticky reset 0b [ 0h ] access RCWC ---------------- range 27 acronym ERR_STAT description Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST) sticky reset 0b [ 0h ] access RCWC ---------------- range 26 acronym ERR_MCFSPF description Multicast Filter Parity Error/Special Packet Filter Parity Error. The Multicast Filter and Special Packets Filter use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT register. sticky reset 0b [ 0h ] access RCWC ---------------- range 25-24 acronym RSVD description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PB description DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST). sticky reset 0b [ 0h ] access RCWC ---------------- range 22 acronym RSVD description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST). sticky reset 0b [ 0h ] access RCWC ---------------- range 20 acronym ERR_RXDS description DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST). sticky reset 0b [ 0h ] access RCWC ---------------- range 19-17 acronym RSVD description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Small Receive Packet Detected. Indicates that a packet of size RSRPD.SIZE register has been detected and transferred to host memory. The interrupt is only asserted if RSRPD.SIZE register has a non-zero value sticky reset 0b [ 0h ] access RCWC ---------------- range 15 acronym TXD_LOW description Transmit Descriptor Low Threshold hit. Indicates that the descriptor ring has reached the threshold specified in "TXDCTL - Transmit Descriptor Control Register" on page 1500. sticky reset 0b [ 0h ] access RCWC ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Receiver Timer Interrupt. Set when the timers expire, see "Receive Interrupts" on page 1360 for details. sticky reset 0b [ 0h ] access RCWC ---------------- range 6 acronym RXO description Receiver Overrun. Set on receive data FIFO overrun. Could be caused either because there are no available buffers or because Internal Bus receive bandwidth is inadequate. sticky reset 0b [ 0h ] access RCWC ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Receive Descriptor Minimum Threshold Hit. Indicates that the minimum number of receive descriptors are available and software should load more receive descriptors. sticky reset 0b [ 0h ] access RCWC ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RCWC ---------------- range 2 acronym RSVD description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Transmit Queue Empty. Set when the last descriptor block for a transmit queue has been used. sticky reset 0b [ 0h ] access RCWC ---------------- range 0 acronym TXDW description Transmit Descriptor Written Back. Set when hardware processes a descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is set in the Transmit Descriptor CMD), the interrupt is delayed until after one of the delayed-timers (TIDV or TADV) expires. sticky reset 0b [ 0h ] access RCWC ============================================================ 8c8h ICS1 table_ref 37-43 offset 8c8h reg_name ICS1 recurring None reg_base_name ICS1 title_desc Interrupt 0 Cause Set Register description None view PCI 3 bar CSRBAR offset_start 8c8h offset_end 8cbh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Triggers Internal Bus Error sticky reset 0b [ 0h ] access RW ---------------- range 27 acronym ERR_STAT description Triggers Statistic Register ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 26 acronym ERR_MCFSPF description Triggers Special Packet Filter Parity Error sticky reset 0b [ 0h ] access RW ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Triggers DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Triggers DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 20 acronym ERR_RXDS description Triggers DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 19-17 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Triggers Small Receive Packet Detected and Transferred sticky reset 0b [ 0h ] access RW ---------------- range 15 acronym TXD_LOW description Triggers Transmit Descriptor Low Threshold Hit sticky reset 0b [ 0h ] access RW ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Triggers Receiver Timer Interrupt sticky reset 0b [ 0h ] access RW ---------------- range 6 acronym RXO description Triggers Receiver Overrun. Set on receive data FIFO overrun sticky reset 0b [ 0h ] access RW ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Triggers Receive Descriptor Minimum Threshold hit sticky reset 0b [ 0h ] access RW ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 2 acronym Rsvd description Reserved. Must be written as '0' sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Triggers Transmit Queue Empty sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym TXDW description Triggers Transmit Descriptor Written Back sticky reset 0b [ 0h ] access RW ============================================================ 8d0h IMS1 table_ref 37-44 offset 8d0h reg_name IMS1 recurring None reg_base_name IMS1 title_desc Interrupt 1 Mask Set/Read Register description None view PCI 3 bar CSRBAR offset_start 8d0h offset_end 8d3h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Enables Internal Bus Error sticky RW <warning> reset 0b [ 0h ] access WO ---------------- range 27 acronym ERR_STAT description Enables Statistic Register ECC Error sticky RW <warning> reset 0b [ 0h ] access WO ---------------- range 26 acronym ERR_MCFSPF description Enables Special Packet Filter Parity Error sticky RW <warning> reset 0b [ 0h ] access WO ---------------- range 25-24 acronym Rsvd description Reserved sticky RV <warning> reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Enables DMA Packet Buffer ECC Error sticky RW <warning> reset 0b [ 0h ] access WO ---------------- range 22 acronym Rsvd description Reserved sticky RV <warning> reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Enables DMA Transmit Descriptor Buffer ECC Error sticky RW <warning> reset 0b [ 0h ] access WO ---------------- range 20 acronym ERR_RXDS description Enables DMA Receive Descriptor Buffer ECC Error sticky RW <warning> reset 0b [ 0h ] access WO ---------------- range 19-17 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Sets the mask for Small Receive Packet Detected and Transferred sticky reset 0b [ 0h ] access RW ---------------- range 15 acronym TXD_LOW description Sets the mask for Transmit Descriptor Low Threshold Hit sticky reset 0b [ 0h ] access RW ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Sets the mask for Receiver Timer Interrupt sticky reset 0b [ 0h ] access RW ---------------- range 6 acronym RXO description Sets the mask for Receiver Overrun. Set on receive data FIFO overrun sticky reset 0b [ 0h ] access RW ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Sets the mask for Receive Descriptor Minimum Threshold hit sticky reset 0b [ 0h ] access RW ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym Rsvd description Reserved. Must be written as '0' sticky reset 0b [ 0h ] access RW ---------------- range 1 acronym TXQE description Sets the mask for Transmit Queue Empty sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym TXDW description Sets the mask for Transmit Descriptor Written Back sticky reset 0b [ 0h ] access RW ============================================================ 8d8h IMC1 table_ref 37-45 offset 8d8h reg_name IMC1 recurring None reg_base_name IMC1 title_desc Interrupt 1 Mask Clear Register description None view PCI 3 bar CSRBAR offset_start 8d8h offset_end 8dbh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Clears the mask for Internal Bus Error sticky reset 0b [ 0h ] access WO ---------------- range 27 acronym ERR_STAT description Clears the mask for Statistic Register ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 26 acronym ERR_MCFSPF description Clears the mask for the Filter Memory Errors sticky reset 0b [ 0h ] access WO ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Clears the mask for DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Clears the mask for DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 20 acronym ERR_RXDS description Clears the mask for DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 19-17 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 16 acronym SRPD description Clears the mask for Small Receive Packet Detected and Transferred sticky reset 0b [ 0h ] access WO ---------------- range 15 acronym TXD_LOW description Clears the mask for Transmit Descriptor Low Threshold Hit sticky reset 0b [ 0h ] access WO ---------------- range 14-8 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym RXT0 description Clears the mask for Receiver Timer Interrupt sticky reset 0b [ 0h ] access WO ---------------- range 6 acronym RXO description Clears the mask for Receiver Overrun. Set on receive data FIFO overrun sticky reset 0b [ 0h ] access WO ---------------- range 5 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 4 acronym RXDMT0 description Clears the mask for Receive Descriptor Minimum Threshold hit sticky reset 0b [ 0h ] access WO ---------------- range 3 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access WO ---------------- range 2 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym TXQE description Clears the mask for Transmit Queue Empty sticky reset 0b [ 0h ] access WO ---------------- range 0 acronym TXDW description Clears the mask for Transmit Descriptor Written Back sticky reset 0b [ 0h ] access WO ============================================================ 8e0h ICR2 table_ref 37-46 offset 8e0h reg_name ICR2 recurring None reg_base_name ICR2 title_desc Error Interrupt Cause Read Register description None view PCI 3 bar CSRBAR offset_start 8e0h offset_end 8e3h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym RSVD description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Internal Bus Error. This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details. The details of this error are reported in the INTBUS_ERR_STAT register. sticky reset 0b [ 0h ] access RCWC ---------------- range 27 acronym ERR_STAT description Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST) sticky reset 0b [ 0h ] access RCWC ---------------- range 26 acronym ERR_MCFSPF description Multicast Filter Parity Error/Special Packet Filter Parity Error. The Multicast Filter and Special Packets Filter use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. sticky reset 0b [ 0h ] access RCWC ---------------- range 25-24 acronym RSVD description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PB description DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST). sticky reset 0b [ 0h ] access RCWC ---------------- range 22 acronym RSVD description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST). sticky reset 0b [ 0h ] access RCWC ---------------- range 20 acronym ERR_RXDS description DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST). sticky reset 0b [ 0h ] access RCWC ---------------- range 19-0 acronym RSVD description Reserved sticky reset 00000000000000000000b [ 00000h ] access RV ============================================================ 8e8h ICS2 table_ref 37-47 offset 8e8h reg_name ICS2 recurring None reg_base_name ICS2 title_desc Error Interrupt Cause Set Register description None view PCI 3 bar CSRBAR offset_start 8e8h offset_end 8ebh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Triggers Internal Bus Error sticky reset 0b [ 0h ] access RW ---------------- range 27 acronym ERR_STAT description Triggers Statistic Register ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 26 acronym ERR_MCFSPF description Triggers Special Packet Filter Parity Error sticky reset 0b [ 0h ] access RW ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Triggers DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Triggers DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 20 acronym ERR_RXDS description Triggers DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 19-0 acronym Rsvd description Reserved sticky reset 00000000000000000000b [ 00000h ] access RV ============================================================ 8f0h IMS2 table_ref 37-48 offset 8f0h reg_name IMS2 recurring None reg_base_name IMS2 title_desc Error Interrupt Mask Set/Read Register description None view PCI 3 bar CSRBAR offset_start 8f0h offset_end 8f3h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Enables Internal Bus Error sticky reset 0b [ 0h ] access RW ---------------- range 27 acronym ERR_STAT description Enables Statistic Register ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 26 acronym ERR_MCFSPF description Enables Special Packet Filter Parity Error sticky reset 0b [ 0h ] access RW ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Enables DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Enables DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 20 acronym ERR_RXDS description Enables DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access RW ---------------- range 19-0 acronym Rsvd description Reserved sticky reset 00000000000000000000b [ 00000h ] access RV ============================================================ 8f8h IMC2 table_ref 37-49 offset 8f8h reg_name IMC2 recurring None reg_base_name IMC2 title_desc Error Interrupt Mask Clear Register description None view PCI 3 bar CSRBAR offset_start 8f8h offset_end 8fbh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-29 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 28 acronym ERR_INTBUS description Clears the mask for Internal Bus Error sticky reset 0b [ 0h ] access WO ---------------- range 27 acronym ERR_STAT description Clears the mask for Statistic Register ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 26 acronym ERR_INT description Clears the mask for Internal Memory Error sticky reset 0b [ 0h ] access WO ---------------- range 25-24 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 23 acronym ERR_PKBUF description Clears the mask for DMA Packet Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 22 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 21 acronym ERR_TXDS description Clears the mask for DMA Transmit Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 20 acronym ERR_RXDS description Clears the mask for DMA Receive Descriptor Buffer ECC Error sticky reset 0b [ 0h ] access WO ---------------- range 19-0 acronym Rsvd description Reserved sticky reset 00000000000000000000b [ 00000h ] access RV ============================================================ 100h RCTL table_ref 37-50 offset 100h reg_name RCTL recurring None reg_base_name RCTL title_desc Receive Control Register description None view PCI 3 bar CSRBAR offset_start 100h offset_end 103h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-27 acronym Rsvd description Reserved sticky reset 00000b [ 00h ] access RV ---------------- range 26 acronym SECRC description Strip Ethernet CRC. This bit controls whether the hardware strips the Ethernet CRC from the received packet. This stripping occurs prior to any checksum calculations. The stripped CRC is not DMA'd to host memory and is not included in the length reported in the descriptor. sticky reset 0b [ 0h ] access RW ---------------- range 25 acronym BSEX description Buffer Size Extension. Combined with RCTL.BSIZE to program the receive buffer size. Control of receive buffer size permits software to trade-off descriptor performance versus required storage space. Buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes. RCTL.BSEX = 0 / RCTL.BSIZE = 00 -> Receive Buffer Size = 2048B RCTL.BSEX = 0 / RCTL.BSIZE = 01 -> Receive Buffer Size = 1024B RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive Buffer Size = 512B RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size = 256B RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved RCTL.BSEX = 1 / RCTL.BSIZE = 01 -> Receive Buffer Size = 16384B RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive Buffer Size = 8192B RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size = 4096B sticky reset 0b [ 0h ] access RW ---------------- range 24 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 23 acronym PMCF description Pass MAC Control Frames. This bit controls the DMA function of MAC control frames (other than flow control). A MAC control frame in this context must be addressed to either the MAC control frame multicast address or the station address, it must match the type field and must NOT match the PAUSE opcode of 0x0001. 0 = Do not pass MAC control frames1 = Pass any MAC control frame (type field value of 0x8808) that does not contain the pause opcode of 0x0001. sticky reset 0b [ 0h ] access RW ---------------- range 22 acronym DPF description Discard Pause Frames. This bit controls the DMA function of flow control packets addressed to the station address (RAH/RAL[0]). If a packet is a valid flow control packet and is addressed to the station address it will not be DMA'd to host memory if RCTL.DPF=1. 0 = Incoming frames are subject to filter comparison1 = Incoming valid PAUSE frames discarded even if they match any of the filter registers sticky reset 0b [ 0h ] access RW ---------------- range 21 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 20 acronym CFI description Canonical Form Indicator. One of the three bits that control the VLAN filter table. This bit may be compared to the CFI bit found in the 802.1q packet as part of the acceptance criteria. RCTL.CFIEN and RCTL.VFE determine whether or not this comparison takes place. sticky reset 0b [ 0h ] access RW ---------------- range 19 acronym CFIEN description Canonical Form Indicator Enable. One of the three bits that control the VLAN filter table. This bit enables using the CFI bit found in the 802.1q packet as part of the acceptance criteria. The next two are used to decide whether the CFI bit found in the.1Q packet should be used as part of the acceptance criteria. 0 = CFI Disabled: bit not compared to determine packet acceptance1 = CFI from packet must match CFI field for acceptance of 802.1q packet sticky reset 0b [ 0h ] access RW ---------------- range 18 acronym VFE description VLAN Filter Enable. One of the three bits that control the VLAN filter table. This bit determines whether the table participates in the packet acceptance criteria. 0 = Disabled, filter table does not decide packet acceptance1 = Enabled, filter table decides acceptance of 802.1q packets sticky reset 0b [ 0h ] access RW ---------------- range 17-16 acronym BSIZE description Receive Buffer Size. Combined with RCTL.BSEX to program the receive buffer size. Control of receive buffer size permits software to trade-off descriptor performance versus required storage space. Buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes. RCTL.BSEX = 0 / RCTL.BSIZE = 00 -> Receive Buffer Size = 2048B RCTL.BSEX = 0 / RCTL.BSIZE = 01 -> Receive Buffer Size = 1024B RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive Buffer Size = 512B RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size = 256B RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved RCTL.BSEX = 1 / RCTL.BSIZE = 01 -> Receive Buffer Size = 16384B RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive Buffer Size = 8192B RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size = 4096B sticky reset 00b [ 0h ] access RW ---------------- range 15 acronym BAM description Broadcast Accept Mode. 0 = Ignore broadcast (unless it matches exact or imperfect filters)1 = Accept broadcast packets sticky reset 0b [ 0h ] access RW ---------------- range 14 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ---------------- range 13-12 acronym MO description Multicast Offset. This determines which bits of the incoming multicast address are used in looking up the bit vector. ? 00 = [47:36] ? 01 = [46:35] ? 10 = [45:34] ? 11 = [43:32] sticky reset 00b [ 0h ] access RW ---------------- range 11-10 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 9-8 acronym RDMTS description Receive Descriptor Minimum Threshold Size. These bits determines the threshold value for free receive descriptors. The corresponding interrupt is set whenever the fractional number of free descriptors becomes equal to RCTL.RDMTS. Refer to "RDLEN - Receive Descriptor Length Register" on page 1481 for further information. ? 00 = 1/2 ? 01 = 1/4 ? 10 = 1/8 ? 11 = Reserved sticky reset 00b [ 0h ] access RW ---------------- range 7-6 acronym LBM description Loopback mode. These bits enable the loopback function.When using a PHY, a value of 00 should be used and the PHY is configured for loopback through the MDIO interface. ? 00 = Normal operation (or PHY loopback in GMII/MII mode) ? 01 = MAC Loopback enable (only supported for GMII/MII mode) ? 10 = Reserved ? 11 = Reserved ? 11 = ReservedNote:PHY devices require programming for loopback operation using MDIO accesses.Note:The GbE must be configured for Full-Duplex operation if Mac Loopback mode is enabled. sticky reset 00b [ 0h ] access RW ---------------- range 5 acronym LPE description Long packet enable. This bit controls whether long packet reception is permitted. 0 = Disabled, hardware discards packets longer than 1522B1 = Enabled, 16384B is the maximum packet size that the GbE can receive sticky reset 0b [ 0h ] access RW ---------------- range 4 acronym MPE description Multicast promiscuous enable. 0 = Disabled1 = Enabled sticky reset 0b [ 0h ] access RW ---------------- range 3 acronym UPE description Unicast promiscuous enable. 0 = Disabled1 = Enabled sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym SBP description Store bad packets. 0 = Disabled1 = Enabled sticky reset 0b [ 0h ] access RW ---------------- range 1 acronym EN description Receiver Enable. 0 = All incoming packets are immediately dropped and are not stored in the receive FIFO. If a packet is already in-progress when disabled it will be finished.1 = Incoming packet reception is enabled. sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ============================================================ 2160h FCRTL table_ref 37-51 offset 2160h reg_name FCRTL recurring None reg_base_name FCRTL title_desc Flow Control Receive Threshold Low Register description None view PCI 3 bar CSRBAR offset_start 2160h offset_end 2163h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31 acronym XONE description XON Enable 0b = Disabled. 1b = Enabled. When set, enables the Ethernet controller to transmit XON packets based on receive FIFO crosses FCRTL.RTL threshold value, or based on external pins XOFF and XON. See Section 37.6.4.3, "FCRTH - Flow Control Receive Threshold High Register" on page 1479 sticky reset 0b [ 0h ] access RW ---------------- range 30-16 acronym Rsvd description Reserved sticky reset 000000000000000b [ 0000h ] access RV ---------------- range 15-3 acronym RTL description Receive Threshold Low. FIFO low water mark for flow control transmission. sticky reset 0000000000000b [ 0000h ] access RW ---------------- range 2-0 acronym 0 description Writes are ignored, reads return 0. sticky reset 000b [ 0h ] access RV ============================================================ 2168h FCRTH table_ref 37-52 offset 2168h reg_name FCRTH recurring None reg_base_name FCRTH title_desc Flow Control Receive Threshold High Register description None view PCI 3 bar CSRBAR offset_start 2168h offset_end 216bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31 acronym XFCE description External Flow Control Enabled 0b = Disabled. 1b = Enabled. Allows the Ethernet controller to send XOFF and XON frames based on external pins XOFF and XON. The transmission of pause frames must be also enabled through the CTRL.TFCE control bit. When the XOFF signal is asserted high, the Ethernet controller transmits a single XOFF frame. The assertion of XON (after deassertion of XOFF) initiates an XON frame transmission, if enabled by FCRTL.XONE. The assertion/deassertion of XON is required between assertions of XOFF in order to send another XOFF frame. This behavior also provides a built-in hysteresis mechanism. Note:The EP80579 does not have external XON/XOFF pins and therefore does not support external flow control enable. This bit must be set to 0 for correct operation. sticky reset 0b [ 0h ] access RW ---------------- range 30-16 acronym Rsvd description Reserved sticky reset 000000000000000b [ 0000h ] access RV ---------------- range 15-3 acronym RTH description Receive Threshold High. FIFO high water mark for flow control transmission. sticky reset 0000000000000b [ 0000h ] access RW ---------------- range 2-0 acronym 0 description Writes are ignored, reads return 0. sticky reset 000b [ 0h ] access RV ============================================================ 2800h RDBAL table_ref 37-53 offset 2800h reg_name RDBAL recurring None reg_base_name RDBAL title_desc Receive Descriptor Base Address Low Register description None view PCI 3 bar CSRBAR offset_start 2800h offset_end 2803h power_well Gbe1/2: size 32 default XXXXXXX0h bus_device_function M:2:0 ---------------- range 31-4 acronym RDBAL description Receive Descriptor Base Address Low sticky reset None <warning> access RW ---------------- range 3-0 acronym 0 description Writes are ignored, reads return 0. sticky reset 0000b [ 0h ] access RV ============================================================ 2804h RDBAH table_ref 37-54 offset 2804h reg_name RDBAH recurring None reg_base_name RDBAH title_desc Receive Descriptor Base Address High Register description None view PCI 3 bar CSRBAR offset_start 2804h offset_end 2807h power_well Gbe1/2: size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym RDBAH description Receive Descriptor Base Address.Note:RDBAH[31:0] must be set to 0. sticky reset None <warning> access RW ============================================================ 2808h RDLEN table_ref 37-55 offset 2808h reg_name RDLEN recurring None reg_base_name RDLEN title_desc Receive Descriptor Length Register description None view PCI 3 bar CSRBAR offset_start 2808h offset_end 280bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-20 acronym Rsvd description Reserved sticky reset 000000000000b [ 000h ] access RV ---------------- range 19-7 acronym LEN description Descriptor Length sticky reset 0000000000000b [ 0000h ] access RW ---------------- range 6-0 acronym 0 description Writes are ignored, reads return 0. sticky reset 0000000b [ 00h ] access RV ============================================================ 2810h RDH table_ref 37-56 offset 2810h reg_name RDH recurring None reg_base_name RDH title_desc Receive Descriptor Head Register description None view PCI 3 bar CSRBAR offset_start 2810h offset_end 2813h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym RDH description Receive Descriptor Head sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 2818h RDT table_ref 37-57 offset 2818h reg_name RDT recurring None reg_base_name RDT title_desc Receive Descriptor Tail Register description None view PCI 3 bar CSRBAR offset_start 2818h offset_end 281bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym RDT description Receive Descriptor Tail sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 2820h RDTR table_ref 37-58 offset 2820h reg_name RDTR recurring None reg_base_name RDTR title_desc RX Interrupt Delay Timer (Packet Timer) Register description None view PCI 3 bar CSRBAR offset_start 2820h offset_end 2823h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31 acronym FPD description Flush Partial Descriptor. Writing this bit with 1 initiates an immediate expiration of the timer, causing a writeback of any consumed receive descriptors pending writeback, and results in a receive timer interrupt in the ICR register. This bit is self clearing and always reads 0. sticky reset 0b [ 0h ] access WO ---------------- range 30-16 acronym Rsvd description Reserved sticky reset 000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym RPDT description Receive Packet Delay Timer Timer increments are RMII: 1.28 microseconds RGMII: 1.024 microseconds. See register description above sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 2828h RXDCTL table_ref 37-59 offset 2828h reg_name RXDCTL recurring None reg_base_name RXDCTL title_desc Receive Descriptor Control Register description None view PCI 3 bar CSRBAR offset_start 2828h offset_end 282bh power_well Gbe1/2: size 32 default 00010000h bus_device_function M:2:0 ---------------- range 31-25 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 24 acronym GRAN description Granularity of the thresholds in this register. 0 = Threshold values are in units of Cache Lines, thresholds specified must not be greater than 31 descriptors (496B) or 15 32B cache lines.1 = Threshold values are in units of Descriptors (16B each) sticky reset 0b [ 0h ] access RW ---------------- range 23-22 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 21-16 acronym WTHRESH description Write-back Threshold. This field controls the write-back of processed receive descriptors. This threshold refers to the number of receive descriptors in the GbE hardware buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back will occur only after more than WTHRESH descriptors are available for write-back.Note:Since the default value for this field is 1, the descriptors are normally written back as soon as one cache line is available. This field must contain a non-zero value to take advantage of the write-back bursting capabilities of the EP80579's GbE. sticky reset 000001b [ 01h ] access RW ---------------- range 15-14 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 13-8 acronym HTHRESH description Host Threshold. This field is used to control the fetching of descriptors from host memory. This threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched. sticky reset 000000b [ 00h ] access RW ---------------- range 7-6 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 5-0 acronym PTHRESH description Prefetch Threshold. This field is used to control when a prefetch of descriptors will be considered. This threshold refers to the number of valid, unprocessed receive descriptors the chip has in its GbE hardware buffer. If this number drops below PTHRESH, the algorithm will consider pre-fetching descriptors from host memory. This fetch will not happen however unless there are at least HTHRESH valid descriptors in host memory to fetch. sticky reset 000000b [ 00h ] access RW ============================================================ 282ch RADV table_ref 37-60 offset 282ch reg_name RADV recurring None reg_base_name RADV title_desc Receive Interrupt Absolute Delay Timer Register description None view PCI 3 bar CSRBAR offset_start 282ch offset_end 282fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym RADT description Receive Absolute Delay Timer Receive Absolute delay timer measured in increments of RMII: 1.28 microseconds RGMII: 1.024 microseconds. (0b =disabled) If the packet delay timer is used to coalesce receive interrupts, the Ethernet controller ensures that when receive traffic abates, an interrupt is generated within a specified interval of no receives. During times when receive traffic is continuous, it may be necessary to ensure that no receive remains unnoticed for too long an interval. This register can be used to ENSURE that a receive interrupt occurs at some predefined interval after the first packet is received. When this timer is enabled, a separate absolute countdown timer is initiated upon successfully receiving each packet to system memory. When this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated. Setting this register to 0b disables the absolute timer mechanism (the RDTR register should be used with a value of 0b to cause immediate interrupts for all receive packets). Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending RADV interrupt. If enabled, the RADV countdown timer is reloaded but halted, so as to avoid generation of a spurious second interrupt after the RDTR has been noted. sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 2c00h RSRPD table_ref 37-61 offset 2c00h reg_name RSRPD recurring None reg_base_name RSRPD title_desc Receive Small Packet Detect Interrupt Register description None view PCI 3 bar CSRBAR offset_start 2c00h offset_end 2c03h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-12 acronym Rsvd description Reserved sticky reset 00000000000000000000b [ 00000h ] access RV ---------------- range 11-0 acronym SIZE description Any packet received that is <= SIZE will assert an interrupt condition (ICR.SRPD). This field is specified in bytes and includes the headers and the CRC but not the VLAN header in the size calculation. sticky reset 000000000000b [ 000h ] access RW ============================================================ 5000h RXCSUM table_ref 37-62 offset 5000h reg_name RXCSUM recurring None reg_base_name RXCSUM title_desc Receive Checksum Control Register description None view PCI 3 bar CSRBAR offset_start 5000h offset_end 5003h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-10 acronym Rsvd description Reserved sticky reset 0000000000000000000000b [ 000000h ] access RV ---------------- range 9 acronym TUOFL description TCP/UDP Checksum Off load Enable. This bit is used to enable the TCP/UDP Checksum off-loading feature. 0 = TCP/UDP Checksum Off load Disabled1 = Hardware will calculate the TCP or UDP checksum and indicate a pass/fail indication to software via the TCP/UDP Checksum Error bit (TCPE). sticky reset 0b [ 0h ] access RW ---------------- range 8 acronym IPOFL description IP Checksum Off load Enable. This bit is used to enable the IP Checksum off-loading feature. 0 = IP Checksum Off load Disabled1 = Hardware will calculate the IP checksum and indicate a pass/fail indication to software via the IP Checksum Error bit (IPE) in the ERROR field of the receive descriptor. sticky reset 0b [ 0h ] access RW ---------------- range 7-0 acronym PCSS description Packet Checksum Start. This field controls the starting byte for the Packet Checksum calculation. The Packet Checksum is the one's complement over the receive packet, starting from the byte indicated by PCSS (0 corresponds to the first byte of the packet), after stripping. For example, for an Ethernet II frame encapsulated as an 802.3ac VLAN packet and with PCSS set to 14, the packet checksum would include the entire encapsulated frame, excluding the 14-byte Ethernet header (DA, SA, Type and Length) and the 4-byte VLAN tag. The Packet Checksum will not include the Ethernet CRC if the RCTL.SECRC bit is set. Software must make the required offsetting computation (to back out the bytes that should not have been included and to include the pseudo-header) prior to comparing the Packet Checksum against the TCP checksum stored in the packet. sticky reset 00000000b [ 00h ] access RW ============================================================ 5200h MTA[0-127] table_ref 37-63 offset 5200h reg_name MTA[0-127] recurring 128 reg_base_name MTA title_desc 128 Multicast Table Array Registers description None view PCI 3 bar CSRBAR offset_start 5200h at 4h offset_end 5203h at 4h power_well Gbe1/2: size 32 default XXXX_XXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym Vector description 32b vector of multicast address filter table information. sticky reset None <warning> access RW ============================================================ 5400h RAL[0-15] table_ref 37-64 offset 5400h reg_name RAL[0-15] recurring 16 reg_base_name RAL title_desc Receive Address Low Register description None view PCI 3 bar CSRBAR offset_start 5400h at 8h offset_end 5403h at 8h power_well None size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym RAL description Receive Address Low. The lower 32 bits of the 48 bit Ethernet address. sticky reset None <warning> access RW ============================================================ 5404h RAH[0-15] table_ref 37-65 offset 5404h reg_name RAH[0-15] recurring 16 reg_base_name RAH title_desc Receive Address High Register description None view PCI 3 bar CSRBAR offset_start 5404h at 8h offset_end 5407h at 8h power_well None size 32 default 000XXXXXh bus_device_function M:2:0 ---------------- range 31 acronym AV description Address valid. This bit determines whether this address is compared against the incoming packet. Cleared after software reset or Unit Reset. 0 = No match on this address field 1 = Match on this address field sticky reset 0b [ 0h ] access RW ---------------- range 30-18 acronym Rsvd description Reserved sticky reset 0000000000000b [ 0000h ] access RV ---------------- range 17-16 acronym ASEL description Address Select. Selects how the address is to be used when performing special filtering on receive packets. ? 00: Destination address (must be set to this in normal mode) ? 01: Source address ? 10: Reserved ? 11: Reserved sticky reset None <warning> access RW ---------------- range 15-0 acronym RAH description Receive Address High. The upper 16 bits of the 48 bit Ethernet address. sticky reset None <warning> access RW ============================================================ 5600h VFTA[0-127] table_ref 37-66 offset 5600h reg_name VFTA[0-127] recurring 128 reg_base_name VFTA title_desc 128 VLAN Filter Table Array Registers description None view PCI 3 bar CSRBAR offset_start 5600h at 4h offset_end 5603h at 4h power_well Gbe1/2: size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym VLAN_Vector description VLAN_Vector 32b vector of VLAN filter table information. sticky reset None <warning> access RW ============================================================ 400h TCTL table_ref 37-67 offset 400h reg_name TCTL recurring None reg_base_name TCTL title_desc Transmit Control Register description None view PCI 3 bar CSRBAR offset_start 400h offset_end 403h power_well Gbe1/2: size 32 default 00000008h bus_device_function M:2:0 ---------------- range 31-25 acronym Rsvd description Reserved sticky reset 0000000b [ 00h ] access RV ---------------- range 24 acronym RTLC description Re-Transmit on Late Collision. This bit configures the hardware to perform retransmission of packets when a late collision is detected. Note that the collision window is speed dependent: 64B for 10/100 Mbps and 512B for 1Gbps operation. If a late collision is detected when this bit is clear, the transmit function assumes the packet is successfully transmitted.Note:This bit is ignored in full-duplex mode. sticky reset 0b [ 0h ] access RW ---------------- range 23 acronym PBE description Packet Burst Enable. The EP80579's GbE does not support Packet Bursting for 1Gbps half-duplex transmit operation. This bit must be set to 0. sticky reset 0b [ 0h ] access RV ---------------- range 22 acronym SWXOFF description Software XOFF Transmission. When set to a 1 the device will schedule the transmission of an XOFF (PAUSE) frame using the current value of the PAUSE timer. This bit clears itself upon transmission of the XOFF frame.Note:While 802.3x flow control is only defined during full duplex operation, the sending of PAUSE frames via the SWXOFF bit is not gated by the duplex settings within the device. Software should not write a 1 to this bit while the device is configured for half duplex operation. sticky reset 0b [ 0h ] access RW ---------------- range 21-12 acronym COLD description Collision Distance. Wire speeds of 1Gbps result in a very short collision radius with traditional minimum packet sizes. This bit specifies the minimum number of bytes in the packet to satisfy the desired collision distance for proper CSMA/CD operation. It is important to note that the resulting packet has special characters appended to the end, not regular data characters. Hardware strips special characters for packets that go from 1 Gbps environments to 100 Mbps environments.Note:The hardware checks and pads to this value even in full-duplex operation. sticky reset 0000000000b [ 000h ] access RW ---------------- range 11-4 acronym CT description Collision Threshold. Software may choose to abort packet transmission in less than the Ethernet mandated 16 collisions. This field determines the number of attempts at retransmission prior to giving up on the packet (not including the first transmission attempt). The Ethernet back-off algorithm is implemented and clamps to the maximum number of slot-times after 10 retries. This field only has meaning when in half-duplex operation.Note:While this field can be varied, it should be set to a value of 15 in order to comply with the IEEE specification requiring a total of 16 attempts. sticky reset 00000000b [ 00h ] access RW ---------------- range 3 acronym PSP description Pad Short Packets to 64B with valid data characters, NOT padding symbols. 0 = Do not pad short packets1 = Pad short packetsNote:This is not the same as the mini-mum collision distance. sticky reset 1b [ 1h ] access RW ---------------- range 2 acronym Rsvd description Reserved. sticky reset 0b [ 0h ] access RV ---------------- range 1 acronym EN description Enable. 0 = Writing this bit to 0 will stop transmission after any in progress packets are sent. Data remains in the transmit FIFO until the device is re-enabled. Software should combine this with reset if the packets in the FIFO should be flushed.1 = The transmitter is enabled. sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym Rsvd description Reserved. sticky reset 0b [ 0h ] access RV ============================================================ 410h TIPG table_ref 37-68 offset 410h reg_name TIPG recurring None reg_base_name TIPG title_desc Transmit IPG Register description None view PCI 3 bar CSRBAR offset_start 410h offset_end 413h power_well Gbe1/2: size 32 default 00602008h bus_device_function M:2:0 ---------------- range 31-30 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 29-20 acronym IPGR2 description IPG Receive Time 2. Specifies the total length of the IPG time for non back-to-back transmissions. Measured in increments of the MAC clock: ? 8 ns MAC clock when operating @ 1 Gbps (82544GC/EI only). ? 80 ns MAC clock when operating @ 100 Mbps ? 800 ns MAC clock when operating @ 10 Mbps. In order to calculate the actual IPG value, a value of six should be added to the IPGR2 value as six MAC clocks are used by the MAC for synchronization and internal engines. For the IEEE 802.3 standard IPG value of 96-bit time, the value that should be programmed into IPGR2 is six (total IPG delay of 12 MAC clock cycles) According to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value.IPGR2 is significant only in half-duplex mode of operation. sticky reset 0000000110b [ 006h ] access RW ---------------- range 19-10 acronym IPGR1 description IPG Receive Time 1. Specifies the length of the first part of the IPG time for non back-to- back transmissions. During this time, the internal IPG counter restarts if any carrier event occurs. Once the time specified in IPGR1 has elapsed, carrier sense does not affect the IPG counter. According to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value. Measured in increments of the MAC clock: ? 8 ns MAC clock when operating @ 1 Gbps ? 80 ns MAC clock when operating @ 100 Mbps ? 800 ns MAC clock when operating @ 10 Mbps. For IEEE 802.3 minimum IPG value of 96-bit time, the value that should be programmed into IPGR1 is eight. IPGR1 is significant only in half-duplex mode of operation. sticky reset 0000001000b [ 008h ] access RW ---------------- range 9-0 acronym IPGT description IPG Transmit Time Specifies the IPG time for back-to-back packet transmissions Measured in increments of the MAC clock: ? 8 ns MAC clock when operating @ 1 Gbps. ? 80 ns MAC clock when operating @ 100 Mbps. ? 800 ns MAC clock when operating @ 10 Mbps. To calculate the IPG value for 10/100/1000BASE-T applications, a value of four should be added to the IPGT value as four clocks are used by the MAC as internal overhead. The value that should be programmed into IPGT is 8. These values are recommended to assure that the minimum IPG gap is met under all synchronization conditions. sticky reset 0000001000b [ 008h ] access RW ============================================================ 458h AIT table_ref 37-69 offset 458h reg_name AIT recurring None reg_base_name AIT title_desc Adaptive IFS Throttle Register description None view PCI 3 bar CSRBAR offset_start 458h offset_end 45bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym AIFS description Adaptive IFS Value Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the CSMA/CD transmit function. Normally, this register should be set to 0b. However, if additional delay is desired between back-to-back transmit packets, then this register can be set with a value greater than zero (0). This feature can be helpful in high collision half-duplex environments. In order for AIFS to take effect it should be larger than the minimum IFS value defined in IEEE 802.3 standard. AIFS has no effect on transmissions that occur immediately after receives or transmissions that are not back-to-back. In addition, it has no effect on re-transmission timing (retransmission after collisions). The AIFS value is additive to the TIPG.IPGT value. This time unit for this value is speed dependent: 1000Mbps is 8ns 100Mbps is 80ns 10 Mbps is 800ns sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 3800h TDBAL table_ref 37-70 offset 3800h reg_name TDBAL recurring None reg_base_name TDBAL title_desc Transmit Descriptor Base Address Low Register description None view PCI 3 bar CSRBAR offset_start 3800h offset_end 3803h power_well Gbe1/2: size 32 default XXXXXXX0h bus_device_function M:2:0 ---------------- range 31-4 acronym TDBAL description Transmit Descriptor Base Address Low sticky reset None <warning> access RW ---------------- range 3-0 acronym 0 description Writes are ignored, reads return 0. sticky reset 0000b [ 0h ] access RV ============================================================ 3804h TDBAH table_ref 37-71 offset 3804h reg_name TDBAH recurring None reg_base_name TDBAH title_desc Transmit Descriptor Base Address High Register description None view PCI 3 bar CSRBAR offset_start 3804h offset_end 3807h power_well Gbe1/2: size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym TDBAH description Transmit Descriptor Base AddressNote:TDBAH[31:0] must be set to 0. sticky reset None <warning> access RW ============================================================ 3808h TDLEN table_ref 37-72 offset 3808h reg_name TDLEN recurring None reg_base_name TDLEN title_desc Transmit Descriptor Length Register description None view PCI 3 bar CSRBAR offset_start 3808h offset_end 380bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-20 acronym Rsvd description Reserved sticky reset 000000000000b [ 000h ] access RV ---------------- range 19-7 acronym LEN description Descriptor Length sticky reset 0000000000000b [ 0000h ] access RW ---------------- range 6-0 acronym 0 description Writes are ignored, reads return 0. sticky reset 0000000b [ 00h ] access RV ============================================================ 3810h TDH table_ref 37-73 offset 3810h reg_name TDH recurring None reg_base_name TDH title_desc Transmit Descriptor Head Register description None view PCI 3 bar CSRBAR offset_start 3810h offset_end 3813h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym TDH description Transmit Descriptor Head sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 3818h TDT table_ref 37-74 offset 3818h reg_name TDT recurring None reg_base_name TDT title_desc Transmit Descriptor Tail Register description None view PCI 3 bar CSRBAR offset_start 3818h offset_end 381bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym TDT description Transmit Descriptor Tail sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 3820h TIDV table_ref 37-75 offset 3820h reg_name TIDV recurring None reg_base_name TIDV title_desc Transmit Interrupt Delay Value Register description None view PCI 3 bar CSRBAR offset_start 3820h offset_end 3823h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym IDV description Interrupt Delay Value. Timer increments are RMII: 1.28 microseconds RGMII: 1.024 microseconds. ? This register is used to delay interrupt notification for transmit operations by coalescing interrupts for multiple transmitted buffers. Delaying interrupt notification helps maximize the amount of transmit buffers reclaimed by a single interrupt. This feature only applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set). ? This feature operates by initiating a countdown timer upon successfully transmitting the buffer. If a subsequent transmit delayed-interrupt is scheduled before the timer expires, the timer is re-initialized to the programmed value and re-starts its countdown. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated. ? Hardware always loads the transmit interrupt counter whenever it processes a descriptor with IDE set even if it is already counting down due to a previous descriptor. ? Setting the value to 0 is not allowed. If an immediate (non-scheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0. ? The occurrence of either an immediate (non-scheduled) or absolute transmit timer interrupt will halt the TIDV timer and eliminate any spurious second interrupts. ? Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or an immediate interrupt (RS =1, IDE=0) will cancel a pending TIDV interrupt. The TIDV countdown timer is reloaded but halted, though it may be restarted by a processing a subsequent transmit descriptor. sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 3828h TXDCTL table_ref 37-76 offset 3828h reg_name TXDCTL recurring None reg_base_name TXDCTL title_desc Transmit Descriptor Control Register description None view PCI 3 bar CSRBAR offset_start 3828h offset_end 382bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-25 acronym LWTHRESH description Transmit Descriptor Low Threshold. This field controls the number of pre-fetched transmit descriptors at which a transmit descriptor-low interrupt is reported. Asserting ICR.TXD_LOW only when the processing distance from the TDT register drops below LWTHRESH may allow software to operate more efficiently by maintaining a continuous addition of transmit work, interrupting only when the hardware nears completion of all submitted work. An interrupt condition is asserted when the number of descriptors available transitions from threshold_level + 1 -> threshold_level where LWTHRESH specifies a multiple of 8 descriptors, (i.e. threshold_level = 8*LWTHRESH). Setting this value to 0 will cause this interrupt to be generated only when the transmit descriptor cache becomes completely empty. sticky reset 0000000b [ 00h ] access RW ---------------- range 24 acronym GRAN description Granularity of the thresholds in this register. 0 = Cache Lines1 = Descriptors (16B each) sticky reset 0b [ 0h ] access RW ---------------- range 23-22 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 21-16 acronym WTHRESH description Write-back Threshold. This field controls the write-back of processed transmit descriptors. This threshold refers to the number of transmit descriptors in the GbE hardware buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back will occur only after more than WTHRESH descriptors are available for write-back. Since write-back notification of transmit descriptor completion is optional (under the control of the RS bit in the descriptor), not all processed descriptors are counted with respect to WTHRESH (any single transmit descriptor with RS=0 is consumed with no writeback notification performed). When WTHRESH is non-zero, processing a descriptor with RS=1 initiates accumulation of pending writebacks; accumulated writebacks will include even those descriptors with RS=0, in order to optimize writeback bursts.Note:When WTHRESH value is set to 0, transmit descriptor writeback notification will be similar to the 82452 behavior. In accordance with WTHRESH=0, the writeback notification for a descriptor with RS=1 will occur as soon as the descriptor is processed. In addition, processed transmit descriptors are not written-back in entirety; only the descriptor status field is written back/ updated. This 82542-compatible mode is the default HW behavior. sticky reset 000000b [ 00h ] access RW ---------------- range 15-14 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 13-8 acronym HTHRESH description Host Threshold. This field is used to control the fetching of descriptors from host memory. This threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched. sticky reset 000000b [ 00h ] access RW ---------------- range 7-6 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 5-0 acronym PTHRESH description Prefetch Threshold. This field is used to control when a prefetch of descriptors will be considered. This threshold refers to the number of valid, unprocessed transmit descriptors the chip has in its GbE hardware buffer. If this number drops below PTHRESH, the algorithm will consider pre-fetching descriptors from host memory. This fetch will not happen however unless there are at least HTHRESH valid descriptors in host memory to fetch. sticky reset 000000b [ 00h ] access RW ============================================================ 382ch TADV table_ref 37-77 offset 382ch reg_name TADV recurring None reg_base_name TADV title_desc Transmit Absolute Interrupt Delay Value Register description None view PCI 3 bar CSRBAR offset_start 382ch offset_end 382fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-16 acronym Rsvd description Reserved sticky reset 0000000000000000b [ 0000h ] access RV ---------------- range 15-0 acronym IDV description Interrupt Delay Value. Timer increments are RMII: 1.28 microseconds RGMII: 1.024 microseconds. The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts. However, it might be necessary to ensure that no completed transmit remains unnoticed for too long an interval in order ensure timely release of transmit buffers. This register can be used to ENSURE that a transmit interrupt occurs at some predefined interval after a transmit is completed. Like the delayed-transmit timer, the absolute transmit timer ONLY applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set). This feature operates by initiating a countdown timer upon successfully transmitting the buffer. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated. The occurrence of either an immediate (non-scheduled) or delayed transmit timer (TIDV) expiration interrupt halts the TADV timer and eliminates any spurious second interrupts. Setting the value to 0b disables the transmit absolute delay function. If an immediate (nonscheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0b.Note:This timer ONLY causes an interrupt. It does NOT cause a writeback sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 3830h TSPMT table_ref 37-78 offset 3830h reg_name TSPMT recurring None reg_base_name TSPMT title_desc TCP Segmentation Pad And Minimum Threshold Register description None view PCI 3 bar CSRBAR offset_start 3830h offset_end 3833h power_well Gbe1/2: size 32 default 01000400h bus_device_function M:2:0 ---------------- range 31-16 acronym TSPBP description TCP Segmentation Packet Buffer Padding, value is in bytes. This field allows software configuration of packet buffer space which must be reserved as "pad" for worst-case header insertion. To ensure that this value does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (maximum TCP HDRLEN + maximum MSS + TSPMT.TMPBP + 80 bytes). sticky reset 0000000100000000b [ 0100h ] access RW ---------------- range 15-0 acronym TSMT description TCP Segmentation Minimum Transfer, value is in bytes. The DMA will attempt to issue burst fetches for as much data as possible, and it is possible for the transmit DMA to cause the transmit packet buffer to approach fullness (less the pad specified). However, if the packet buffer empties slightly, the transmit DMA could initiate a series of small transfers. To further optimize the efficiency of the transmit DMA during TCP segmentation operation, the this TSPMT.TSMT field allows software configuration of the minimum number of bytes which the DMA should attempt to transfer in a single burst operation. The transmit DMA will use this value to refrain from issuing a burst read until at least TSPMT.TSMT bytes of data from the current data descriptor can be stored in the packet buffer. This check will be ignored if, after a series of DMA operations, the descriptor contains a smaller number of unfetched data bytes. To ensure that this minimum threshold does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (TSPMT.TSMT + TSPMT.TSPBP + 80 bytes). sticky reset 0000010000000000b [ 0400h ] access RW ============================================================ 4000h CRCERRS table_ref 37-79 offset 4000h reg_name CRCERRS recurring None reg_base_name CRCERRS title_desc CRC Error Count Register description None view PCI 3 bar CSRBAR offset_start 4000h offset_end 4003h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym CRCERRS description CRC error count sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4004h ALGNERRC table_ref 37-80 offset 4004h reg_name ALGNERRC recurring None reg_base_name ALGNERRC title_desc Alignment Error Count Register description None view PCI 3 bar CSRBAR offset_start 4004h offset_end 4007h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym ALGNERRC description Alignment error count sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 400ch RXERRC table_ref 37-81 offset 400ch reg_name RXERRC recurring None reg_base_name RXERRC title_desc Receive Error Count Register description None view PCI 3 bar CSRBAR offset_start 400ch offset_end 400fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym RXERRC description RX Error Count sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4010h MPC table_ref 37-82 offset 4010h reg_name MPC recurring None reg_base_name MPC title_desc Missed Packet Count Register description None view PCI 3 bar CSRBAR offset_start 4010h offset_end 4013h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym MPC description Missed Packets Count sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4014h SCC table_ref 37-83 offset 4014h reg_name SCC recurring None reg_base_name SCC title_desc Single Collision Count Register description None view PCI 3 bar CSRBAR offset_start 4014h offset_end 4017h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym SCC description Number of times a transmit encountered a single collision. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4018h ECOL table_ref 37-84 offset 4018h reg_name ECOL recurring None reg_base_name ECOL title_desc Excessive Collisions Count Register description None view PCI 3 bar CSRBAR offset_start 4018h offset_end 401bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym ECOL description Number of packets with more than 16 collisions sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 401ch MCC table_ref 37-85 offset 401ch reg_name MCC recurring None reg_base_name MCC title_desc Multiple Collision Count Register description None view PCI 3 bar CSRBAR offset_start 401ch offset_end 401fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym MCC description Number of times a successful transmit encountered multiple collisions. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4020h LATECOL table_ref 37-86 offset 4020h reg_name LATECOL recurring None reg_base_name LATECOL title_desc Late Collisions Count Register description None view PCI 3 bar CSRBAR offset_start 4020h offset_end 4023h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym LATECOL description Number of packets with late collisions sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4028h COLC table_ref 37-87 offset 4028h reg_name COLC recurring None reg_base_name COLC title_desc Collision Count Register description None view PCI 3 bar CSRBAR offset_start 4028h offset_end 402bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym COLC description Total number of collisions experienced by the transmitter sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4030h DC table_ref 37-88 offset 4030h reg_name DC recurring None reg_base_name DC title_desc Defer Count Register description None view PCI 3 bar CSRBAR offset_start 4030h offset_end 4033h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym DC description Number of defer events. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4034h TNCRS table_ref 37-89 offset 4034h reg_name TNCRS recurring None reg_base_name TNCRS title_desc Transmit with No CRS Count Register description None view PCI 3 bar CSRBAR offset_start 4034h offset_end 4037h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TNCRS description Number of transmissions without a CRS assertion from the PHY. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 403ch CEXTERR table_ref 37-90 offset 403ch reg_name CEXTERR recurring None reg_base_name CEXTERR title_desc Carrier Extension Error Count Register description None view PCI 3 bar CSRBAR offset_start 403ch offset_end 403fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym CEXTERR description Number of packets received with a carrier extension error. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4040h RLEC table_ref 37-91 offset 4040h reg_name RLEC recurring None reg_base_name RLEC title_desc Receive Length Error Count Register description None view PCI 3 bar CSRBAR offset_start 4040h offset_end 4043h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym RLEC description Number of packets with receive length errors. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4048h XONRXC table_ref 37-92 offset 4048h reg_name XONRXC recurring None reg_base_name XONRXC title_desc XON Received Count Register description None view PCI 3 bar CSRBAR offset_start 4048h offset_end 404bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym XONRXC description Number of XON packets received. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 404ch XONTXC table_ref 37-93 offset 404ch reg_name XONTXC recurring None reg_base_name XONTXC title_desc XON Transmitted Count Register description None view PCI 3 bar CSRBAR offset_start 404ch offset_end 404fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym XONTXC description Number of XON packets transmitted. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4050h XOFFRXC table_ref 37-94 offset 4050h reg_name XOFFRXC recurring None reg_base_name XOFFRXC title_desc XOFF Received Count Register description None view PCI 3 bar CSRBAR offset_start 4050h offset_end 4053h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym XOFFRXC description Number of XOFF packets received. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4054h XOFFTXC table_ref 37-95 offset 4054h reg_name XOFFTXC recurring None reg_base_name XOFFTXC title_desc XOFF Transmitted Count Register description None view PCI 3 bar CSRBAR offset_start 4054h offset_end 4057h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym XOFFTXC description Number of XOFF packets transmitted. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4058h FCRUC table_ref 37-96 offset 4058h reg_name FCRUC recurring None reg_base_name FCRUC title_desc FC Received Unsupported Count Register description None view PCI 3 bar CSRBAR offset_start 4058h offset_end 405bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym FCRUC description Number of unsupported flow control frames received sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 405ch PRC64 table_ref 37-97 offset 405ch reg_name PRC64 recurring None reg_base_name PRC64 title_desc Good Packets Received Count (64 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 405ch offset_end 405fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PRC64 description Number of good packets received exactly 64 bytes in length. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4060h PRC127 table_ref 37-98 offset 4060h reg_name PRC127 recurring None reg_base_name PRC127 title_desc Good Packets Received Count (65-127 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 4060h offset_end 4063h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PRC127 description Number of good packets received, (65-127) bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4064h PRC255 table_ref 37-99 offset 4064h reg_name PRC255 recurring None reg_base_name PRC255 title_desc Good Packets Received Count (128-255 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 4064h offset_end 4067h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PRC255 description Number of good packets received, (128-255) bytes in length. sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4068h PRC511 table_ref 37-100 offset 4068h reg_name PRC511 recurring None reg_base_name PRC511 title_desc Good Packets Received Count (256-511 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 4068h offset_end 406bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PRC511 description Number of good packets received, (256-511) bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 406ch PRC1023 table_ref 37-101 offset 406ch reg_name PRC1023 recurring None reg_base_name PRC1023 title_desc Good Packets Received Count (512-1023 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 406ch offset_end 406fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PRC1023 description Number of good packets received, (512-1023) bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4070h PRC1522 table_ref 37-102 offset 4070h reg_name PRC1522 recurring None reg_base_name PRC1522 title_desc Good Packets Received Count (1024 to Max Bytes) Register description None view PCI 3 bar CSRBAR offset_start 4070h offset_end 4073h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PRC1522 description Number of good packets received, (1024-Max) bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4074h GPRC table_ref 37-103 offset 4074h reg_name GPRC recurring None reg_base_name GPRC title_desc Good Packets Received Count (Total) Register description None view PCI 3 bar CSRBAR offset_start 4074h offset_end 4077h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym GPRC description Number of good packets received (total of all lengths) sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4078h BPRC table_ref 37-104 offset 4078h reg_name BPRC recurring None reg_base_name BPRC title_desc Broadcast Packets Received Count Register description None view PCI 3 bar CSRBAR offset_start 4078h offset_end 407bh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym BPRC description Number of broadcast packets received sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 407ch MPRC table_ref 37-105 offset 407ch reg_name MPRC recurring None reg_base_name MPRC title_desc Multicast Packets Received Count Register description None view PCI 3 bar CSRBAR offset_start 407ch offset_end 407fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym MPRC description Number of multicast packets received sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4080h GPTC table_ref 37-106 offset 4080h reg_name GPTC recurring None reg_base_name GPTC title_desc Good Packets Transmitted Count Register description None view PCI 3 bar CSRBAR offset_start 4080h offset_end 4083h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym GPTC description Number of good packets transmitted sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4088h GORCL table_ref 37-107 offset 4088h reg_name GORCL recurring None reg_base_name GORCL title_desc Good Octets Received Count Low Register description None view PCI 3 bar CSRBAR offset_start 4088h offset_end 408ah power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym GORCL description Number of good octets received - lower 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 408ch GORCH table_ref 37-108 offset 408ch reg_name GORCH recurring None reg_base_name GORCH title_desc Good Octets Received Count High Register description None view PCI 3 bar CSRBAR offset_start 408ch offset_end 408fh power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym GORCH description Number of good octets received - upper 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4090h GOTCL table_ref 37-109 offset 4090h reg_name GOTCL recurring None reg_base_name GOTCL title_desc Good Octets Transmitted Count Low Register description None view PCI 3 bar CSRBAR offset_start 4090h offset_end 4093h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym GOTCL description Number of good octets transmitted - lower 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 4094h GOTCH table_ref 37-110 offset 4094h reg_name GOTCH recurring None reg_base_name GOTCH title_desc Good Octets Transmitted Count High Register description None view PCI 3 bar CSRBAR offset_start 4094h offset_end 4097h power_well Gbe1/2: size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym GOTCH description Number of good octets transmitted - upper 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40a0h RNBC table_ref 37-111 offset 40a0h reg_name RNBC recurring None reg_base_name RNBC title_desc Receive No Buffers Count Register description None view PCI 3 bar CSRBAR offset_start 40a0h offset_end 40a3h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym RNBC description Number of receive no buffer conditions sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40a4h RUC table_ref 37-112 offset 40a4h reg_name RUC recurring None reg_base_name RUC title_desc Receive Undersize Count Register description None view PCI 3 bar CSRBAR offset_start 40a4h offset_end 40a7h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym RUC description Number of receive undersize errors sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40a8h RFC table_ref 37-113 offset 40a8h reg_name RFC recurring None reg_base_name RFC title_desc Receive Fragment Count Register description None view PCI 3 bar CSRBAR offset_start 40a8h offset_end 40abh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym RFC description Number of receive fragment errors sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40ach ROC table_ref 37-114 offset 40ach reg_name ROC recurring None reg_base_name ROC title_desc Receive Oversize Count Register description None view PCI 3 bar CSRBAR offset_start 40ach offset_end 40afh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym ROC description Number of receive oversize errors sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40b0h RJC table_ref 37-115 offset 40b0h reg_name RJC recurring None reg_base_name RJC title_desc Receive Jabber Count Register description None view PCI 3 bar CSRBAR offset_start 40b0h offset_end 40b3h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym RJC description Number of receive jabber errors sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40c0h TORL table_ref 37-116 offset 40c0h reg_name TORL recurring None reg_base_name TORL title_desc Total Octets Received Low Register description None view PCI 3 bar CSRBAR offset_start 40c0h offset_end 40c3h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TORL description Number of total octets received - lower 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40c4h TORH table_ref 37-117 offset 40c4h reg_name TORH recurring None reg_base_name TORH title_desc Total Octets Received High Register description None view PCI 3 bar CSRBAR offset_start 40c4h offset_end 40c7h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TORH description Number of total octets received - upper 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40c8h TOTL table_ref 37-118 offset 40c8h reg_name TOTL recurring None reg_base_name TOTL title_desc Total Octets Transmitted Low Register description None view PCI 3 bar CSRBAR offset_start 40c8h offset_end 40cfh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TOTL description Number of total octets transmitted - lower 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40cch TOTH table_ref 37-119 offset 40cch reg_name TOTH recurring None reg_base_name TOTH title_desc Total Octets Transmitted High Register description None view PCI 3 bar CSRBAR offset_start 40cch offset_end 40cfh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TOTH description Number of total octets transmitted - upper 4 bytes sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40d0h TPR table_ref 37-120 offset 40d0h reg_name TPR recurring None reg_base_name TPR title_desc Total Packets Received Register description None view PCI 3 bar CSRBAR offset_start 40d0h offset_end 40d3h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TPR description Total of all packets received sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40d4h TPT table_ref 37-121 offset 40d4h reg_name TPT recurring None reg_base_name TPT title_desc Total Packets Transmitted Register description None view PCI 3 bar CSRBAR offset_start 40d4h offset_end 40d7h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TPT description Number of all packets transmitted sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40d8h PTC64 table_ref 37-122 offset 40d8h reg_name PTC64 recurring None reg_base_name PTC64 title_desc Packets Transmitted Count (64 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 40d8h offset_end 40dbh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PTC64 description Number of all packets transmitted that are 64 bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40e0h PTC255 table_ref 37-123 offset 40e0h reg_name PTC255 recurring None reg_base_name PTC255 title_desc Packets Transmitted Count (128-255 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 40e0h offset_end 40e3h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PTC255 description Number of packets transmitted that are 128-255 bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40e4h PTC511 table_ref 37-124 offset 40e4h reg_name PTC511 recurring None reg_base_name PTC511 title_desc Packets Transmitted Count (256-511 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 40e4h offset_end 40e7h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PTC511 description Number of packets transmitted that are 256-511 bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40e8h PTC1023 table_ref 37-125 offset 40e8h reg_name PTC1023 recurring None reg_base_name PTC1023 title_desc Packets Transmitted Count (512-1023 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 40e8h offset_end 40ebh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PTC1023 description Number of packets transmitted that are 512-1023 bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40ech PTC1522 table_ref 37-126 offset 40ech reg_name PTC1522 recurring None reg_base_name PTC1522 title_desc Packets Transmitted Count (1024-1522 Bytes) Register description None view PCI 3 bar CSRBAR offset_start 40ech offset_end 40efh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym PTC1522 description Number of packets transmitted that are 1024 or more bytes in length sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40f0h MPTC table_ref 37-127 offset 40f0h reg_name MPTC recurring None reg_base_name MPTC title_desc Multicast Packets Transmitted Count Register description None view PCI 3 bar CSRBAR offset_start 40f0h offset_end 40f3h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym MPTC description Number of multicast packets transmitted sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40f4h BPTC table_ref 37-128 offset 40f4h reg_name BPTC recurring None reg_base_name BPTC title_desc Broadcast Packets Transmitted Count Register description None view PCI 3 bar CSRBAR offset_start 40f4h offset_end 40f7h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym BPTC description Number of broadcast packets transmitted count sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40f8h TSCTC table_ref 37-129 offset 40f8h reg_name TSCTC recurring None reg_base_name TSCTC title_desc TCP Segmentation Context Transmitted Count Register description None view PCI 3 bar CSRBAR offset_start 40f8h offset_end 40fbh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TSCTC description Number of TCP Segmentation contexts transmitted count sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 40fch TSCTFC table_ref 37-130 offset 40fch reg_name TSCTFC recurring None reg_base_name TSCTFC title_desc TCP Segmentation Context Transmit Fail Count Register description None view PCI 3 bar CSRBAR offset_start 40fch offset_end 40ffh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-0 acronym TSCTFC description Number of TCP Segmentation contexts where the device failed to transmit the entire data payload sticky reset 00000000000000000000000000000000b [ 00000000h ] access RC ============================================================ 5800h WUC table_ref 37-131 offset 5800h reg_name WUC recurring None reg_base_name WUC title_desc Wake Up Control Register (0x05800; RW) description None view PCI 3 bar CSRBAR offset_start 5800h offset_end 5803h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-4 acronym RSVD description Reserved sticky reset 0000000000000000000000000000b [ 0000000h ] access RO ---------------- range 3 acronym APMPME description Assert PME On APM Wakeup - If it is 1, the GbE will set the PME_Status bit in the Power Management Control / Status Register (PMCSR) and assert GBE_PME_WAKE when APM Wakeup is enabled and the GbE receives a matching magic packet. *Note that this bit is loaded from the EEPROM, if present sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym PME_Status description PME_Status This bit is set when the GbE receives a wakeup event. It is the same as the PME_Status bit in the Power Management Control / Status Register (PMCSR). Writing a "1" to this bit will clear it and clear the PME_Status bit in the PMCSR. sticky reset 0b [ 0h ] access RWC ---------------- range 1 acronym PME_EN description PME_En This read/write bit is used by the driver to access the PME_En bit of the Power Management Control / Status Register (PMCSR) without writing to PCI configuration space. sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym APME description Advance Power Management Enable - If "1", APM Wakeup is enabled. *Note that this bit is loaded from the EEPROM, if present sticky reset 0b [ 0h ] access RW ============================================================ 5808h WUFC table_ref 37-132 offset 5808h reg_name WUFC recurring None reg_base_name WUFC title_desc Wake Up Filter Control Register (0x05808; RW) description None view PCI 3 bar CSRBAR offset_start 5808h offset_end 580bh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-20 acronym RSVD description Reserved. Should be set to 0. sticky reset 000000000000b [ 000h ] access RV ---------------- range 19 acronym FLX3 description Flexible Filter 3 Enable sticky reset 0b [ 0h ] access RW ---------------- range 18 acronym FLX2 description Flexible Filter 2 Enable sticky reset 0b [ 0h ] access RW ---------------- range 17 acronym FLX1 description Flexible Filter 1 Enable sticky reset 0b [ 0h ] access RW ---------------- range 16 acronym FLX0 description Flexible Filter 0 Enable sticky reset 0b [ 0h ] access RW ---------------- range 15 acronym RSVD description Reserved. Should be set to 0. sticky reset 0b [ 0h ] access RW ---------------- range 14-8 acronym RSVD description Reserved. Should be set to 0. sticky reset 0000000b [ 00h ] access RV ---------------- range 7 acronym IPV6 description Directed IPv6 Packet Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 6 acronym IPV4 description Directed IPv4 Packet Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 5 acronym ARP description ARP/IPv4 Request Packet Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 4 acronym BC description Broadcast Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 3 acronym MC description Directed Multicast Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym EX description Directed Exact Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 1 acronym MAG description Magic Packet Wake Up Enable sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym Rsvd description Reserved sticky reset 0b [ 0h ] access RV ============================================================ 5810h WUS table_ref 37-133 offset 5810h reg_name WUS recurring None reg_base_name WUS title_desc Wake Up Status Register (0x05810; RW) description None view PCI 3 bar CSRBAR offset_start 5810h offset_end 5813h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-20 acronym RSVD description Reserved. Should be set to 0. sticky reset 000000000000b [ 000h ] access RV ---------------- range 19 acronym FLX3 description Flexible Filter 3 Match sticky reset 0b [ 0h ] access RWC ---------------- range 18 acronym FLX2 description Flexible Filter 2 Match sticky reset 0b [ 0h ] access RWC ---------------- range 17 acronym FLX1 description Flexible Filter 1 Match sticky reset 0b [ 0h ] access RWC ---------------- range 16 acronym FLX0 description Flexible Filter 0 Match sticky reset 0b [ 0h ] access RWC ---------------- range 15-8 acronym Reserved description Reserved. sticky reset 00000000b [ 00h ] access RV ---------------- range 7 acronym IPV6 description Directed IPv6 Packet Wake Up Packet Received sticky reset 0b [ 0h ] access RWC ---------------- range 6 acronym IPV4 description Directed IPv4 Packet Wake Up Packet Received sticky reset 0b [ 0h ] access RWC ---------------- range 5 acronym ARP description ARP/IPv4 Request Packet Wake Up Packet Received sticky reset 0b [ 0h ] access RWC ---------------- range 4 acronym BC description Broadcast Wake Up Packet Received sticky reset 0b [ 0h ] access RWC ---------------- range 3 acronym MC description Directed Multicast Wake Up Packet Received The packet was a multicast packet whose hashed to a value that corresponded to a 1 bit in the Multicast Table ArrayNote:If the MAC has been configured for promiscuous mode, a multicast wakeup will occur if a broadcast packet is received. This is because a broadcast message is a special type of multicast message. Refer to 802.3. sticky reset 0b [ 0h ] access RWC ---------------- range 2 acronym EX description Directed Exact Wake Up Packet Received The packet's address matched one of the 16 pre-programmed exact values in the Receive Address registers sticky reset 0b [ 0h ] access RWC ---------------- range 1 acronym MAG description Magic Packet Wake Up Packet Received sticky reset 0b [ 0h ] access RWC ---------------- range 0 acronym Rsvd description Reserved. Must be written as '0' sticky reset 0b [ 0h ] access RV ============================================================ 5838h IPAV table_ref 37-134 offset 5838h reg_name IPAV recurring None reg_base_name IPAV title_desc IP Address Valid Register (0x05838; RW) description None view PCI 3 bar CSRBAR offset_start 5838h offset_end 583bh power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-17 acronym RSVD description Reserved. Should be set to 0. sticky reset 000000000000000b [ 0000h ] access RV ---------------- range 16 acronym V60 description IPv6 Address 0 Valid sticky reset 0b [ 0h ] access RW ---------------- range 15-4 acronym RSVD description Reserved. Should be set to 0. sticky reset 000000000000b [ 000h ] access RV ---------------- range 3 acronym V43 description IPv4 Address 3 Valid sticky reset 0b [ 0h ] access RW ---------------- range 2 acronym V42 description IPv4 Address 2 Valid sticky reset 0b [ 0h ] access RW ---------------- range 1 acronym V41 description IPv4 Address 1 Valid sticky reset 0b [ 0h ] access RW ---------------- range 0 acronym V40 description IPv4 Address 0 Valid The initial value is loaded from the IP Address Valid bit of the EEPROM's Management Control Register sticky reset 0b [ 0h ] access RW ============================================================ 5880h IPV6_ADDR0BYTES_1_4 table_ref 37-136 offset 5880h reg_name IPV6_ADDR0BYTES_1_4 recurring None reg_base_name IPV6_ADDR0BYTES_1_4 title_desc IPv6 Address Table Register (0x5880), Bytes 1 - 4 description None view PCI 3 bar CSRBAR offset_start 5880h offset_end 5883h power_well None size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym IPV6ADDR0 description IPV6 Address0, bytes 1 - 4 sticky reset None <warning> access RW ============================================================ 5884h IPV6_ADDR0BYTES_5_8 table_ref 37-137 offset 5884h reg_name IPV6_ADDR0BYTES_5_8 recurring None reg_base_name IPV6_ADDR0BYTES_5_8 title_desc IPv6 Address Table Register, Bytes 5 - 8 description None view PCI 3 bar CSRBAR offset_start 5884h offset_end 588fh power_well None size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym IPV6ADDR1 description IPV6 Address, bytes 5 - 8 sticky reset None <warning> access RW ============================================================ 5888h IPV6_ADDR0BYTES_9_12 table_ref 37-138 offset 5888h reg_name IPV6_ADDR0BYTES_9_12 recurring None reg_base_name IPV6_ADDR0BYTES_9_12 title_desc IPv6 Address Table Register, Bytes 9 - 12 description None view PCI 3 bar CSRBAR offset_start 5888h offset_end 588bh power_well None size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym IPV6ADDR2 description IPV6 Address, bytes 9 - 12 sticky reset None <warning> access RW ============================================================ 588ch IPV6_ADDR0BYTES_13_16 table_ref 37-139 offset 588ch reg_name IPV6_ADDR0BYTES_13_16 recurring None reg_base_name IPV6_ADDR0BYTES_13_16 title_desc IPv6 Address Table Register, Bytes 13 - 16 description None view PCI 3 bar CSRBAR offset_start 588ch offset_end 588fh power_well None size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-0 acronym IPV6DDR3 description IPV6 Address, bytes 13 - 16 sticky reset None <warning> access RW ============================================================ 5f00h FFLT[0-3] table_ref 37-140 offset 5f00h reg_name FFLT[0-3] recurring 4 reg_base_name FFLT title_desc Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW) description None view PCI 3 bar CSRBAR offset_start 5f00h at 8h offset_end 5f03h at 8h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-11 acronym RSVD description Reserved sticky reset 000000000000000000000b [ 000000h ] access RV ---------------- range 10-0 acronym FFLT_LENx description Flexible Filter Length for FIlter x sticky reset 00000000000b [ 000h ] access RW ============================================================ 9000h FFMT[0-127] table_ref 37-142 offset 9000h reg_name FFMT[0-127] recurring 128 reg_base_name FFMT title_desc Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW) description None view PCI 3 bar CSRBAR offset_start 9000h at 8h offset_end 9003h at 8h power_well None size 32 default 0000000Xh bus_device_function M:2:0 ---------------- range 31-4 acronym RSVD description Reserved sticky reset 0000000000000000000000000000b [ 0000000h ] access RV ---------------- range 3-0 acronym Mask_x description Byte Mask for Byte xx sticky reset None <warning> access RW ============================================================ 9800h FFVT[0-127] table_ref 37-144 offset 9800h reg_name FFVT[0-127] recurring 128 reg_base_name FFVT title_desc Flexible Filter Value Table Registers description None view PCI 3 bar CSRBAR offset_start 9800h at 8h offset_end 9803h at 8h power_well None size 32 default XXXXXXXXh bus_device_function M:2:0 ---------------- range 31-24 acronym VAL3 description Byte x Compare Value 3 sticky reset None <warning> access RW ---------------- range 23-16 acronym VAL2 description Byte x Compare Value 2 sticky reset None <warning> access RW ---------------- range 15-8 acronym VAL1 description Byte x Compare Value 1 sticky reset None <warning> access RW ---------------- range 7-0 acronym VAL0 description Byte x Compare Value 0 sticky reset None <warning> access RW ============================================================ 510h INTBUS_ERR_STAT table_ref 37-145 offset 510h reg_name INTBUS_ERR_STAT recurring None reg_base_name INTBUS_ERR_STAT title_desc Internal Bus Error Status Register description None view PCI 3 bar CSRBAR offset_start 510h offset_end 513h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-13 acronym Rsvd description Reserved sticky reset 0000000000000000000b [ 00000h ] access RV ---------------- range 12 acronym INTBUS_ERR_H_DIS description 0 - Internal Bus errors will halt further GbE transmit/receive operation. 1 - Internal Bus errors will not halt further GbE operation. sticky reset [ 0b ] 0h access RW ---------------- range 11-6 acronym Rsvd description Reserved sticky reset 000000b [ 00h ] access RV ---------------- range 5-4 acronym Type description Internal Bus Error Type: ? 00 = Unsupported internal bus transaction targeted at GbE ? 01 = Pull data error detected during a target write transaction ? 10 = GbE received a Internal Bus Data Error response while mastering a DMA transaction ? 11 = Master Pull data error occurred as a result of an internal memory error sticky reset 00b [ 0h ] access RO ---------------- range 3-2 acronym Rsvd description Reserved sticky reset 00b [ 0h ] access RV ---------------- range 1 acronym MERR description Indicates whether one or more than one Internal Bus errors have occurred before INTBUS_ERR_STAT.CERR was cleared 0 = One Internal Bus Error1 = More than one Internal Bus Error sticky reset 0b [ 0h ] access RWC ---------------- range 0 acronym CERR description Internal Bus Error: Asserts when Internal Bus Error status and address registers are valid 0 = no error has been logged1 = Internal Bus Error status and address registers have logged an error If error handling is enabled (INTBUS_ERR_H_DIS = 0) then this bit can only be cleared by a reset. sticky reset 0b [ 0h ] access RWC ============================================================ 900h MEM_TST table_ref 37-146 offset 900h reg_name MEM_TST recurring None reg_base_name MEM_TST title_desc Memory Error Test Register description None view PCI 3 bar CSRBAR offset_start 900h offset_end 903h power_well None size 32 default 00000000h bus_device_function M:2:0 ---------------- range 31-19 acronym Rsvd description Reserved sticky reset 0000000000000b [ 0000h ] access RV ---------------- range 18-16 acronym Select description Selects the memory where the error mask is applied: 000 : None - no errors injected 001 : Statistics Registers 010 : Multicast Filter Memory 011 : Special Packet Filter Memory 100 : TX Descriptor Buffer 101 : RX Descriptor Buffer 110 : Packet Buffer 111 : Flexible Filter Memory sticky reset 000b [ 0h ] access RW ---------------- range 15-0 acronym Mask description ECC/Parity check bit XOR mask The Valid Mask bits are selected according to the Select field, as follows: 001 : 15:8 Reserved; 7:0 ECC Mask 010 : 15:4 Reserved; 3:0 Parity bit Mask 011 : 15:4 Reserved; 3:0 Parity bit Mask 100 : 15:0 ECC Mask 101 : 15:0 ECC Mask 110 : 15:0 ECC Mask 111 : 15:0 Reserved; 3:0 Parity bit Mask sticky reset 0000000000000000b [ 0000h ] access RW ============================================================ 904h MEM_STS table_ref 37-147 offset 904h reg_name MEM_STS recurring None reg_base_name MEM_STS title_desc Memory Error Status Register description None view PCI 3 bar CSRBAR offset_start 904h offset_end 907h power_well None size 32 default 007f0000h bus_device_function M:2:0 ---------------- range 31-23 acronym Rsvd description Reserved. sticky reset 000000000b [ 000h ] access RV ---------------- range 22 acronym ERR_FLEX_DIS description Flex Filter Parity Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 21 acronym ERR_STAT_DIS description Statistics Register ECC Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 20 acronym ERR_PKBUF_DIS description Packet Buffer ECC Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 19 acronym ERR_TXDS_DIS description Transmit Descriptor ECC Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 18 acronym ERR_RXDS_DIS description Receive Descriptor ECC Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 17 acronym ERR_SPF_DIS description Special Packets Filter Parity Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 16 acronym ERR_MF_DIS description Multicast Filter Parity Error Disable 0: Error trapping enabled 1: Error trapping disabled sticky reset 1b [ 1h ] access RW ---------------- range 15-13 acronym Rsvd description Reserved sticky reset 000b [ 0h ] access RV ---------------- range 12 acronym MEM_ERRH_DIS description Memory Error Handling Disable: Indicates, for the following error types, whether GbE Tx/Rx operation will be halted: ERR_STAT ERR_PKBUF ERR_RXDS ERR_TXDS 0: Memory Errors will halt further GbE Tx/Rx operation and a soft-reset is required to restore operation 1: Memory Errors will be logged, but will not halt further GbE Tx/Rx operation sticky reset 0b [ 0h ] access RW ---------------- range 11-7 acronym Rsvd description Reserved. sticky reset 00000b [ 00h ] access RV ---------------- range 6 acronym ERR_FLEX description Flex filter Parity Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC. sticky reset 0b [ 0h ] access RO/RWC ---------------- range 5 acronym ERR_STAT description Statistics Register ECC Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC sticky reset 0b [ 0h ] access RO/RWC ---------------- range 4 acronym ERR_PKBUF description Packet Buffer ECC 2-bit Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC. sticky reset 0b [ 0h ] access RO/RWC ---------------- range 3 acronym ERR_TXDS description Transmit Descriptor ECC 2-bit Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC. sticky reset 0b [ 0h ] access RO/RWC ---------------- range 2 acronym ERR_RXDS description Receive Descriptor ECC 2-bit Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC. sticky reset 0b [ 0h ] access RO/RWC ---------------- range 1 acronym ERR_SPF description Special Packets Filter Parity Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC sticky reset 0b [ 0h ] access RO/RWC ---------------- range 0 acronym ERR_MF description Multicast Filter Parity Error 0: No error occurred 1: Error occurred When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC sticky reset 0b [ 0h ] access RO/RWC