{'AAAAREG': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 2863311530L, 'description': 'AAAAREG: Fixed A Pattern', 'fields': [{'access': 'RO', 'acronym': 'AAAA', 'description': ['Hardwired to As for read-return '], 'range': (31, 0), 'reset': 2863311530L, 'sticky': 'N'}], 'offset': 236, 'offset_end': (239, None), 'offset_start': (236, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'AAAAREG', 'reg_name': 'AAAAREG', 'size': 32, 'table_ref': '16-256', 'title_desc': 'Fixed A Pattern Register', 'view': 'PCI'}, 'DCALADDR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DCALADDR - DCAL Address Register', 'fields': [{'access': 'RW', 'acronym': 'DCALADDR', 'description': ['DCAL Address and Other Information based on DCALCSR.OPCODE. See Table 16-230.'], 'range': (31, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 68, 'offset_end': (71, None), 'offset_start': (68, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DCALADDR', 'reg_name': 'DCALADDR', 'size': 32, 'table_ref': '16-229', 'title_desc': 'DCAL Address Register', 'view': 'PCI'}, 'DCALCSR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DCALCSR - DCAL Control and Status Register', 'fields': [{'access': 'RWS', 'acronym': 'START', 'description': ['Start Operation', 'When set to 1 by software, the operation selected by the DCALCSR.OPCODE is initiated. Hardware clears this bit when the operation is complete.'], 'range': (31, 31), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'FAIL', 'description': ['Completion Status', '1xx = Fail, 0xx = Pass', 'Note: Best practice is to rely on MemBIST following calibration to confirm a reliable DRAM interface.'], 'range': (30, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'BASPAT', 'description': ['Basic Data Pattern Enable: This controls which data pattern is used for the DQS Delay calibration. Setting this field enables the use of the basic data pattern selected by the DCALCSR.PATTERN bits. When cleared, the extended data pattern specified in the DDQSCVDP and DDQSCADP registers is used. Note: extended data pattern mode is not to be used in 2T configurations.'], 'range': (27, 27), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'RSTREGSS', 'description': ['Reset Registers in Single Step Mode: Reset DCALDATA CSR in single step calibration mode. This bit should be set during the first step of a single step calibration. It will enable hardware to clear all registers and status bits during the calibration step the same way hardware does on the first step of an automatic "all passes" calibration.'], 'range': (26, 26), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (25, 24), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'SGLSTP', 'description': ['Single Step Calibration Operation:', 'Applies only to Receive enable and DQS cal.', '"1" = Single step - a single step of the algorithm selected by the DCALCSR.OPCODE is run by hardware. No data analysis is run."0" = All passes - all steps of the algorithm selected by the DACLCSR.OPCODE is run by hardware including data analysis.'], 'range': (23, 23), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'CS', 'description': ['Chip select:', 'This field corresponds to the chip select outputs: CS[1:0]. This field Applies to NOP, Refresh, Precharge all, and MRS/EMRS commands. It also applies to Receive Enable, and DQS Delay cal in single step mode.', '01: select Rank 0', '10: select Rank 1', '00: Reserved', '11: ReservedNote:Set CS to 01 for Self Refresh Entry. Hardware will automatically detect presence of a second rank/DIMM and sequence Self Refresh Entry via both chip selects if necessary.'], 'range': (22, 21), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (20, 19), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'PAT', 'description': ['Data pattern: for DQS cal. This sets the burst length 4 pattern for a nibble of data. The pattern is repeated for BL8. This pattern is replicated on all nibbles of the data bus.', '"000" = F > 0 > F > 0"001" = 0 > F > 0 > F"010" = A > 5 > A > 5"011" = 5 > A > 5 > A"100" = C > 3 > C > 3"101" = 3 > C > 3 > C"110" = 9 > 6 > 9 > 6"111" = 6 > 9 > 6 > 9'], 'range': (18, 16), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DARWPR', 'description': ['Disable FIFO reset: in single pass mode.', 'Applies only to Receiver enable and DQS cal.', 'When set to 1, this bit inhibits the core to DDR cluster reset signal generated during the calibration modes. This prevents the DDR cluster synchronizer FIFO write pointer and data latches from being reset so that they can be read out of the cluster using the error monitor function. The reset signal can only be disabled in single step mode. When the DCALCSR.SGLSTP bit is set to 0, the DARWPR bit has no effect.'], 'range': (15, 15), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'OPMODS', 'description': ['Operation modifiers: See Table 16-224, Table 16-224, Table 16-227, and Table 16-235 for details'], 'range': (14, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'OPCODE', 'description': ['OPCODE:', '"0000" = NOP"0001" = Refresh (SeeTable 16-226) "0010" = Pre-Charge"0011" = MRS/EMRS', '"0100" = Self-Refresh-Exit (SeeTable 16-226) "0101" = Automatic DQS Delay Calibration"0110"= Reserved"0111" = DLL BIST', '"1100" = Automatic Receive Enable Calibration', '"1101" = Self-Refresh Entry (SeeTable 16-226) ', '"1110" = Error Monitor/Read DDRIO FIFO', '"1111" = ZQ Calibration', 'All other settings are reserved'], 'range': (3, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 64, 'offset_end': (67, None), 'offset_start': (64, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DCALCSR', 'reg_name': 'DCALCSR', 'size': 32, 'table_ref': '16-223', 'title_desc': 'DCAL Control and Status Register', 'view': 'PCI'}, 'DCALDATA[0-71]': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DCALData - DRAM Calibration Data Registers', 'fields': [{'access': 'RW', 'acronym': 'DCALDATA', 'description': ['DCAL Data and other information based on DCALCSR.OPCODE. See Table 16-232.'], 'range': (7, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 72, 'offset_end': (72, 1), 'offset_start': (72, 1), 'power_well': 'Core', 'recurring': 72, 'reg_base_name': 'DCALDATA', 'reg_name': 'DCALDATA[0-71]', 'size': 8, 'table_ref': '16-231', 'title_desc': 'DRAM Calibration Data Register', 'view': 'PCI'}, 'DDQSCADP0': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 2863398911L, 'description': 'DDQSCADP0: DQS Delay Cal Pattern', 'fields': [{'access': 'RW', 'acronym': 'AP0', 'description': ['Aggressor pattern 0'], 'range': (31, 0), 'reset': 2863398911L, 'sticky': ''}], 'offset': 220, 'offset_end': (223, None), 'offset_start': (220, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDQSCADP0', 'reg_name': 'DDQSCADP0', 'size': 32, 'table_ref': '16-250', 'title_desc': 'DQS Delay Calibration Aggressor Pattern 0 Register', 'view': 'PCI'}, 'DDQSCADP1': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 3677592801L, 'description': 'DDQSCADP1: DQS Delay Cal Pattern', 'fields': [{'access': 'RW', 'acronym': 'AP1', 'description': ['Aggressor pattern 1'], 'range': (31, 0), 'reset': 3677592801L, 'sticky': ''}], 'offset': 224, 'offset_end': (227, None), 'offset_start': (224, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDQSCADP1', 'reg_name': 'DDQSCADP1', 'size': 32, 'table_ref': '16-251', 'title_desc': 'DQS Delay Calibration Aggressor Pattern 1 Register', 'view': 'PCI'}, 'DDQSCVDP0': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 2863270405L, 'description': 'DDQSCVDP0: DQS Delay Cal Pattern', 'fields': [{'access': 'RW', 'acronym': 'VP0', 'description': ['Victim pattern 0'], 'range': (31, 0), 'reset': 2863270405L, 'sticky': ''}], 'offset': 212, 'offset_end': (215, None), 'offset_start': (212, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDQSCVDP0', 'reg_name': 'DDQSCVDP0', 'size': 32, 'table_ref': '16-248', 'title_desc': 'DQS Delay Calibration Victim Pattern 0 Register', 'view': 'PCI'}, 'DDQSCVDP1': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 1530109021, 'description': 'DDQSCVDP1: DQS Delay Cal Pattern', 'fields': [{'access': 'RW', 'acronym': 'VP1', 'description': ['Victim pattern 1'], 'range': (31, 0), 'reset': 1530109021, 'sticky': ''}], 'offset': 216, 'offset_end': (219, None), 'offset_start': (216, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDQSCVDP1', 'reg_name': 'DDQSCVDP1', 'size': 32, 'table_ref': '16-249', 'title_desc': 'DQS Delay Calibration Victim Pattern 1 Register', 'view': 'PCI'}, 'DDRIOMC0': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 120, 'description': None, 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 13), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQVOXADJ', 'description': ['Bits to configure DQ buffer tco balancing '], 'range': (12, 9), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DDRVOXCTL1', 'description': ['Combine this bit with DDRVOXCTL0 (defined below) Encodings:', '00 : DQ and CA buffers are in VOX Cross Reference Mode', '01: Bypass DQ and CA VOX Cross Reference Mode (default)', '10: VOX Bypass Mode', '11: Reset VOX Mode'], 'range': (8, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 7), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (6, 4), 'reset': 7, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DDRVOXCTL0', 'description': ['This is the least significant bit of DDRVOXCTL. For encoding details, see DDRVOXCTL1 above'], 'range': (3, 3), 'reset': 1, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (2, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 608, 'offset_end': (611, None), 'offset_start': (608, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDRIOMC0', 'reg_name': 'DDRIOMC0', 'size': 32, 'table_ref': '16-287', 'title_desc': 'DDRIO Mode Register Control Register', 'view': 'PCI'}, 'DDRIOMC1': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 1381105664, 'description': 'DDRIOMC1: DDRIO Mode Control Register 1', 'fields': [{'access': 'RW', 'acronym': 'CASLEW', 'description': ['CASLEW: The digital slew override 8-bit control allow for balancing of pull-up and pull-down slew rates T for CA/CLK buffers. The format of these controls and recommended reset value is given below:', 'BitsFunction', 'DDR2Selection.', '7DDR2 = 0', 'Fast Corner falling 6:5slew rate trim', 'Slow Corner falling 4:2slew rate trim', 'Fast corner rising 1:0slew rate trim'], 'range': (31, 24), 'reset': 82, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQSLEW', 'description': ['DQSLEW: The digital slew override 8-bit control allow for balancing of pull-up and pull-down slew rates T for CA/CLK buffers. The format of these controls and recommended reset value is given below:', 'BitsFunction', 'DDR2 Selection.', '7DDR2 = 0', 'Fast Corner falling 6:5slew rate trim', 'Slow Corner falling 4:2slew rate trim', 'Fast corner rising 1:0slew rate trim'], 'range': (23, 16), 'reset': 82, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 7), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DEMPDQ', 'description': ['De-emphasis mode select bit for DQ/DQS pins. This mode can be used to reduce power and enhance data eyes. When de-emphasis is enable for a given group of I/Os, subsequent driver values that are the same have their strength reduced by half ', 'It is recommended that this be controllable by the BIOS in case there are unwanted side effects of this feature. ', 'EncodingDescription', '00Disabled', '01Weakly Enabled', '10Full Enabled', 'OthersReserved'], 'range': (6, 5), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DEMPCA', 'description': ['De-emphasis mode select bit for command/clock pins. This mode can be used to reduce power and enhance data eyes. When de-emphasis is enable for a given group of I/Os, subsequent driver values that are the same have their strength reduced by half.', 'It is recommended that this be controllable by the BIOS in case there are unwanted side effects of this feature. For instance, de-emphasis should be off before entering self-refresh mode of the DRAM to prevent the CKE from exceeding the JEDEC threshold once self-refresh is entered.', 'EncodingDescription', '00Disabled', '01Weakly Enabled', '10Full Enabled', 'OthersReserved'], 'range': (4, 3), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (2, 2), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'FASTSLEW', 'description': ['bit[0] controls the control bits', 'bit[1] controls the data bits'], 'range': (1, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 612, 'offset_end': (615, None), 'offset_start': (612, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDRIOMC1', 'reg_name': 'DDRIOMC1', 'size': 32, 'table_ref': '16-288', 'title_desc': 'DDRIO Mode Register Control Register 1', 'view': 'PCI'}, 'DDRIOMC2': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 60710912, 'description': 'DDRIOMC2: DDRIO Mode Control Register 2', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'PHSEL', 'description': ['Core phase to Command/Address relationship. '], 'range': (27, 26), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'LEGOVERRIDE', 'description': ['Digital Impedance Control for RCOMP of DDR pads. See Legoverride table above.', 'Do not use the Default setting Please refer to Section 11.4.6, "RCOMP" for more details.'], 'range': (25, 16), 'reset': 926, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'FIFOWPTRCLR', 'description': ['This bit clears the DDRIO Receive FIFO read and write pointers. The write pointer of this FIFO is generated by the DDRIO logic based on DQS while the read pointer is generated by the memory controller.', 'The DDRIO receive FIPO read/write pointers need to be cleared after DCAL or Mbist operations are completed and before issuing any functional DRAM R/W operations.', 'Unlike SDRC.DDRRFRS this register will reset only the read/write pointers of the DDRIO receive FIFO. It will not reset the DLL\'s. Please see Section 16.1.1.45, "Offset 88h: SDRC - DDR SDRAM Secondary Control Register" for more details.'], 'range': (15, 15), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'MASTCNTL', 'description': ['Coarse delay of DQS Master DLL '], 'range': (14, 12), 'reset': 6, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (11, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 616, 'offset_end': (619, None), 'offset_start': (616, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DDRIOMC2', 'reg_name': 'DDRIOMC2', 'size': 32, 'table_ref': '16-291', 'title_desc': 'DDRIO Mode Control Register 2', 'view': 'PCI'}, 'DIOMON': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DIOMON: DDR I/O Monitor', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 25), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DSAMP', 'description': ['Causes the analog to digital converter to sample the analog input selected by biasssel '], 'range': (24, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'VRESULT', 'description': ['A/D converter output of DDR I/O '], 'range': (23, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'ENABLE', 'description': ['Enable A/D converter for the DDR IO Bias logic. Also enables updates to the following fields of this CSR: VRESULT, DQLEGSELOUT, DIOPWR, CALEGSELOUT'], 'range': (15, 15), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'BIASSEL', 'description': ['A/D converter input selection '], 'range': (14, 11), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'DQLEGSELOUT', 'description': ['DQ legsel output of DDR I/O. Sets the driver strength for DQ IO buffers. '], 'range': (10, 7), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'DIOPWR', 'description': ['Nopwr = 0 if Vccddr is off OR in burnin mode.', "During normal operation it's set to 1. "], 'range': (6, 6), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (5, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'CALEGSELOUT', 'description': ['cmd/addr legsel output of DDR I/O Sets the driver strength for cmd/addr IO buffers. '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 240, 'offset_end': (243, None), 'offset_start': (240, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DIOMON', 'reg_name': 'DIOMON', 'size': 32, 'table_ref': '16-252', 'title_desc': 'DDR I/O Monitor Register', 'view': 'PCI'}, 'DQSFAIL0': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSFAIL0: DQS Failure Configuration Register', 'fields': [{'access': 'RW', 'acronym': 'Reserved_R1DQS15', 'description': ['Reserved'], 'range': (31, 31), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS06', 'description': ['Rank 1 DQS06 '], 'range': (30, 30), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS14', 'description': ['Reserved'], 'range': (29, 29), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS05', 'description': ['Rank 1 DQS05 '], 'range': (28, 28), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS13', 'description': ['Reserved'], 'range': (27, 27), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS04', 'description': ['Rank 1 DQS04 '], 'range': (26, 26), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS12', 'description': ['Reserved'], 'range': (25, 25), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS03', 'description': ['Rank 1 DQS03 '], 'range': (24, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS11', 'description': ['Reserved'], 'range': (23, 23), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS02', 'description': ['Rank 1 DQS02 '], 'range': (22, 22), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS10', 'description': ['Reserved'], 'range': (21, 21), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS01', 'description': ['Rank 1 DQS01 '], 'range': (20, 20), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS09', 'description': ['Reserved'], 'range': (19, 19), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS00', 'description': ['Rank 1 DQS00 '], 'range': (18, 18), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS17', 'description': ['Reserved'], 'range': (17, 17), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS08', 'description': ['Rank 0 DQS08 '], 'range': (16, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS16', 'description': ['Reserved'], 'range': (15, 15), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS07', 'description': ['Rank 0 DQS07 '], 'range': (14, 14), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS15', 'description': ['Reserved'], 'range': (13, 13), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS06', 'description': ['Rank 0 DQS06 '], 'range': (12, 12), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS14', 'description': ['Reserved'], 'range': (11, 11), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS05', 'description': ['Rank 0 DQS05 '], 'range': (10, 10), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS13', 'description': ['Reserved'], 'range': (9, 9), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS04', 'description': ['Rank 0 DQS04 '], 'range': (8, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS12', 'description': ['Reserved'], 'range': (7, 7), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS03', 'description': ['Rank 0 DQS03 '], 'range': (6, 6), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS11', 'description': ['Reserved'], 'range': (5, 5), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS02', 'description': ['Rank 0 DQS02 '], 'range': (4, 4), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS10', 'description': ['Reserved'], 'range': (3, 3), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS01', 'description': ['Rank 0 DQS01 '], 'range': (2, 2), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R0DQS09', 'description': ['Reserved'], 'range': (1, 1), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R0DQS00', 'description': ['Rank 0 DQS00 '], 'range': (0, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 160, 'offset_end': (163, None), 'offset_start': (160, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSFAIL0', 'reg_name': 'DQSFAIL0', 'size': 32, 'table_ref': '16-236', 'title_desc': 'DQS Failure Configuration Register 0', 'view': 'PCI'}, 'DQSFAIL1': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSFAIL1: DQS Failure Configuration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS17', 'description': ['Reserved'], 'range': (3, 3), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS08', 'description': ['Rank 1 DQS08 '], 'range': (2, 2), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved_R1DQS16', 'description': ['Reserved'], 'range': (1, 1), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'R1DQS07', 'description': ['Rank 1 DQS07 '], 'range': (0, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 156, 'offset_end': (156, None), 'offset_start': (156, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSFAIL1', 'reg_name': 'DQSFAIL1', 'size': 8, 'table_ref': '16-235', 'title_desc': 'DQS Failure Configuration Register 1', 'view': 'PCI'}, 'DQSOFCS00': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSOFCS00: DQS Calibration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS03', 'description': ['Rank 0 DQS03: Fine delay '], 'range': (27, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 20), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS02', 'description': ['Rank 0 DQS02: Fine delay '], 'range': (19, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS01', 'description': ['Rank 0 DQS01: Fine delay '], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS00', 'description': ['Rank 0 DQS00: Fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 180, 'offset_end': (183, None), 'offset_start': (180, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSOFCS00', 'reg_name': 'DQSOFCS00', 'size': 32, 'table_ref': '16-240', 'title_desc': 'DQS Calibration Register', 'view': 'PCI'}, 'DQSOFCS01': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSOFCS01: DQS Calibration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS07', 'description': ['Rank 0 DQS07: Fine delay '], 'range': (27, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 20), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS06', 'description': ['Rank 0 DQS06: Fine delay '], 'range': (19, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS05', 'description': ['Rank 0 DQS05: Fine delay '], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS04', 'description': ['Rank 0 DQS04: Fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 184, 'offset_end': (187, None), 'offset_start': (184, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSOFCS01', 'reg_name': 'DQSOFCS01', 'size': 32, 'table_ref': '16-241', 'title_desc': 'DQS Calibration Register', 'view': 'PCI'}, 'DQSOFCS02': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSOFCS02: DQS Calibration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS08', 'description': ['Rank 0 DQS08: Fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 198, 'offset_end': (198, None), 'offset_start': (198, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSOFCS02', 'reg_name': 'DQSOFCS02', 'size': 8, 'table_ref': '16-242', 'title_desc': 'DQS Calibration Register', 'view': 'PCI'}, 'DQSOFCS10': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSOFCS10: DQS Calibration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS03', 'description': ['Rank 1 DQS03: Fine delay '], 'range': (27, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 20), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS02', 'description': ['Rank 1 DQS02: Fine delay '], 'range': (19, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS01', 'description': ['Rank 1 DQS01: Fine delay '], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS00', 'description': ['Rank 1 DQS00: Fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 188, 'offset_end': (191, None), 'offset_start': (188, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSOFCS10', 'reg_name': 'DQSOFCS10', 'size': 32, 'table_ref': '16-243', 'title_desc': 'DQS Calibration Register', 'view': 'PCI'}, 'DQSOFCS11': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSOFCS11: DQS Calibration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS07', 'description': ['Rank 1 DQS07: Fine delay '], 'range': (27, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 20), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS06', 'description': ['Rank 1 DQS06: Fine delay '], 'range': (19, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS05', 'description': ['Rank 1 DQS05: Fine delay '], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS04', 'description': ['Rank 1 DQS04: Fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 192, 'offset_end': (195, None), 'offset_start': (192, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSOFCS11', 'reg_name': 'DQSOFCS11', 'size': 32, 'table_ref': '16-244', 'title_desc': 'DQS Calibration Register', 'view': 'PCI'}, 'DQSOFCS12': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'DQSOFCS12: DQS Calibration Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DQS08', 'description': ['Rank 1 DQS08: Fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 199, 'offset_end': (199, None), 'offset_start': (199, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DQSOFCS12', 'reg_name': 'DQSOFCS12', 'size': 8, 'table_ref': '16-245', 'title_desc': 'DQS Calibration Register', 'view': 'PCI'}, 'DRAMDLLC': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 898752, 'description': 'DRAMDLLC: DDR I/O DLL Control', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 22), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'SLVBYP', 'description': ['DQS delay bypass '], 'range': (21, 21), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'SLVLEN4', 'description': ['dqs 8 coarse DQS delay '], 'range': (20, 18), 'reset': 3, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'SLVLEN3', 'description': ['dqs 7 & 6 coarse DQS delay '], 'range': (17, 15), 'reset': 3, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'SLVLEN2', 'description': ['dqs 5 & 4 coarse DQS delay '], 'range': (14, 12), 'reset': 3, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'SLVLEN1', 'description': ['dqs 3 & 2 coarse DQS delay '], 'range': (11, 9), 'reset': 3, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'SLVLEN0', 'description': ['dqs1 & 0 coarse DQS delay '], 'range': (8, 6), 'reset': 3, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (5, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 200, 'offset_end': (202, None), 'offset_start': (200, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DRAMDLLC', 'reg_name': 'DRAMDLLC', 'size': 24, 'table_ref': '16-254', 'title_desc': 'DDR I/O DLL Control Register', 'view': 'PCI'}, 'DRAMISCTL': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 4113, 'description': 'DRAMISCTL: Miscellaneous DRAM DDR Cluster Control Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 13), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (12, 12), 'reset': 1, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (11, 11), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'Reserved_RW', 'description': ['Reserved for future use. These bits are RW but SW should not change the default reset value of these bits.'], 'range': (10, 8), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'VREFSEL', 'description': ['Vref selection: Adjustable VREF voltage at receivers. The threshold voltage at receiver can be raised or lowered to allow the noise margin on the data from memory be skewed.', 'Vref is estimated with the following equation', 'Vref = (SQU * VCCDDR + (SQD - SQU) * 0.45) / (SQU + SQD) + VOFF', 'where,', 'SQU = SQRT(4*VREFSEL<7> + 2*VREFSEL<6> + VREFSEL<5> + 8*VREFSEL<4>)', 'SQD = SQRT(4*VREFSEL<3> + 2*VREFSEL<2> + VREFSEL<1> + 8*VREFSEL<0>)', 'VOFF = offset, varying for each chip, nominal value is 0 but can be up to +/- 0.1V', 'Examples with VCCDDR=1.8V and VOFF=0', '.VREFSEL. Vref (V) ', '00010001 0.9', '00010011 0.887', '00010101 0.875', '00011001 0.855', '11101001 0.840', '11001001 0.823', '10001001 0.779', '00110001 0.913', '01010001 0.925', '10010001 0.945', '10011110 0.960', '10011100 0.977', '10011000 1.021'], 'range': (7, 0), 'reset': 17, 'sticky': 'Y'}], 'offset': 248, 'offset_end': (251, None), 'offset_start': (248, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DRAMISCTL', 'reg_name': 'DRAMISCTL', 'size': 32, 'table_ref': '16-253', 'title_desc': 'Miscellaneous DRAM DDR Cluster Control Register', 'view': 'PCI'}, 'DRRTC00': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 101058054, 'description': 'DRRTC00: Receive Enable Reference Output Timing Control Register', 'fields': [{'access': 'RW', 'acronym': 'RCVEN03', 'description': ['Receiver enable delay for DQS3 '], 'range': (31, 24), 'reset': 6, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'RCVEN02', 'description': ['Receiver enable delay for DQS2 '], 'range': (23, 16), 'reset': 6, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'RCVEN01', 'description': ['Receiver enable delay for DQS1 '], 'range': (15, 8), 'reset': 6, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'RCVEN00', 'description': ['Receiver enable delay for DQS0 '], 'range': (7, 0), 'reset': 6, 'sticky': 'Y'}], 'offset': 164, 'offset_end': (167, None), 'offset_start': (164, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DRRTC00', 'reg_name': 'DRRTC00', 'size': 32, 'table_ref': '16-237', 'title_desc': 'Receive Enable Reference Output Timing Control Register', 'view': 'PCI'}, 'DRRTC01': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 101058054, 'description': 'DRRTC01: Receive Enable Reference Output Timing Control Register', 'fields': [{'access': 'RW', 'acronym': 'RCVEN07', 'description': ['Receiver enable delay for DQS7 '], 'range': (31, 24), 'reset': 6, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'RCVEN06', 'description': ['Receiver enable delay for DQS6 '], 'range': (23, 16), 'reset': 6, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'RCVEN05', 'description': ['Receiver enable delay for DQS5 '], 'range': (15, 8), 'reset': 6, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'RCVEN04', 'description': ['Receiver enable delay for DQS4 '], 'range': (7, 0), 'reset': 6, 'sticky': 'Y'}], 'offset': 168, 'offset_end': (171, None), 'offset_start': (168, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DRRTC01', 'reg_name': 'DRRTC01', 'size': 32, 'table_ref': '16-238', 'title_desc': 'Receive Enable Reference Output Timing Control Register', 'view': 'PCI'}, 'DRRTC02': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 6, 'description': 'DRRTC02: Receive Enable Reference Output Timing Control Register', 'fields': [{'access': 'RW', 'acronym': 'RCVEN08', 'description': ['Receiver enable delay for DQS8 '], 'range': (7, 0), 'reset': 6, 'sticky': 'Y'}], 'offset': 196, 'offset_end': (196, None), 'offset_start': (196, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DRRTC02', 'reg_name': 'DRRTC02', 'size': 8, 'table_ref': '16-239', 'title_desc': 'Receive Enable Reference Output Timing Control Register', 'view': 'PCI'}, 'DSRETC': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 1544819712, 'description': 'DSRETC: DRAM Self-Refresh (SR) Extended Timing and Control Register', 'fields': [{'access': 'RW', 'acronym': 'TXSNR', 'description': ['Exit self-refresh to non-read command timing. Number of Controller cycles for which accesses to the DIMMs need to be blocked by memory controller. '], 'range': (31, 24), 'reset': 92, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DRSRENT', 'description': ['Dual rank self-refresh (SR) entry and exit timing - stagger of self refresh commands between ranks. ', 'Staggering of the SR commands result is in the power intensive refresh operations to be staggered between the 2 ranks.'], 'range': (23, 16), 'reset': 20, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DRARTIM', 'description': ['Dual rank auto-refresh timing - stagger of commands between ranks prior to self-refresh entry. '], 'range': (15, 8), 'reset': 20, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 1), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'ENSREXIT', 'description': ['Enable Self-refresh (SR) exit state machine.', 'This bit needs to be set by BIOS upon power-up from an S3 event. '], 'range': (0, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 152, 'offset_end': (155, None), 'offset_start': (152, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'DSRETC', 'reg_name': 'DSRETC', 'size': 32, 'table_ref': '16-234', 'title_desc': 'DRAM Self-Refresh (SR) Extended Timing and Control Register', 'view': 'PCI'}, 'FIVESREG': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 1431655765, 'description': 'FIVESREG: Fixed 5s Pattern', 'fields': [{'access': 'RO', 'acronym': 'FIVES', 'description': ['Hardwired to 5s for read-return '], 'range': (31, 0), 'reset': 1431655765, 'sticky': 'N'}], 'offset': 232, 'offset_end': (235, None), 'offset_start': (232, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'FIVESREG', 'reg_name': 'FIVESREG', 'size': 32, 'table_ref': '16-255', 'title_desc': 'Fixed 5s Pattern Register', 'view': 'PCI'}, 'MBADDR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MBADDR: Memory Test Address', 'fields': [{'access': 'RW', 'acronym': 'ROW', 'description': ['Row Address 15:0 '], 'range': (31, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'SPARE', 'description': ["Reserved. Must write as '0' "], 'range': (15, 15), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'COL', 'description': ['Column Address BL8[14:3] <==> DRAM Column Address 15:11,9:3BL4[14:3] <==> DRAM Column Address 14:11,9:2'], 'range': (14, 3), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'BA', 'description': ['Bank Address 2:0 '], 'range': (2, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 324, 'offset_end': (327, None), 'offset_start': (324, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MBADDR', 'reg_name': 'MBADDR', 'size': 32, 'table_ref': '16-258', 'title_desc': 'Memory Test Address Register', 'view': 'PCI'}, 'MBCSR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MBCSR: Top level control register for DDR MemBIST.', 'fields': [{'access': 'RWS', 'acronym': 'START', 'description': ['Start operation:', '1 => Set this bit to begin MemBIST execution.', '0 => Hardware will clear this bit when MemBIST execution is completed.'], 'range': (31, 31), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'PF', 'description': ['Fail/Pass indicator:', 'Write to 0 when start MemBIST. Hardware will set to 1 when a failure is detected.', '0 => Pass', '1 => Fail'], 'range': (30, 30), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'HALT', 'description': ['Halt on Error:', '0 => Operation will not halt due to a detected error.', '1 => Operation will halt after read-compare data error is detected.', 'MemBIST will complete the current transaction before halting. This may result in multiple errors being logged.'], 'range': (29, 29), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'ABORT', 'description': ['MemBIST test abort. When test abort bit is set, MBCSR bit 31 (Start operation, RWS) needs to be set to "0" at the same time to avoid restarting MemBIST. ', '0 => Normal operation.', '1 => Need to abort the test during MemBIST operation.', 'If there is any following Membist test after the abort test, bit [28] needs to be cleared. ', 'The Write to set MBCSR.abort must occur at least tRFC after the Write to set MBCSR.start. Otherwise subsequent MemBIST operations may fail. '], 'range': (28, 28), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'SPARE', 'description': ['Reserved'], 'range': (27, 27), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'ALGO', 'description': ['000b: only support setting'], 'range': (26, 24), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 22), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'CS', 'description': ['Chip Select[1:0] selection in MemBIST mode', '01: select Rank 0', '10: select Rank 1', '00: Reserved', '11: Reserved'], 'range': (21, 20), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'INV', 'description': ['0b: only supported setting'], 'range': (19, 19), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'FX', 'description': ['FIXED: Fixed data pattern selection for MemBIST operation', '000 => 0', '001 => F', '010 => A', '011 => 5', '100 => C', '101 => 3', '110 => 9', '111 => 6'], 'range': (18, 16), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'EN288', 'description': ['0b: only supported setting'], 'range': (15, 15), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'MBDATA', 'description': ['MBDATA: Selects use of MBDATA for error log field for LFSR, Circular Shift and user defined data modes. This field has no effect on fixed data patterns.', '0 => use MBDATA0/1/2/3/8 for failure data bit location accumulator.', '1 => use MBDATA0/1/2/3/8 to log 5 failure addresses. '], 'range': (14, 14), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'ABAR', 'description': ['0: only supported setting'], 'range': (13, 13), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'ADIR', 'description': ['ADIR: Address decode direction ', '0 => Address increments', '1 => Address decrements'], 'range': (12, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'FAST', 'description': ['FAST Address sequencing', '00: only supported setting'], 'range': (11, 10), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'DTYPE', 'description': ['Data type selection:', '00 => Fixed data pattern, selected by MBCSR bits 18:16', '01 => 144 bits user defined data', '10 => Circular shift data based on Seed in MBLFSRSED ', '11 => LFSR data, seeded from 32 bit LFSR seed register.', 'Note: Circular shift data and LFSR data type should not be used for single address operation (ATYPE = 01).', 'Note: Circular shift data and LFSR data type only for 72-bit mode'], 'range': (9, 8), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'ATYPE', 'description': ['Address type:', '00 => Reserved', '01 => Single physical address operation, contained in MBADDR row/column/bank.', '10 => start/end physical address range defined in MB_START_ADDR & MB_END_ADDR registers. ', '11 => full address range of the DIMM as defined in DRA/DRB registers which specifies the number of banks, rows, and columns. ', '?'], 'range': (7, 6), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'CMD', 'description': ['Command execution:', '00 => Read only without data comparison', '01 => Write only ', '10 => Read with data comparison', '11 => Write followed by Read with data comparison'], 'range': (5, 4), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (3, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 320, 'offset_end': (323, None), 'offset_start': (320, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MBCSR', 'reg_name': 'MBCSR', 'size': 32, 'table_ref': '16-257', 'title_desc': 'MemBIST Control Register', 'view': 'PCI'}, 'MBDATA[0:9]': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MBADDR[0:9]: Memory Test Data', 'fields': [{'access': 'RW', 'acronym': 'MBDATA', 'description': ['Usage varies by mode, refer to table below for details '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 328, 'offset_end': (332, 4), 'offset_start': (328, 4), 'power_well': 'Core', 'recurring': 10, 'reg_base_name': 'MBDATA', 'reg_name': 'MBDATA[0:9]', 'size': 32, 'table_ref': '16-259', 'title_desc': 'Memory Test Data Register', 'view': 'PCI'}, 'MBFADDRPTR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MBFADDRPTR: Memory Test Failure Address Pointer Register', 'fields': [{'access': 'RW', 'acronym': 'MBFADDRPTR', 'description': ['This 32 bit register designates which MemBIST failures to log in the available failure address locations. ', 'The default value of this register is zero. It means MemBIST always logs beginning with the first failure. If it is programmed to hex A (10 in decimal), MemBIST will log failures starting from the11th failure. ', 'The corresponding MB_ERR_DATA0/1/2/3 registers will log corrupted data in the first through fourth designated failure addresses. ', 'Note: this register does not affect the MBDATA failure bit location accumulators. '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 424, 'offset_end': (427, None), 'offset_start': (424, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MBFADDRPTR', 'reg_name': 'MBFADDRPTR', 'size': 32, 'table_ref': '16-266', 'title_desc': 'Memory Test Failure Address Pointer Register', 'view': 'PCI'}, 'MBLFSRSED': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MBLFSRSED: Memory Test Circular Shift and LFSR Seed', 'fields': [{'access': 'RW', 'acronym': 'MBLFSRSED', 'description': ['MemBIST LFSR Seed ', 'This 32 bit register will be used as the initial data seed for LFSR or Circular shift data pattern.'], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 420, 'offset_end': (423, None), 'offset_start': (420, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MBLFSRSED', 'reg_name': 'MBLFSRSED', 'size': 32, 'table_ref': '16-265', 'title_desc': 'Memory Test Circular Shift and LFSR Seed Register', 'view': 'PCI'}, 'MB_END_ADDR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_END_ADDR: Memory Test End Address', 'fields': [{'access': 'RW', 'acronym': 'ROW', 'description': ['MemBIST End Row Address 15:0 '], 'range': (31, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'RESERVED', 'description': ['Reserved'], 'range': (15, 15), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'COL', 'description': ['MemBIST End Column Address ', 'BL8[14:3] <==> DRAM Column Address 15:11,9:3', 'BL4[14:3] <==> DRAM Column Address 14:11,9:2'], 'range': (14, 3), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'BA', 'description': ['MemBIST End Bank Address 2:0 '], 'range': (2, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 416, 'offset_end': (419, None), 'offset_start': (416, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_END_ADDR', 'reg_name': 'MB_END_ADDR', 'size': 32, 'table_ref': '16-264', 'title_desc': 'Memory Test End Address Register', 'view': 'PCI'}, 'MB_ERR_DATA00': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA00', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 432, 'offset_end': (435, None), 'offset_start': (432, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA00', 'reg_name': 'MB_ERR_DATA00', 'size': 32, 'table_ref': '16-267', 'title_desc': 'Memory Test Error Data 0', 'view': 'PCI'}, 'MB_ERR_DATA01': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA01', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 436, 'offset_end': (439, None), 'offset_start': (436, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA01', 'reg_name': 'MB_ERR_DATA01', 'size': 32, 'table_ref': '16-268', 'title_desc': 'Memory Test Error Data 0', 'view': 'PCI'}, 'MB_ERR_DATA02': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA02', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 440, 'offset_end': (443, None), 'offset_start': (440, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA02', 'reg_name': 'MB_ERR_DATA02', 'size': 32, 'table_ref': '16-269', 'title_desc': 'Memory Test Error Data 0', 'view': 'PCI'}, 'MB_ERR_DATA03': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA03', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 444, 'offset_end': (447, None), 'offset_start': (444, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA03', 'reg_name': 'MB_ERR_DATA03', 'size': 32, 'table_ref': '16-270', 'title_desc': 'Memory Test Error Data 0', 'view': 'PCI'}, 'MB_ERR_DATA04': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA04', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [71:64] & Early failure data [71:64] '], 'range': (15, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 448, 'offset_end': (449, None), 'offset_start': (448, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA04', 'reg_name': 'MB_ERR_DATA04', 'size': 16, 'table_ref': '16-271', 'title_desc': 'Memory Test Error Data 0', 'view': 'PCI'}, 'MB_ERR_DATA10': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA10', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 452, 'offset_end': (455, None), 'offset_start': (452, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA10', 'reg_name': 'MB_ERR_DATA10', 'size': 32, 'table_ref': '16-272', 'title_desc': 'Memory Test Error Data 1', 'view': 'PCI'}, 'MB_ERR_DATA11': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA11', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 456, 'offset_end': (459, None), 'offset_start': (456, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA11', 'reg_name': 'MB_ERR_DATA11', 'size': 32, 'table_ref': '16-273', 'title_desc': 'Memory Test Error Data 1', 'view': 'PCI'}, 'MB_ERR_DATA12': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA12', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 460, 'offset_end': (463, None), 'offset_start': (460, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA12', 'reg_name': 'MB_ERR_DATA12', 'size': 32, 'table_ref': '16-274', 'title_desc': 'Memory Test Error Data 1', 'view': 'PCI'}, 'MB_ERR_DATA13': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA13', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 464, 'offset_end': (467, None), 'offset_start': (464, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA13', 'reg_name': 'MB_ERR_DATA13', 'size': 32, 'table_ref': '16-275', 'title_desc': 'Memory Test Error Data 1', 'view': 'PCI'}, 'MB_ERR_DATA14': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA14', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [71:64] & Early failure data [71:64] '], 'range': (15, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 468, 'offset_end': (469, None), 'offset_start': (468, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA14', 'reg_name': 'MB_ERR_DATA14', 'size': 16, 'table_ref': '16-276', 'title_desc': 'Memory Test Error Data 1', 'view': 'PCI'}, 'MB_ERR_DATA20': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA20', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 472, 'offset_end': (475, None), 'offset_start': (472, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA20', 'reg_name': 'MB_ERR_DATA20', 'size': 32, 'table_ref': '16-277', 'title_desc': 'Memory Test Error Data 2', 'view': 'PCI'}, 'MB_ERR_DATA21': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA21', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 476, 'offset_end': (479, None), 'offset_start': (476, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA21', 'reg_name': 'MB_ERR_DATA21', 'size': 32, 'table_ref': '16-278', 'title_desc': 'Memory Test Error Data 2', 'view': 'PCI'}, 'MB_ERR_DATA22': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA22', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 480, 'offset_end': (483, None), 'offset_start': (480, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA22', 'reg_name': 'MB_ERR_DATA22', 'size': 32, 'table_ref': '16-279', 'title_desc': 'Memory Test Error Data 2', 'view': 'PCI'}, 'MB_ERR_DATA23': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA23', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 484, 'offset_end': (487, None), 'offset_start': (484, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA23', 'reg_name': 'MB_ERR_DATA23', 'size': 32, 'table_ref': '16-280', 'title_desc': 'Memory Test Error Data 2', 'view': 'PCI'}, 'MB_ERR_DATA24': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA24', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [71:64] & Early failure data [71:64] '], 'range': (15, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 488, 'offset_end': (489, None), 'offset_start': (488, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA24', 'reg_name': 'MB_ERR_DATA24', 'size': 16, 'table_ref': '16-281', 'title_desc': 'Memory Test Error Data 2', 'view': 'PCI'}, 'MB_ERR_DATA30': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA30', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 492, 'offset_end': (495, None), 'offset_start': (492, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA30', 'reg_name': 'MB_ERR_DATA30', 'size': 32, 'table_ref': '16-282', 'title_desc': 'Memory Test Error Data 3', 'view': 'PCI'}, 'MB_ERR_DATA31': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA31', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Early failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 496, 'offset_end': (500, None), 'offset_start': (496, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA31', 'reg_name': 'MB_ERR_DATA31', 'size': 32, 'table_ref': '16-283', 'title_desc': 'Memory Test Error Data 3', 'view': 'PCI'}, 'MB_ERR_DATA32': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA32', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [31:0] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 500, 'offset_end': (503, None), 'offset_start': (500, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA32', 'reg_name': 'MB_ERR_DATA32', 'size': 32, 'table_ref': '16-284', 'title_desc': 'Memory Test Error Data 3', 'view': 'PCI'}, 'MB_ERR_DATA33': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA33', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [63:32] '], 'range': (31, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 504, 'offset_end': (507, None), 'offset_start': (504, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA33', 'reg_name': 'MB_ERR_DATA33', 'size': 32, 'table_ref': '16-285', 'title_desc': 'Memory Test Error Data 3', 'view': 'PCI'}, 'MB_ERR_DATA34': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_ERR_DATA34', 'fields': [{'access': 'RW', 'acronym': 'DATA', 'description': ['Late failure data [71:64] & Early failure data [71:64] '], 'range': (15, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 508, 'offset_end': (509, None), 'offset_start': (508, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_ERR_DATA34', 'reg_name': 'MB_ERR_DATA34', 'size': 16, 'table_ref': '16-286', 'title_desc': 'Memory Test Error Data 3', 'view': 'PCI'}, 'MB_START_ADDR': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'MB_START_ADDR: Memory Test Start Address', 'fields': [{'access': 'RW', 'acronym': 'ROW', 'description': ['MemBIST Start Row Address 15:0 '], 'range': (31, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'RESERVED', 'description': ['Reserved'], 'range': (15, 15), 'reset': 0, 'sticky': ''}, {'access': 'RW', 'acronym': 'COL', 'description': ['MemBIST Start Column Address ', 'BL8[14:3] <==> DRAM Column Address 15:11,9:3', 'BL4[14:3] <==> DRAM Column Address 14:11,9:2'], 'range': (14, 3), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'BA', 'description': ['MemBIST Start Bank Address 2:0 '], 'range': (2, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 412, 'offset_end': (415, None), 'offset_start': (412, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'MB_START_ADDR', 'reg_name': 'MB_START_ADDR', 'size': 32, 'table_ref': '16-263', 'title_desc': 'Memory Test Start Address Register', 'view': 'PCI'}, 'NOTEPAD': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': None, 'fields': [{'access': 'RW', 'acronym': 'BNSR', 'description': ['BIOS Register: This register is used by BIOS.'], 'range': (15, 0), 'reset': 0, 'sticky': 'N'}], 'offset': 2, 'offset_end': (3, None), 'offset_start': (2, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'NOTEPAD', 'reg_name': 'NOTEPAD', 'size': 16, 'table_ref': '16-222', 'title_desc': 'Note Pad for BIOS Support Register', 'view': 'PCI'}, 'NOTESPAD': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': None, 'fields': [{'access': 'RW', 'acronym': 'BSR', 'description': ['BIOS Sticky Register [STICKY]: This register is used by BIOS. It is sticky through reset.'], 'range': (15, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 0, 'offset_end': (1, None), 'offset_start': (0, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'NOTESPAD', 'reg_name': 'NOTESPAD', 'size': 16, 'table_ref': '16-221', 'title_desc': 'Note (Sticky) Pad for BIOS Support Register', 'view': 'PCI'}, 'RCVENAC': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 1574928, 'description': 'RCVENAC: Receiver Enable Algorithm Control', 'fields': [{'access': 'RW', 'acronym': 'PWIDTH', 'description': ['Minimum preamble width limit, used to detect if a low pulse in a DQS waveform is wide enough to be a valid preamble. The default corresponds to 3/4 of a DRAM clock cycle '], 'range': (23, 16), 'reset': 24, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 14), 'reset': 0, 'sticky': ''}, {'access': 'RW', 'acronym': 'HWIDTH', 'description': ['Minimum high pulse width limit, used to detect if a high pulse in a DQS waveform is wide enough to indicate a strobe is toggling in a valid manner. The default corresponds to 1/4 of a DRAM clock cycle. '], 'range': (13, 8), 'reset': 8, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 6), 'reset': 0, 'sticky': ''}, {'access': 'RW', 'acronym': 'POFFSET', 'description': ['Preamble center offset from first rising edge, used to position the DQS receiver enable relative to the preamble edge location recorded in the DCALDATA registers. The default value corresponds to 1/2 of a DRAM clock cycle. '], 'range': (5, 0), 'reset': 16, 'sticky': 'Y'}], 'offset': 148, 'offset_end': (150, None), 'offset_start': (148, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'RCVENAC', 'reg_name': 'RCVENAC', 'size': 24, 'table_ref': '16-233', 'title_desc': 'Receiver Enable Algorithm Control Register', 'view': 'PCI'}, 'WDLL_MISC': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'WDLL_MISC- DLL Miscellaneous Control', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 25), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'WLCKDLY', 'description': ['0: delay ECC/DQS[8]/DQS_L[8] only, clocks not delayed', '1: delay ECC/DQS[8]/DQS_L[8] and CK[2:0]/CK_L[2:0] (Normal setting for DDR2)'], 'range': (24, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (23, 23), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'WL_PHSEL_MODE', 'description': ['See Table 16-294 for DQ/DQS', 'Connectivity:', '[22] CS, ODT, CKE', '[21] CK[5:3], CK_L[5:3]', '[20] WL_CNTL[0] (DQ[15:0], DQS/DQS_L[1:0])', '[19] WL_CNTL[1] (DQ[31:16], DQS/DQS_L[3:2])', '[18] WL_CNTL[4] (ECC[7:0], DQS/DQS_L[8],CK[2:0], CK_L[2:0])', '[17] WL_CNTL[2] (DQ[47:32], DQS/DQS_L[5:4])', '[16] WL_CNTL[3] (DQ[63:48], DQS/DQS_L[7:6])'], 'range': (22, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'WL_CNTRL', 'description': ['Delay select for CK[5:3] and CK_L[5:3]:', '0xxx: no delay', '1001: delay 1/4 clk1x', '1000: delay 1/2 clk1x', '1011: delay 3/4 clk1x', '1100: delay 1 clk1x', 'OthersReserved'], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'WL_CNTRL_A', 'description': ['Delay select for CS, ODT and CKE', '0xxx: no delay', '1001: delay 1/4 clk1x', '1000: delay 1/2 clk1x', '1011: delay 3/4 clk1x', '1100: delay 1 clk1x', 'OthersReserved'], 'range': (7, 4), 'reset': 0, 'sticky': 'Y'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (3, 3), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'WL_CMD_DLY', 'description': ['Reserved to Intel', 'Encoded additional delay for CS, CKE, ODT', 'Delay introduced = (~100ps * WL_CMD_DLY)'], 'range': (2, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 664, 'offset_end': (667, None), 'offset_start': (664, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'WDLL_MISC', 'reg_name': 'WDLL_MISC', 'size': 32, 'table_ref': '16-295', 'title_desc': 'DLL Miscellaneous Control', 'view': 'PCI'}, 'WL_CNTL[4:0]': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'WL_CNTL[4:0]: Write Levelization Control Register', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (31, 16), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (15, 14), 'reset': 0, 'sticky': 'N'}, {'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (13, 12), 'reset': 0, 'sticky': 'N'}, {'access': 'RW', 'acronym': 'WL_CNTRL', 'description': ['Delay Select', 'See Table 16-294'], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'WDLL_CNTL', 'description': ['Length controls for Slave Write DLL (WDLL). A delay of 0 up to 3/8 of clk1x can be programmed using this CSR.'], 'range': (7, 2), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'WDLL_CLKG', 'description': ['Control bit for Clock gating of DQ/DQS.', '0- Disable clock gating for DQ/DQS', '1- Enable clock gating for DQ/DQS', 'Note: for WL_CNTL[4], WDLL_CLKG must be equal to 0'], 'range': (1, 1), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'BYP_WDLL', 'description': ['Bypass Write DLL. This bit is used only for centering DQS to the DQ eye. For write leveling, see Table 16-294.', '0 - Bypass DLL', '1 - Output with WDLL', 'Before enabling/setting this bit to 1, software needs to first program the appropriate values in DRAMDLLC.SLVLEN & WL_CNTL[x].WDLL_CNTL.'], 'range': (0, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 644, 'offset_end': (660, 4), 'offset_start': (644, 4), 'power_well': 'Core', 'recurring': 5, 'reg_base_name': 'WL_CNTL', 'reg_name': 'WL_CNTL[4:0]', 'size': 32, 'table_ref': '16-293', 'title_desc': 'Write Levelization Control Register', 'view': 'PCI'}, 'WPTRTC0': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'WPTRTC0: Write pointer timing control', 'fields': [{'access': 'RW', 'acronym': 'DQS07', 'description': ['DQS7 write pointer fine delay '], 'range': (31, 28), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS06', 'description': ['DQS6 write pointer fine delay '], 'range': (27, 24), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS05', 'description': ['DQS5 write pointer fine delay '], 'range': (23, 20), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS04', 'description': ['DQS4 write pointer fine delay'], 'range': (19, 16), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS03', 'description': ['DQS3 write pointer fine delay '], 'range': (15, 12), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS02', 'description': ['DQS2 write pointer fine delay '], 'range': (11, 8), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS01', 'description': ['DQS1 write pointer fine delay '], 'range': (7, 4), 'reset': 0, 'sticky': 'Y'}, {'access': 'RW', 'acronym': 'DQS00', 'description': ['DQS0 write pointer fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 204, 'offset_end': (207, None), 'offset_start': (204, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'WPTRTC0', 'reg_name': 'WPTRTC0', 'size': 32, 'table_ref': '16-246', 'title_desc': 'Write Pointer Timing Control Register', 'view': 'PCI'}, 'WPTRTC1': {'bar': 'SMRBASE', 'bus_device_function': '0:0:0', 'default': 0, 'description': 'WPTRTC1: Write pointer timing control', 'fields': [{'access': 'RO', 'acronym': 'Reserved', 'description': ['Reserved'], 'range': (7, 4), 'reset': 0, 'sticky': ''}, {'access': 'RW', 'acronym': 'DQS08', 'description': ['DQS8 write pointer fine delay '], 'range': (3, 0), 'reset': 0, 'sticky': 'Y'}], 'offset': 208, 'offset_end': (208, None), 'offset_start': (208, None), 'power_well': 'Core', 'recurring': None, 'reg_base_name': 'WPTRTC1', 'reg_name': 'WPTRTC1', 'size': 8, 'table_ref': '16-247', 'title_desc': 'Write Pointer Timing Control 1 Register', 'view': 'PCI'}}