0 = VLAN Mode Disabled.1 = VLAN Mode Enabled. All packets transmitted have an 802.1q header added to the packet. The contents of the header come from the transmit descriptor and from the VLAN type register. On receive, VLAN information is stripped from 802.1q packets. See "802.1q VLAN Support" on page 1400 for more details.

0 = Transmit Flow Control Disabled.1 = Transmit Flow Control Enabled. Flow control packets (XON & XOFF frames) will be transmitted based on receiver fullness. If Auto-Negotiation is enabled, this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more information about Auto-Negotiation.

0 = Receive Flow Control Disabled.1 = Receive Flow Control Enabled. Indicates the device will respond to the reception of flow control packets. Reception of flow control packets requires the correct loading of the FCAH/FCAL & FCT registers. If Auto-Negotiation is enabled, this bit is set to the negotiated duplex value. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more information about Auto-Negotiation.

Device Reset, also referred to as a "Soft Reset". Normally 0, writing 1 initiates the reset. This bit is self clearing.

CTRL.RST may be used to globally reset the entire GbE hardware. This register is provided primarily as a last-ditch software mechanism to recover from an indeterminate or suspected hung hardware state. Most registers (receive, transmit, interrupt, statistics, etc.), and state machines will be set to their power-on reset values, approximating the state following a power-on or Unit Reset. However, the Packet Buffer Allocation Register (PBA) retains its value through a global reset.Note:Software must first disable both transmit & receive operation using the TCTL.EN and RCTL.EN register bits before asserting CTRL.RST. To ensure that the global device reset has fully completed and that the controller will respond to subsequent accesses, software must wait a minimum of 5 milliseconds after setting CTRL.RST before attempting to check if the bit has cleared or to access any other GbE device register.

When set, D3Cold wakeup capability may be advertised based on whether the AUX_PWR pin advertises presence of auxiliary power (see section 2.13.3 for details). When 0, D3Cold wakeup capability will not be advertised even if AUX_PWR presence is indicated. Formerly used as SDP2 pin data value, initial value is EEPROM-configurable

0 = Mode is Full-Duplex, regardless of the FD setting.1 =CTRL.FD bit sets duplex mode.

0 = Default of 1Gbps is used to set the MAC speed. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for more details.1 =CTRL.SPEED bits set the MAC speed.Note:This bit is superseded by the CTRL_EXT.SPD_BYPS bit which has a similar function.Note:*Note that this bit is loaded from the EEPROM, if present

These bits are written by software (assuming, after reading the PHY registers through the MDIO interface) to set the MAC speed configuration. See "Physical Layer Auto-Negotiation & Link Setup Features" on page 1394 for details.

? 11 => reservedNote:These bits affect the MAC speed setting only if CTRL_EXT.SPD_BYPS or CTRL.FRCSPD are used.

SLU must be set to '1' to enable the MAC. This bit may also be initialized by the APME bit in the EEPROM Initialization Control Word3, if an EEPROM is used.

In half-duplex mode, EP80579's GbE transmits carrier extended packets and can receive both carrier extended packets, and packets transmitted with bursting.

In GMII/MII mode, these bits reflect the software CTRL.SPEED setting 

Transmission Off. This bit indicates the state of the transmit function when symmetrical flow control has been enabled and negotiated with the link partner.

0 = Symmetrical flow control is disabled, or transmission is not paused.1 = Symmetrical flow control is enabled, and the transmit function is paused due to the reception of an XOFF frame. It is cleared upon expiration of the pause timer or the receipt of an XON frame.

Full Duplex. This bit reflects the MAC duplex configuration. Normally, the duplex setting for the link, as it should reflect the duplex configuration negotiated between the PHY and link partner (copper link) or MAC and link partner (fiber link).

0 = For proper 100mbps receive operation, after assertion of the RMII CRS_DV signal on GBEn_RXCTL, the RMII gasket requires that a minimum of two di-bits of '00' appear on GBEn_RXDATA[1:0] before the preamble appears.1 = For proper 100mbps receive operation, the RMII gasket requires that CRS_DV be asserted on GBEn_RXCTL synchronously with GBE_REFCLK_RMII and on the same cycle in which the first di-bit of the preamble appears on GBEn_RXDATA[1:0].

0 is the default value of this bit and makes the RMII gasket compatible with RMII PHYs that assert CRS_DV as soon as the receive medium is non-idle, and subsequently drive '00' on RXD[1:0] until proper receive signal decoding has been achieved (per the RMII Specification, Revision 1.2).

Setting this bit to a 1 makes the gasket compatible with RMII PHYs that assert CRS_DV simultaneously with the start of the preamble driven on RXD[1:0]. While this CRS_DV signalling mode does not scrictly conform to the RMII specification, it is provided to allow compatibility with PHY devices that use this alternate method of asserting CRS_DV at the start of the packet.

This bit must be set to the proper state that corresponds to the CRS_DV behavior of the attached RMII PHY, otherwise 100mbps packets cannot be properly received by the GbE.

Link Mode. This controls which interface is used to talk to the link.

0 = Normal speed detection mechanisms are used to determine the speed of the MAC.1 = All speed detection mechanisms are bypassed and the MAC is immediately set to the setting of CTRL.SPEED.Note:CTRL_EXT.SPD_BYPS performs a function similar to CTRL.FRCSPD in that the device's speed settings are determined by the value software writes to the CTRL.SPEED bits. However, when using CTRL_EXT.SPD_BYPS the CTRL.SPEED setting takes effect immediately, when using CTRL.FRCSPD the CTRL.SPEED setting waits until after the device's clock switching circuitry performs the change.

Initiates a "reset-like" event to the EEPROM function. This causes the EEPROM to be read as if a UNIT_RESET had occurred. All device functions should be disabled prior to setting this bit. This bit is self-clearing.

To enable this mode of operation, set this bit to a '1'. When enabled, the fix modifies the legacy new-packet signalling logic in the transmit path to prevent the first 8 bytes of packet data from being dropped when operating in RMII mode and a line speed of 100mbps.

Disable DMA frequency change to fix RMII 100mbps TX dropped packet data.

To disable this mode of operation, set this bit to a '1'. This must be disabled if FIX2 is enabled.

When enabled, sets the DMA clock frequency to 50MHz when operating in RMII mode. This produces a favorable frequency ratio between DMA and MAC clocks that prevents the first 8 bytes of transmit packet data from being dropped when operating in RMII mode and a line speed of 100mbps.

Selects whether the descriptor or packet data is controlled by endianness configuration.

These bits control the endianness of the data in memory. These settings apply to all internal bus transactions, including packet data and descriptors

If an EEPROM is present, this bit indicates its size, based on acknowledges seen during EEPROM scans of different addresses. 

NOTE: this bit will not be updated as a result of anything but a power up reset.

This bit attempts to indicate if an EEPROM is present by monitoring the EE_DO input for a active-low "acknowledge" by the serial EEPROM during initial EEPROM scan. If no EEPROM is present, the EE_DO line will remain pulled-high and thus no acknowledge will be seen. 

NOTE: this bit will not be set except as a result of EEPROM detection during power up reset.

When this bit is 1 the software can access the EEPROM using the SK, CS, DI, and DO bits.

The software must write a 1 to this bit to get direct EEPROM access. It has access when EE_GNT is 1. When the software completes the access it must write a 0.

The EE_DO input signal is mapped directly to this bit in the register and contains the EEPROM data output. This bit is read-only from the software perspective - writes to this bit have no effect.

When EE_GNT is 1, the EE_DI output signal is mapped directly to this bit. Software provides data input to the EEPROM via writes to this bit.

When EE_GNT is 1, the EE_CS output signal is mapped to the chip select of the EEPROM device. Software enables the EEPROM by writing a 1 to this bit.

When EE_GNT is 1, the EE_SK output signal is mapped to this bit and provides the serial clock input to the EEPROM. Software clocks the EEPROM via toggling this bit with successive writes.

This field is written by software along with Start Read to indicate the word to read.

Writing a 1 to this bit causes the EEPROM to read a (16-bit) word at the address stored in the EE_ADDR field, storing the result in the EE_DATA field. This bit is self-clearing

To be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00

To be compliant with the 802.3ac standard, this register must be programmed with the value 0x00_00_81_00.

Transmit Packet Buffer Allocation in K bytes. PBA.TXA is read only and calculated based on PBA.RXA.

Receive Packet Buffer Allocation in K bytes. PBA.RXA legal values must be 8K aligned.

This bit indicates that an error occurred during either a Target or Host transaction on the bus. Refer to Section 37.5.12, "Error Handling" for complete details.

The details of this error are reported in the INTBUS_ERR_STAT register.

Statistic Register ECC Error. The Statistic Registers are implemented using a memory that uses a single-bit correct/multi-bit detect ECC parity algorithm to protect it. This bit indicates that a multi-bit error has occurred on a read from that memory. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)

This bit indicates that either a Multicast Filter Parity Error, Special Packet Filter Parity Error or a Flex Filter Parity Error occurred. These filters use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT register.

DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)

DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)

DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST)

Indicates that a packet of size   RSRPD.SIZE register has been detected and transferred to host memory. The interrupt is only asserted if RSRPD.SIZE register has a non-zero value

Transmit Descriptor Low Threshold hit. Indicates that the descriptor ring has reached the threshold specified in "TXDCTL - Transmit Descriptor Control Register" on page 1500.

Receiver Timer Interrupt. Set when the timers expire, see "Receive Interrupts" on page 1360 for details.

Receiver Overrun. Set on receive data FIFO overrun. Could be caused either because there are no available buffers or because Internal Bus receive bandwidth is inadequate.

Receive Descriptor Minimum Threshold Hit. Indicates that the minimum number of receive descriptors are available and software should load more receive descriptors.

Transmit Queue Empty. Set when the last descriptor block for a transmit queue has been used.

Transmit Descriptor Written Back. Set when hardware processes a descriptor with its RS bit set. If using delayed interrupts (TDESC.IDE is set in the Transmit Descriptor CMD), the interrupt is delayed until after one of the delayed-timers (TIDV or TADV) expires.

? In RGMII mode, the interval is specified in 256ns increments. 

To independently validate configuration settings, software can use the following formula to convert the inter-interrupt interval value to the common 'interrupts/sec' performance metric:-9-interrupts/sec = (256 x 10 sec x inter-interrupt interval)1

Inversely, inter-interrupt interval value can be calculated as:-9-inter-interrupt interval = (256 x 10 sec x interrupts/sec)1

For example, if the interval is programmed to 500d, the network controller guarantees the CPU will not be interrupted by the network controller for 128 usec from the last interrupt. The maximum observable interrupt rate from the adapter should never exceed 7813 interrupts/sec.

The optimal performance setting for this register is system/configuration specific. A initial suggested range is 651-5580 (28Bh - 15CCh), or, more generally, between 700 and 6000 interrupts per second.

Sets the mask for Receiver Overrun. Set on receive data FIFO overrun

Clears the mask for Small Receive Packet Detected and Transferred

Clears the mask for Receiver Overrun. Set on receive data FIFO overrun

Multicast Filter Parity Error/Special Packet Filter Parity Error. The Multicast Filter and Special Packets Filter use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. This error is considered non-fatal and will clear after a read of the MEM_ERR_STAT register.

DMA Packet Buffer 2-bit ECC Error. The 64KB DMA Packet Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for data. This bit indicates that a multi-bit error has occurred on a read from that SRAM. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).

DMA Transmit Descriptor 2-bit ECC Error. The DMA Transmit Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).

DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware. Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).

Multicast Filter Parity Error/Special Packet Filter Parity Error. The Multicast Filter and Special Packets Filter use parity protected SRAMs for data buffers. This bit indicates that a parity error has occurred on a read from either of these data buffers. 

DMA Receive Descriptor 2-bit ECC Error. The DMA Receive Descriptor Buffer uses a single-bit correct/multi-bit detect ECC parity algorithm to protect the SRAM it uses for a data buffer. This bit indicates that a multi-bit error has occurred on a read from that data buffer. No indication of a single-bit error correction will be given by hardware.Note:If this interrupt asserts, further GbE DMA Reads and Writes are blocked until software issues a soft reset to the GbE by writing the Device Control Register (CTRL.RST).

Strip Ethernet CRC. This bit controls whether the hardware strips the Ethernet CRC from the received packet. This stripping occurs prior to any checksum calculations. The stripped CRC is not DMA'd to host memory and is not included in the length reported in the descriptor.

Buffer Size Extension. Combined with RCTL.BSIZE to program the receive buffer size. Control of receive buffer size permits software to trade-off descriptor performance versus required storage space. Buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes.

Pass MAC Control Frames. This bit controls the DMA function of MAC control frames (other than flow control). A MAC control frame in this context must be addressed to either the MAC control frame multicast address or the station address, it must match the type field and must NOT match the PAUSE opcode of 0x0001.

0 = Do not pass MAC control frames1 = Pass any MAC control frame (type field value of 0x8808) that does not contain the pause opcode of 0x0001.

Discard Pause Frames. This bit controls the DMA function of flow control packets addressed to the station address (RAH/RAL[0]). If a packet is a valid flow control packet and is addressed to the station address it will not be DMA'd to host memory if RCTL.DPF=1.

0 = Incoming frames are subject to filter comparison1 = Incoming valid PAUSE frames discarded even if they match any of the filter registers

Canonical Form Indicator. One of the three bits that control the VLAN filter table. This bit may be compared to the CFI bit found in the 802.1q packet as part of the acceptance criteria. RCTL.CFIEN and RCTL.VFE determine whether or not this comparison takes place.

Canonical Form Indicator Enable. One of the three bits that control the VLAN filter table. This bit enables using the CFI bit found in the 802.1q packet as part of the acceptance criteria.

The next two are used to decide whether the CFI bit found in the.1Q packet should be used as part of the acceptance criteria.

0 = CFI Disabled: bit not compared to determine packet acceptance1 = CFI from packet must match CFI field for acceptance of 802.1q packet

VLAN Filter Enable. One of the three bits that control the VLAN filter table. This bit determines whether the table participates in the packet acceptance criteria.

0 = Disabled, filter table does not decide packet acceptance1 = Enabled, filter table decides acceptance of 802.1q packets

Receive Buffer Size. Combined with RCTL.BSEX to program the receive buffer size. Control of receive buffer size permits software to trade-off descriptor performance versus required storage space. Buffers that are 2048 bytes require only one descriptor per receive packet maximizing descriptor efficiency. Buffers that are 256 bytes maximize memory efficiency at a cost of multiple descriptors for packets longer than 256 bytes.

0 = Ignore broadcast (unless it matches exact or imperfect filters)1 = Accept broadcast packets

Multicast Offset. This determines which bits of the incoming multicast address are used in looking up the bit vector.

Receive Descriptor Minimum Threshold Size. These bits determines the threshold value for free receive descriptors. The corresponding interrupt is set whenever the fractional number of free descriptors becomes equal to RCTL.RDMTS. Refer to "RDLEN - Receive Descriptor Length Register" on page 1481 for further information.

Loopback mode. These bits enable the loopback function.When using a PHY, a value of 00 should be used and the PHY is configured for loopback through the MDIO interface.

? 11 = ReservedNote:PHY devices require programming for loopback operation using MDIO accesses.Note:The GbE must be configured for Full-Duplex operation if Mac Loopback mode is enabled.

Long packet enable. This bit controls whether long packet reception is permitted.

0 = Disabled, hardware discards packets longer than 1522B1 = Enabled, 16384B is the maximum packet size that the GbE can receive

0 = All incoming packets are immediately dropped and are not stored in the receive FIFO. If a packet is already in-progress when disabled it will be finished.1 = Incoming packet reception is enabled.

When set, enables the Ethernet controller to transmit XON packets based on receive FIFO crosses FCRTL.RTL threshold value, or based on external pins XOFF and XON. See Section 37.6.4.3, "FCRTH - Flow Control Receive Threshold High Register" on page 1479

Receive Threshold Low. FIFO low water mark for flow control transmission.

Allows the Ethernet controller to send XOFF and XON frames based on external pins XOFF and XON. The transmission of pause frames must be also enabled through the CTRL.TFCE control bit. When the XOFF signal is asserted high, the Ethernet controller transmits a single XOFF frame. The assertion of XON (after deassertion of XOFF) initiates an XON frame transmission, if enabled by FCRTL.XONE. The assertion/deassertion of XON is required between assertions of XOFF in order to send another XOFF frame.

Note:The EP80579 does not have external XON/XOFF pins and therefore does not support external flow control enable. This bit must be set to 0 for correct operation.

Receive Threshold High. FIFO high water mark for flow control transmission.

Receive Descriptor Base Address.Note:RDBAH[31:0] must be set to 0.

Flush Partial Descriptor. Writing this bit with 1 initiates an immediate expiration of the timer, causing a writeback of any consumed receive descriptors pending writeback, and results in a receive timer interrupt in the ICR register. This bit is self clearing and always reads 0.

0 = Threshold values are in units of Cache Lines, thresholds specified must not be greater than 31 descriptors (496B) or 15 32B cache lines.1 = Threshold values are in units of Descriptors (16B each)

Write-back Threshold. This field controls the write-back of processed receive descriptors. This threshold refers to the number of receive descriptors in the GbE hardware buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back will occur only after more than WTHRESH descriptors are available for write-back.Note:Since the default value for this field is 1, the descriptors are normally written back as soon as one cache line is available. This field must contain a non-zero value to take advantage of the write-back bursting capabilities of the EP80579's GbE.

Host Threshold. This field is used to control the fetching of descriptors from host memory. This threshold refers to the number of valid, unprocessed receive descriptors that must exist in host memory before they will be fetched.

Prefetch Threshold. This field is used to control when a prefetch of descriptors will be considered. This threshold refers to the number of valid, unprocessed receive descriptors the chip has in its GbE hardware buffer. If this number drops below PTHRESH, the algorithm will consider pre-fetching descriptors from host memory. This fetch will not happen however unless there are at least HTHRESH valid descriptors in host memory to fetch.

If the packet delay timer is used to coalesce receive interrupts, the Ethernet controller ensures that when receive traffic abates, an interrupt is generated within a specified interval of no receives. During times when receive traffic is continuous, it may be necessary to ensure that no receive remains unnoticed for too long an interval. This register can be used to ENSURE that a receive interrupt occurs at some predefined interval after the first packet is received. When this timer is enabled, a separate absolute countdown timer is initiated upon successfully receiving each packet to system memory. When this absolute timer expires, pending receive descriptor writebacks are flushed and a receive timer interrupt is generated. 

Setting this register to 0b disables the absolute timer mechanism (the RDTR register should be used with a value of 0b to cause immediate interrupts for all receive packets).

Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending RADV interrupt. If enabled, the RADV countdown timer is reloaded but halted, so as to avoid generation of a spurious second interrupt after the RDTR has been noted.

Any packet received that is <= SIZE will assert an interrupt condition (ICR.SRPD). This field is specified in bytes and includes the headers and the CRC but not the VLAN header in the size calculation.

TCP/UDP Checksum Off load Enable. This bit is used to enable the TCP/UDP Checksum off-loading feature.

0 = TCP/UDP Checksum Off load Disabled1 = Hardware will calculate the TCP or UDP checksum and indicate a pass/fail indication to software via the TCP/UDP Checksum Error bit (TCPE).

IP Checksum Off load Enable. This bit is used to enable the IP Checksum off-loading feature.

0 = IP Checksum Off load Disabled1 = Hardware will calculate the IP checksum and indicate a pass/fail indication to software via the IP Checksum Error bit (IPE) in the ERROR field of the receive descriptor.

Packet Checksum Start. This field controls the starting byte for the Packet Checksum calculation. The Packet Checksum is the one's complement over the receive packet, starting from the byte indicated by PCSS (0 corresponds to the first byte of the packet), after stripping.

For example, for an Ethernet II frame encapsulated as an 802.3ac VLAN packet and with PCSS set to 14, the packet checksum would include the entire encapsulated frame, excluding the 14-byte Ethernet header (DA, SA, Type and Length) and the 4-byte VLAN tag. The Packet Checksum will not include the Ethernet CRC if the RCTL.SECRC bit is set. Software must make the required offsetting computation (to back out the bytes that should not have been included and to include the pseudo-header) prior to comparing the Packet Checksum against the TCP checksum stored in the packet. 

Receive Address Low. The lower 32 bits of the 48 bit Ethernet address.

Address valid. This bit determines whether this address is compared against the incoming packet. Cleared after software reset or Unit Reset.

Address Select. Selects how the address is to be used when performing special filtering on receive packets.

Receive Address High. The upper 16 bits of the 48 bit Ethernet address.

Re-Transmit on Late Collision. This bit configures the hardware to perform retransmission of packets when a late collision is detected. Note that the collision window is speed dependent: 64B for 10/100 Mbps and 512B for 1Gbps operation. If a late collision is detected when this bit is clear, the transmit function assumes the packet is successfully transmitted.Note:This bit is ignored in full-duplex mode.

Packet Burst Enable. The EP80579's GbE does not support Packet Bursting for 1Gbps half-duplex transmit operation. This bit must be set to 0.

Software XOFF Transmission. When set to a 1 the device will schedule the transmission of an XOFF (PAUSE) frame using the current value of the PAUSE timer. This bit clears itself upon transmission of the XOFF frame.Note:While 802.3x flow control is only defined during full duplex operation, the sending of PAUSE frames via the SWXOFF bit is not gated by the duplex settings within the device. Software should not write a 1 to this bit while the device is configured for half duplex operation.

Collision Distance. Wire speeds of 1Gbps result in a very short collision radius with traditional minimum packet sizes. This bit specifies the minimum number of bytes in the packet to satisfy the desired collision distance for proper CSMA/CD operation. It is important to note that the resulting packet has special characters appended to the end, not regular data characters. Hardware strips special characters for packets that go from 1 Gbps environments to 100 Mbps environments.Note:The hardware checks and pads to this value even in full-duplex operation.

Collision Threshold. Software may choose to abort packet transmission in less than the Ethernet mandated 16 collisions. This field determines the number of attempts at retransmission prior to giving up on the packet (not including the first transmission attempt). The Ethernet back-off algorithm is implemented and clamps to the maximum number of slot-times after 10 retries. This field only has meaning when in half-duplex operation.Note:While this field can be varied, it should be set to a value of 15 in order to comply with the IEEE specification requiring a total of 16 attempts.

Pad Short Packets to 64B with valid data characters, NOT padding symbols.

0 = Do not pad short packets1 = Pad short packetsNote:This is not the same as the mini-mum collision distance.

0 = Writing this bit to 0 will stop transmission after any in progress packets are sent. Data remains in the transmit FIFO until the device is re-enabled. Software should combine this with reset if the packets in the FIFO should be flushed.1 = The transmitter is enabled.

Specifies the total length of the IPG time for non back-to-back transmissions. Measured in increments of the MAC clock: 

In order to calculate the actual IPG value, a value of six should be added to the IPGR2 value as six MAC clocks are used by the MAC for synchronization and internal engines. 

For the IEEE 802.3 standard IPG value of 96-bit time, the value that should be programmed into IPGR2 is six (total IPG delay of 12 MAC clock cycles) 

According to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value.IPGR2 is significant only in half-duplex mode of operation. 

Specifies the length of the first part of the IPG time for non back-to- back transmissions. During this time, the internal IPG counter restarts if any carrier event occurs. Once the time specified in IPGR1 has elapsed, carrier sense does not affect the IPG counter. According to the IEEE802.3 standard, IPGR1 should be 2/3 of IPGR2 value. Measured in increments of the MAC clock:

For IEEE 802.3 minimum IPG value of 96-bit time, the value that should be programmed into IPGR1 is eight. IPGR1 is significant only in half-duplex mode of operation. 

To calculate the IPG value for 10/100/1000BASE-T applications, a value of four should be added to the IPGT value as four clocks are used by the MAC as internal overhead. The value that should be programmed into IPGT is 8. These values are recommended to assure that the minimum IPG gap is met under all synchronization conditions. 

Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and delays their transfer to the CSMA/CD transmit function. Normally, this register should be set to 0b. However, if additional delay is desired between back-to-back transmit packets, then this register can be set with a value greater than zero (0). This feature can be helpful in high collision half-duplex environments.

In order for AIFS to take effect it should be larger than the minimum IFS value defined in IEEE 802.3 standard. AIFS has no effect on transmissions that occur immediately after receives or transmissions that are not back-to-back. In addition, it has no effect on re-transmission timing (retransmission after collisions).

Transmit Descriptor Base AddressNote:TDBAH[31:0] must be set to 0.

? This register is used to delay interrupt notification for transmit operations by coalescing interrupts for multiple transmitted buffers. Delaying interrupt notification helps maximize the amount of transmit buffers reclaimed by a single interrupt. This feature only applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set).

? This feature operates by initiating a countdown timer upon successfully transmitting the buffer. If a subsequent transmit delayed-interrupt is scheduled before the timer expires, the timer is re-initialized to the programmed value and re-starts its countdown. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated.

? Hardware always loads the transmit interrupt counter whenever it processes a descriptor with IDE set even if it is already counting down due to a previous descriptor.

? Setting the value to 0 is not allowed. If an immediate (non-scheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0.

? The occurrence of either an immediate (non-scheduled) or absolute transmit timer interrupt will halt the TIDV timer and eliminate any spurious second interrupts.

? Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or an immediate interrupt (RS =1, IDE=0) will cancel a pending TIDV interrupt. The TIDV countdown timer is reloaded but halted, though it may be restarted by a processing a subsequent transmit descriptor.

Transmit Descriptor Low Threshold. This field controls the number of pre-fetched transmit descriptors at which a transmit descriptor-low interrupt is reported. Asserting ICR.TXD_LOW only when the processing distance from the TDT register drops below LWTHRESH may allow software to operate more efficiently by maintaining a continuous addition of transmit work, interrupting only when the hardware nears completion of all submitted work.

An interrupt condition is asserted when the number of descriptors available transitions from

where LWTHRESH specifies a multiple of 8 descriptors, (i.e. threshold_level = 8*LWTHRESH).

Setting this value to 0 will cause this interrupt to be generated only when the transmit descriptor cache becomes completely empty.

Write-back Threshold. This field controls the write-back of processed transmit descriptors. This threshold refers to the number of transmit descriptors in the GbE hardware buffer which are ready to be written back to host memory. In the absence of external events (explicit flushes), the write-back will occur only after more than WTHRESH descriptors are available for write-back.

Since write-back notification of transmit descriptor completion is optional (under the control of the RS bit in the descriptor), not all processed descriptors are counted with respect to WTHRESH (any single transmit descriptor with RS=0 is consumed with no writeback notification performed). When WTHRESH is non-zero, processing a descriptor with RS=1 initiates accumulation of pending writebacks; accumulated writebacks will include even those descriptors with RS=0, in order to optimize writeback bursts.Note:When WTHRESH value is set to 0, transmit descriptor writeback notification will be similar to the 82452 behavior. In accordance with WTHRESH=0, the writeback notification for a descriptor with RS=1 will occur as soon as the descriptor is processed. In addition, processed transmit descriptors are not written-back in entirety; only the descriptor status field is written back/ updated. This 82542-compatible mode is the default HW behavior.

Prefetch Threshold. This field is used to control when a prefetch of descriptors will be considered. This threshold refers to the number of valid, unprocessed transmit descriptors the chip has in its GbE hardware buffer. If this number drops below PTHRESH, the algorithm will consider pre-fetching descriptors from host memory. This fetch will not happen however unless there are at least HTHRESH valid descriptors in host memory to fetch.

The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts. However, it might be necessary to ensure that no completed transmit remains unnoticed for too long an interval in order ensure timely release of transmit buffers. This register can be used to ENSURE that a transmit interrupt occurs at some predefined interval after a transmit is completed. Like the delayed-transmit timer, the absolute transmit timer ONLY applies to transmit descriptor operations where (a) interrupt-based reporting is requested (RS set) and (b) the use of the timer function is requested (IDE is set).

This feature operates by initiating a countdown timer upon successfully transmitting the buffer. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated. The occurrence of either an immediate (non-scheduled) or delayed transmit timer (TIDV) expiration interrupt halts the TADV timer and eliminates any spurious second interrupts.

Setting the value to 0b disables the transmit absolute delay function. If an immediate (nonscheduled) interrupt is desired for any transmit descriptor, the descriptor IDE should be set to 0b.Note:This timer ONLY causes an interrupt. It does NOT cause a writeback

TCP Segmentation Packet Buffer Padding, value is in bytes. This field allows software configuration of packet buffer space which must be reserved as "pad" for worst-case header insertion. To ensure that this value does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (maximum TCP HDRLEN + maximum MSS + TSPMT.TMPBP + 80 bytes).

TCP Segmentation Minimum Transfer, value is in bytes. The DMA will attempt to issue burst fetches for as much data as possible, and it is possible for the transmit DMA to cause the transmit packet buffer to approach fullness (less the pad specified). However, if the packet buffer empties slightly, the transmit DMA could initiate a series of small transfers.

To further optimize the efficiency of the transmit DMA during TCP segmentation operation, the this TSPMT.TSMT field allows software configuration of the minimum number of bytes which the DMA should attempt to transfer in a single burst operation. The transmit DMA will use this value to refrain from issuing a burst read until at least TSPMT.TSMT bytes of data from the current data descriptor can be stored in the packet buffer.

This check will be ignored if, after a series of DMA operations, the descriptor contains a smaller number of unfetched data bytes. To ensure that this minimum threshold does not prevent descriptors from being serviced at all, it is necessary that the transmit packet buffer allocation should be larger than the sum of (TSPMT.TSMT + TSPMT.TSPBP + 80 bytes).

Number of times a successful transmit encountered multiple collisions.

Number of packets transmitted that are 1024 or more bytes in length

Number of TCP Segmentation contexts where the device failed to transmit the entire data payload

If it is 1, the GbE will set the PME_Status bit in the Power Management Control / Status Register (PMCSR) and assert GBE_PME_WAKE when APM Wakeup is enabled and the GbE receives a matching magic packet.

This bit is set when the GbE receives a wakeup event. It is the same as the PME_Status bit in the Power Management Control / Status Register (PMCSR). Writing a "1" to this bit will clear it and clear the PME_Status bit in the PMCSR.

This read/write bit is used by the driver to access the PME_En bit of the Power Management Control / Status Register (PMCSR) without writing to PCI configuration space.

The packet was a multicast packet whose hashed to a value that corresponded to a 1 bit in the Multicast Table ArrayNote:If the MAC has been configured for promiscuous mode, a multicast wakeup will occur if a broadcast packet is received. This is because a broadcast message is a special type of multicast message. Refer to 802.3.

The packet's address matched one of the 16 pre-programmed exact values in the Receive Address registers

The initial value is loaded from the IP Address Valid bit of the EEPROM's Management Control Register

0 - Internal Bus errors will halt further GbE transmit/receive operation.

? 01 = Pull data error detected during a target write transaction

? 10 = GbE received a Internal Bus Data Error response while mastering a DMA transaction

? 11 = Master Pull data error occurred as a result of an internal memory error

Indicates whether one or more than one Internal Bus errors have occurred before INTBUS_ERR_STAT.CERR was cleared

Internal Bus Error: Asserts when Internal Bus Error status and address registers are valid

0 = no error has been logged1 = Internal Bus Error status and address registers have logged an error

If error handling is enabled (INTBUS_ERR_H_DIS = 0) then this bit can only be cleared by a reset.

The Valid Mask bits are selected according to the Select field, as follows:

Indicates, for the following error types, whether GbE Tx/Rx operation will be halted:

0: Memory Errors will halt further GbE Tx/Rx operation and a soft-reset is required to restore operation

1: Memory Errors will be logged, but will not halt further GbE Tx/Rx operation

When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC.

When MEM_ERRH_DIS is clear then this bit is RO. When MEM_ERRH_DIS is set then this bit is RWC