From 8fb6b0908176704a3ea22005e8a9fa3ebf35b5be Mon Sep 17 00:00:00 2001 From: Jeff Kirsher Date: Mon, 16 May 2011 01:39:01 -0700 Subject: bmac/mace/macmace/mac89x0/cs89x0: Move the Macintosh (Apple) drivers Move the Apple drivers into driver/net/ethernet/apple/ and make the necessary Kconfig and Makefile changes. CC: Paul Mackerras CC: Paul Mackerras CC: Russell Nelson Signed-off-by: Jeff Kirsher --- drivers/net/Kconfig | 75 -- drivers/net/Makefile | 6 - drivers/net/bmac.c | 1685 ------------------------------ drivers/net/bmac.h | 164 --- drivers/net/cs89x0.c | 1913 ---------------------------------- drivers/net/cs89x0.h | 465 --------- drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/apple/Kconfig | 96 ++ drivers/net/ethernet/apple/Makefile | 9 + drivers/net/ethernet/apple/bmac.c | 1685 ++++++++++++++++++++++++++++++ drivers/net/ethernet/apple/bmac.h | 164 +++ drivers/net/ethernet/apple/cs89x0.c | 1913 ++++++++++++++++++++++++++++++++++ drivers/net/ethernet/apple/cs89x0.h | 465 +++++++++ drivers/net/ethernet/apple/mac89x0.c | 634 +++++++++++ drivers/net/ethernet/apple/mace.c | 1031 ++++++++++++++++++ drivers/net/ethernet/apple/mace.h | 173 +++ drivers/net/ethernet/apple/macmace.c | 799 ++++++++++++++ drivers/net/mac89x0.c | 634 ----------- drivers/net/mace.c | 1031 ------------------ drivers/net/mace.h | 173 --- drivers/net/macmace.c | 799 -------------- 22 files changed, 6971 insertions(+), 6945 deletions(-) delete mode 100644 drivers/net/bmac.c delete mode 100644 drivers/net/bmac.h delete mode 100644 drivers/net/cs89x0.c delete mode 100644 drivers/net/cs89x0.h create mode 100644 drivers/net/ethernet/apple/Kconfig create mode 100644 drivers/net/ethernet/apple/Makefile create mode 100644 drivers/net/ethernet/apple/bmac.c create mode 100644 drivers/net/ethernet/apple/bmac.h create mode 100644 drivers/net/ethernet/apple/cs89x0.c create mode 100644 drivers/net/ethernet/apple/cs89x0.h create mode 100644 drivers/net/ethernet/apple/mac89x0.c create mode 100644 drivers/net/ethernet/apple/mace.c create mode 100644 drivers/net/ethernet/apple/mace.h create mode 100644 drivers/net/ethernet/apple/macmace.c delete mode 100644 drivers/net/mac89x0.c delete mode 100644 drivers/net/mace.c delete mode 100644 drivers/net/mace.h delete mode 100644 drivers/net/macmace.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a7ec50f197f..d81f8f95012 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -237,52 +237,6 @@ config MACB source "drivers/net/arm/Kconfig" -config MACE - tristate "MACE (Power Mac ethernet) support" - depends on PPC_PMAC && PPC32 - select CRC32 - help - Power Macintoshes and clones with Ethernet built-in on the - motherboard will usually use a MACE (Medium Access Control for - Ethernet) interface. Say Y to include support for the MACE chip. - - To compile this driver as a module, choose M here: the module - will be called mace. - -config MACE_AAUI_PORT - bool "Use AAUI port instead of TP by default" - depends on MACE - help - Some Apple machines (notably the Apple Network Server) which use the - MACE ethernet chip have an Apple AUI port (small 15-pin connector), - instead of an 8-pin RJ45 connector for twisted-pair ethernet. Say - Y here if you have such a machine. If unsure, say N. - The driver will default to AAUI on ANS anyway, and if you use it as - a module, you can provide the port_aaui=0|1 to force the driver. - -config BMAC - tristate "BMAC (G3 ethernet) support" - depends on PPC_PMAC && PPC32 - select CRC32 - help - Say Y for support of BMAC Ethernet interfaces. These are used on G3 - computers. - - To compile this driver as a module, choose M here: the module - will be called bmac. - -config MAC89x0 - tristate "Macintosh CS89x0 based ethernet cards" - depends on MAC - ---help--- - Support for CS89x0 chipset based Ethernet cards. If you have a - Nubus or LC-PDS network (Ethernet) card of this type, say Y and - read the Ethernet-HOWTO, available from - . - - To compile this driver as a module, choose M here. This module will - be called mac89x0. - config MACSONIC tristate "Macintosh SONIC based ethernet (onboard, NuBus, LC, CS)" depends on MAC @@ -296,16 +250,6 @@ config MACSONIC To compile this driver as a module, choose M here. This module will be called macsonic. -config MACMACE - bool "Macintosh (AV) onboard MACE ethernet" - depends on MAC - select CRC32 - help - Support for the onboard AMD 79C940 MACE Ethernet controller used in - the 660AV and 840AV Macintosh. If you have one of these Macintoshes - say Y and read the Ethernet-HOWTO, available from - . - config KORINA tristate "Korina (IDT RC32434) Ethernet support" depends on NET_ETHERNET && MIKROTIK_RB532 @@ -677,25 +621,6 @@ config FORCEDETH To compile this driver as a module, choose M here. The module will be called forcedeth. -config CS89x0 - tristate "CS89x0 support" - depends on NET_ETHERNET && (ISA || EISA || MACH_IXDP2351 \ - || ARCH_IXDP2X01 || MACH_MX31ADS || MACH_QQ2440) - ---help--- - Support for CS89x0 chipset based Ethernet cards. If you have a - network (Ethernet) card of this type, say Y and read the - Ethernet-HOWTO, available from - as well as - . - - To compile this driver as a module, choose M here. The module - will be called cs89x0. - -config CS89x0_NONISA_IRQ - def_bool y - depends on CS89x0 != n - depends on MACH_IXDP2351 || ARCH_IXDP2X01 || MACH_MX31ADS || MACH_QQ2440 - config TC35815 tristate "TOSHIBA TC35815 Ethernet support" depends on NET_PCI && PCI && MIPS diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b54e308fc19..79f93f08c49 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -38,9 +38,6 @@ obj-$(CONFIG_PLIP) += plip.o obj-$(CONFIG_ROADRUNNER) += rrunner.o -obj-$(CONFIG_MACE) += mace.o -obj-$(CONFIG_BMAC) += bmac.o - obj-$(CONFIG_TLAN) += tlan.o obj-$(CONFIG_SIS190) += sis190.o obj-$(CONFIG_SIS900) += sis900.o @@ -133,10 +130,7 @@ obj-$(CONFIG_KORINA) += korina.o obj-$(CONFIG_MIPS_JAZZ_SONIC) += jazzsonic.o obj-$(CONFIG_MIPS_SIM_NET) += mipsnet.o obj-$(CONFIG_SGI_IOC3_ETH) += ioc3-eth.o -obj-$(CONFIG_CS89x0) += cs89x0.o obj-$(CONFIG_MACSONIC) += macsonic.o -obj-$(CONFIG_MACMACE) += macmace.o -obj-$(CONFIG_MAC89x0) += mac89x0.o obj-$(CONFIG_TUN) += tun.o obj-$(CONFIG_VETH) += veth.o obj-$(CONFIG_NET_NETX) += netx-eth.o diff --git a/drivers/net/bmac.c b/drivers/net/bmac.c deleted file mode 100644 index 45e45e8d3d6..00000000000 --- a/drivers/net/bmac.c +++ /dev/null @@ -1,1685 +0,0 @@ -/* - * Network device driver for the BMAC ethernet controller on - * Apple Powermacs. Assumes it's under a DBDMA controller. - * - * Copyright (C) 1998 Randy Gobbel. - * - * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to - * dynamic procfs inode. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bmac.h" - -#define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1)))) -#define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1))) - -/* - * CRC polynomial - used in working out multicast filter bits. - */ -#define ENET_CRCPOLY 0x04c11db7 - -/* switch to use multicast code lifted from sunhme driver */ -#define SUNHME_MULTICAST - -#define N_RX_RING 64 -#define N_TX_RING 32 -#define MAX_TX_ACTIVE 1 -#define ETHERCRC 4 -#define ETHERMINPACKET 64 -#define ETHERMTU 1500 -#define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2) -#define TX_TIMEOUT HZ /* 1 second */ - -/* Bits in transmit DMA status */ -#define TX_DMA_ERR 0x80 - -#define XXDEBUG(args) - -struct bmac_data { - /* volatile struct bmac *bmac; */ - struct sk_buff_head *queue; - volatile struct dbdma_regs __iomem *tx_dma; - int tx_dma_intr; - volatile struct dbdma_regs __iomem *rx_dma; - int rx_dma_intr; - volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ - volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ - struct macio_dev *mdev; - int is_bmac_plus; - struct sk_buff *rx_bufs[N_RX_RING]; - int rx_fill; - int rx_empty; - struct sk_buff *tx_bufs[N_TX_RING]; - int tx_fill; - int tx_empty; - unsigned char tx_fullup; - struct timer_list tx_timeout; - int timeout_active; - int sleeping; - int opened; - unsigned short hash_use_count[64]; - unsigned short hash_table_mask[4]; - spinlock_t lock; -}; - -#if 0 /* Move that to ethtool */ - -typedef struct bmac_reg_entry { - char *name; - unsigned short reg_offset; -} bmac_reg_entry_t; - -#define N_REG_ENTRIES 31 - -static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = { - {"MEMADD", MEMADD}, - {"MEMDATAHI", MEMDATAHI}, - {"MEMDATALO", MEMDATALO}, - {"TXPNTR", TXPNTR}, - {"RXPNTR", RXPNTR}, - {"IPG1", IPG1}, - {"IPG2", IPG2}, - {"ALIMIT", ALIMIT}, - {"SLOT", SLOT}, - {"PALEN", PALEN}, - {"PAPAT", PAPAT}, - {"TXSFD", TXSFD}, - {"JAM", JAM}, - {"TXCFG", TXCFG}, - {"TXMAX", TXMAX}, - {"TXMIN", TXMIN}, - {"PAREG", PAREG}, - {"DCNT", DCNT}, - {"NCCNT", NCCNT}, - {"NTCNT", NTCNT}, - {"EXCNT", EXCNT}, - {"LTCNT", LTCNT}, - {"TXSM", TXSM}, - {"RXCFG", RXCFG}, - {"RXMAX", RXMAX}, - {"RXMIN", RXMIN}, - {"FRCNT", FRCNT}, - {"AECNT", AECNT}, - {"FECNT", FECNT}, - {"RXSM", RXSM}, - {"RXCV", RXCV} -}; - -#endif - -static unsigned char *bmac_emergency_rxbuf; - -/* - * Number of bytes of private data per BMAC: allow enough for - * the rx and tx dma commands plus a branch dma command each, - * and another 16 bytes to allow us to align the dma command - * buffers on a 16 byte boundary. - */ -#define PRIV_BYTES (sizeof(struct bmac_data) \ - + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \ - + sizeof(struct sk_buff_head)) - -static int bmac_open(struct net_device *dev); -static int bmac_close(struct net_device *dev); -static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev); -static void bmac_set_multicast(struct net_device *dev); -static void bmac_reset_and_enable(struct net_device *dev); -static void bmac_start_chip(struct net_device *dev); -static void bmac_init_chip(struct net_device *dev); -static void bmac_init_registers(struct net_device *dev); -static void bmac_enable_and_reset_chip(struct net_device *dev); -static int bmac_set_address(struct net_device *dev, void *addr); -static irqreturn_t bmac_misc_intr(int irq, void *dev_id); -static irqreturn_t bmac_txdma_intr(int irq, void *dev_id); -static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id); -static void bmac_set_timeout(struct net_device *dev); -static void bmac_tx_timeout(unsigned long data); -static int bmac_output(struct sk_buff *skb, struct net_device *dev); -static void bmac_start(struct net_device *dev); - -#define DBDMA_SET(x) ( ((x) | (x) << 16) ) -#define DBDMA_CLEAR(x) ( (x) << 16) - -static inline void -dbdma_st32(volatile __u32 __iomem *a, unsigned long x) -{ - __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); -} - -static inline unsigned long -dbdma_ld32(volatile __u32 __iomem *a) -{ - __u32 swap; - __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a)); - return swap; -} - -static void -dbdma_continue(volatile struct dbdma_regs __iomem *dmap) -{ - dbdma_st32(&dmap->control, - DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD)); - eieio(); -} - -static void -dbdma_reset(volatile struct dbdma_regs __iomem *dmap) -{ - dbdma_st32(&dmap->control, - DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)); - eieio(); - while (dbdma_ld32(&dmap->status) & RUN) - eieio(); -} - -static void -dbdma_setcmd(volatile struct dbdma_cmd *cp, - unsigned short cmd, unsigned count, unsigned long addr, - unsigned long cmd_dep) -{ - out_le16(&cp->command, cmd); - out_le16(&cp->req_count, count); - out_le32(&cp->phy_addr, addr); - out_le32(&cp->cmd_dep, cmd_dep); - out_le16(&cp->xfer_status, 0); - out_le16(&cp->res_count, 0); -} - -static inline -void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data ) -{ - out_le16((void __iomem *)dev->base_addr + reg_offset, data); -} - - -static inline -unsigned short bmread(struct net_device *dev, unsigned long reg_offset ) -{ - return in_le16((void __iomem *)dev->base_addr + reg_offset); -} - -static void -bmac_enable_and_reset_chip(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - volatile struct dbdma_regs __iomem *td = bp->tx_dma; - - if (rd) - dbdma_reset(rd); - if (td) - dbdma_reset(td); - - pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1); -} - -#define MIFDELAY udelay(10) - -static unsigned int -bmac_mif_readbits(struct net_device *dev, int nb) -{ - unsigned int val = 0; - - while (--nb >= 0) { - bmwrite(dev, MIFCSR, 0); - MIFDELAY; - if (bmread(dev, MIFCSR) & 8) - val |= 1 << nb; - bmwrite(dev, MIFCSR, 1); - MIFDELAY; - } - bmwrite(dev, MIFCSR, 0); - MIFDELAY; - bmwrite(dev, MIFCSR, 1); - MIFDELAY; - return val; -} - -static void -bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb) -{ - int b; - - while (--nb >= 0) { - b = (val & (1 << nb))? 6: 4; - bmwrite(dev, MIFCSR, b); - MIFDELAY; - bmwrite(dev, MIFCSR, b|1); - MIFDELAY; - } -} - -static unsigned int -bmac_mif_read(struct net_device *dev, unsigned int addr) -{ - unsigned int val; - - bmwrite(dev, MIFCSR, 4); - MIFDELAY; - bmac_mif_writebits(dev, ~0U, 32); - bmac_mif_writebits(dev, 6, 4); - bmac_mif_writebits(dev, addr, 10); - bmwrite(dev, MIFCSR, 2); - MIFDELAY; - bmwrite(dev, MIFCSR, 1); - MIFDELAY; - val = bmac_mif_readbits(dev, 17); - bmwrite(dev, MIFCSR, 4); - MIFDELAY; - return val; -} - -static void -bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val) -{ - bmwrite(dev, MIFCSR, 4); - MIFDELAY; - bmac_mif_writebits(dev, ~0U, 32); - bmac_mif_writebits(dev, 5, 4); - bmac_mif_writebits(dev, addr, 10); - bmac_mif_writebits(dev, 2, 2); - bmac_mif_writebits(dev, val, 16); - bmac_mif_writebits(dev, 3, 2); -} - -static void -bmac_init_registers(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - volatile unsigned short regValue; - unsigned short *pWord16; - int i; - - /* XXDEBUG(("bmac: enter init_registers\n")); */ - - bmwrite(dev, RXRST, RxResetValue); - bmwrite(dev, TXRST, TxResetBit); - - i = 100; - do { - --i; - udelay(10000); - regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */ - } while ((regValue & TxResetBit) && i > 0); - - if (!bp->is_bmac_plus) { - regValue = bmread(dev, XCVRIF); - regValue |= ClkBit | SerialMode | COLActiveLow; - bmwrite(dev, XCVRIF, regValue); - udelay(10000); - } - - bmwrite(dev, RSEED, (unsigned short)0x1968); - - regValue = bmread(dev, XIFC); - regValue |= TxOutputEnable; - bmwrite(dev, XIFC, regValue); - - bmread(dev, PAREG); - - /* set collision counters to 0 */ - bmwrite(dev, NCCNT, 0); - bmwrite(dev, NTCNT, 0); - bmwrite(dev, EXCNT, 0); - bmwrite(dev, LTCNT, 0); - - /* set rx counters to 0 */ - bmwrite(dev, FRCNT, 0); - bmwrite(dev, LECNT, 0); - bmwrite(dev, AECNT, 0); - bmwrite(dev, FECNT, 0); - bmwrite(dev, RXCV, 0); - - /* set tx fifo information */ - bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */ - - bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */ - bmwrite(dev, TXFIFOCSR, TxFIFOEnable ); - - /* set rx fifo information */ - bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */ - bmwrite(dev, RXFIFOCSR, RxFIFOEnable ); - - //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */ - bmread(dev, STATUS); /* read it just to clear it */ - - /* zero out the chip Hash Filter registers */ - for (i=0; i<4; i++) bp->hash_table_mask[i] = 0; - bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */ - bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */ - bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */ - bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */ - - pWord16 = (unsigned short *)dev->dev_addr; - bmwrite(dev, MADD0, *pWord16++); - bmwrite(dev, MADD1, *pWord16++); - bmwrite(dev, MADD2, *pWord16); - - bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets); - - bmwrite(dev, INTDISABLE, EnableNormal); -} - -#if 0 -static void -bmac_disable_interrupts(struct net_device *dev) -{ - bmwrite(dev, INTDISABLE, DisableAll); -} - -static void -bmac_enable_interrupts(struct net_device *dev) -{ - bmwrite(dev, INTDISABLE, EnableNormal); -} -#endif - - -static void -bmac_start_chip(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - unsigned short oldConfig; - - /* enable rx dma channel */ - dbdma_continue(rd); - - oldConfig = bmread(dev, TXCFG); - bmwrite(dev, TXCFG, oldConfig | TxMACEnable ); - - /* turn on rx plus any other bits already on (promiscuous possibly) */ - oldConfig = bmread(dev, RXCFG); - bmwrite(dev, RXCFG, oldConfig | RxMACEnable ); - udelay(20000); -} - -static void -bmac_init_phy(struct net_device *dev) -{ - unsigned int addr; - struct bmac_data *bp = netdev_priv(dev); - - printk(KERN_DEBUG "phy registers:"); - for (addr = 0; addr < 32; ++addr) { - if ((addr & 7) == 0) - printk(KERN_DEBUG); - printk(KERN_CONT " %.4x", bmac_mif_read(dev, addr)); - } - printk(KERN_CONT "\n"); - - if (bp->is_bmac_plus) { - unsigned int capable, ctrl; - - ctrl = bmac_mif_read(dev, 0); - capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1; - if (bmac_mif_read(dev, 4) != capable || - (ctrl & 0x1000) == 0) { - bmac_mif_write(dev, 4, capable); - bmac_mif_write(dev, 0, 0x1200); - } else - bmac_mif_write(dev, 0, 0x1000); - } -} - -static void bmac_init_chip(struct net_device *dev) -{ - bmac_init_phy(dev); - bmac_init_registers(dev); -} - -#ifdef CONFIG_PM -static int bmac_suspend(struct macio_dev *mdev, pm_message_t state) -{ - struct net_device* dev = macio_get_drvdata(mdev); - struct bmac_data *bp = netdev_priv(dev); - unsigned long flags; - unsigned short config; - int i; - - netif_device_detach(dev); - /* prolly should wait for dma to finish & turn off the chip */ - spin_lock_irqsave(&bp->lock, flags); - if (bp->timeout_active) { - del_timer(&bp->tx_timeout); - bp->timeout_active = 0; - } - disable_irq(dev->irq); - disable_irq(bp->tx_dma_intr); - disable_irq(bp->rx_dma_intr); - bp->sleeping = 1; - spin_unlock_irqrestore(&bp->lock, flags); - if (bp->opened) { - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - volatile struct dbdma_regs __iomem *td = bp->tx_dma; - - config = bmread(dev, RXCFG); - bmwrite(dev, RXCFG, (config & ~RxMACEnable)); - config = bmread(dev, TXCFG); - bmwrite(dev, TXCFG, (config & ~TxMACEnable)); - bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */ - /* disable rx and tx dma */ - st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ - st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ - /* free some skb's */ - for (i=0; irx_bufs[i] != NULL) { - dev_kfree_skb(bp->rx_bufs[i]); - bp->rx_bufs[i] = NULL; - } - } - for (i = 0; itx_bufs[i] != NULL) { - dev_kfree_skb(bp->tx_bufs[i]); - bp->tx_bufs[i] = NULL; - } - } - } - pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); - return 0; -} - -static int bmac_resume(struct macio_dev *mdev) -{ - struct net_device* dev = macio_get_drvdata(mdev); - struct bmac_data *bp = netdev_priv(dev); - - /* see if this is enough */ - if (bp->opened) - bmac_reset_and_enable(dev); - - enable_irq(dev->irq); - enable_irq(bp->tx_dma_intr); - enable_irq(bp->rx_dma_intr); - netif_device_attach(dev); - - return 0; -} -#endif /* CONFIG_PM */ - -static int bmac_set_address(struct net_device *dev, void *addr) -{ - struct bmac_data *bp = netdev_priv(dev); - unsigned char *p = addr; - unsigned short *pWord16; - unsigned long flags; - int i; - - XXDEBUG(("bmac: enter set_address\n")); - spin_lock_irqsave(&bp->lock, flags); - - for (i = 0; i < 6; ++i) { - dev->dev_addr[i] = p[i]; - } - /* load up the hardware address */ - pWord16 = (unsigned short *)dev->dev_addr; - bmwrite(dev, MADD0, *pWord16++); - bmwrite(dev, MADD1, *pWord16++); - bmwrite(dev, MADD2, *pWord16); - - spin_unlock_irqrestore(&bp->lock, flags); - XXDEBUG(("bmac: exit set_address\n")); - return 0; -} - -static inline void bmac_set_timeout(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - unsigned long flags; - - spin_lock_irqsave(&bp->lock, flags); - if (bp->timeout_active) - del_timer(&bp->tx_timeout); - bp->tx_timeout.expires = jiffies + TX_TIMEOUT; - bp->tx_timeout.function = bmac_tx_timeout; - bp->tx_timeout.data = (unsigned long) dev; - add_timer(&bp->tx_timeout); - bp->timeout_active = 1; - spin_unlock_irqrestore(&bp->lock, flags); -} - -static void -bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp) -{ - void *vaddr; - unsigned long baddr; - unsigned long len; - - len = skb->len; - vaddr = skb->data; - baddr = virt_to_bus(vaddr); - - dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0); -} - -static void -bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp) -{ - unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf; - - dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN, - virt_to_bus(addr), 0); -} - -static void -bmac_init_tx_ring(struct bmac_data *bp) -{ - volatile struct dbdma_regs __iomem *td = bp->tx_dma; - - memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd)); - - bp->tx_empty = 0; - bp->tx_fill = 0; - bp->tx_fullup = 0; - - /* put a branch at the end of the tx command list */ - dbdma_setcmd(&bp->tx_cmds[N_TX_RING], - (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds)); - - /* reset tx dma */ - dbdma_reset(td); - out_le32(&td->wait_sel, 0x00200020); - out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds)); -} - -static int -bmac_init_rx_ring(struct bmac_data *bp) -{ - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - int i; - struct sk_buff *skb; - - /* initialize list of sk_buffs for receiving and set up recv dma */ - memset((char *)bp->rx_cmds, 0, - (N_RX_RING + 1) * sizeof(struct dbdma_cmd)); - for (i = 0; i < N_RX_RING; i++) { - if ((skb = bp->rx_bufs[i]) == NULL) { - bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2); - if (skb != NULL) - skb_reserve(skb, 2); - } - bmac_construct_rxbuff(skb, &bp->rx_cmds[i]); - } - - bp->rx_empty = 0; - bp->rx_fill = i; - - /* Put a branch back to the beginning of the receive command list */ - dbdma_setcmd(&bp->rx_cmds[N_RX_RING], - (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds)); - - /* start rx dma */ - dbdma_reset(rd); - out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds)); - - return 1; -} - - -static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *td = bp->tx_dma; - int i; - - /* see if there's a free slot in the tx ring */ - /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */ - /* bp->tx_empty, bp->tx_fill)); */ - i = bp->tx_fill + 1; - if (i >= N_TX_RING) - i = 0; - if (i == bp->tx_empty) { - netif_stop_queue(dev); - bp->tx_fullup = 1; - XXDEBUG(("bmac_transmit_packet: tx ring full\n")); - return -1; /* can't take it at the moment */ - } - - dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0); - - bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]); - - bp->tx_bufs[bp->tx_fill] = skb; - bp->tx_fill = i; - - dev->stats.tx_bytes += skb->len; - - dbdma_continue(td); - - return 0; -} - -static int rxintcount; - -static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - volatile struct dbdma_cmd *cp; - int i, nb, stat; - struct sk_buff *skb; - unsigned int residual; - int last; - unsigned long flags; - - spin_lock_irqsave(&bp->lock, flags); - - if (++rxintcount < 10) { - XXDEBUG(("bmac_rxdma_intr\n")); - } - - last = -1; - i = bp->rx_empty; - - while (1) { - cp = &bp->rx_cmds[i]; - stat = ld_le16(&cp->xfer_status); - residual = ld_le16(&cp->res_count); - if ((stat & ACTIVE) == 0) - break; - nb = RX_BUFLEN - residual - 2; - if (nb < (ETHERMINPACKET - ETHERCRC)) { - skb = NULL; - dev->stats.rx_length_errors++; - dev->stats.rx_errors++; - } else { - skb = bp->rx_bufs[i]; - bp->rx_bufs[i] = NULL; - } - if (skb != NULL) { - nb -= ETHERCRC; - skb_put(skb, nb); - skb->protocol = eth_type_trans(skb, dev); - netif_rx(skb); - ++dev->stats.rx_packets; - dev->stats.rx_bytes += nb; - } else { - ++dev->stats.rx_dropped; - } - if ((skb = bp->rx_bufs[i]) == NULL) { - bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2); - if (skb != NULL) - skb_reserve(bp->rx_bufs[i], 2); - } - bmac_construct_rxbuff(skb, &bp->rx_cmds[i]); - st_le16(&cp->res_count, 0); - st_le16(&cp->xfer_status, 0); - last = i; - if (++i >= N_RX_RING) i = 0; - } - - if (last != -1) { - bp->rx_fill = last; - bp->rx_empty = i; - } - - dbdma_continue(rd); - spin_unlock_irqrestore(&bp->lock, flags); - - if (rxintcount < 10) { - XXDEBUG(("bmac_rxdma_intr done\n")); - } - return IRQ_HANDLED; -} - -static int txintcount; - -static irqreturn_t bmac_txdma_intr(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_cmd *cp; - int stat; - unsigned long flags; - - spin_lock_irqsave(&bp->lock, flags); - - if (txintcount++ < 10) { - XXDEBUG(("bmac_txdma_intr\n")); - } - - /* del_timer(&bp->tx_timeout); */ - /* bp->timeout_active = 0; */ - - while (1) { - cp = &bp->tx_cmds[bp->tx_empty]; - stat = ld_le16(&cp->xfer_status); - if (txintcount < 10) { - XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat)); - } - if (!(stat & ACTIVE)) { - /* - * status field might not have been filled by DBDMA - */ - if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr))) - break; - } - - if (bp->tx_bufs[bp->tx_empty]) { - ++dev->stats.tx_packets; - dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]); - } - bp->tx_bufs[bp->tx_empty] = NULL; - bp->tx_fullup = 0; - netif_wake_queue(dev); - if (++bp->tx_empty >= N_TX_RING) - bp->tx_empty = 0; - if (bp->tx_empty == bp->tx_fill) - break; - } - - spin_unlock_irqrestore(&bp->lock, flags); - - if (txintcount < 10) { - XXDEBUG(("bmac_txdma_intr done->bmac_start\n")); - } - - bmac_start(dev); - return IRQ_HANDLED; -} - -#ifndef SUNHME_MULTICAST -/* Real fast bit-reversal algorithm, 6-bit values */ -static int reverse6[64] = { - 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38, - 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c, - 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a, - 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e, - 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39, - 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d, - 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b, - 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f -}; - -static unsigned int -crc416(unsigned int curval, unsigned short nxtval) -{ - register unsigned int counter, cur = curval, next = nxtval; - register int high_crc_set, low_data_set; - - /* Swap bytes */ - next = ((next & 0x00FF) << 8) | (next >> 8); - - /* Compute bit-by-bit */ - for (counter = 0; counter < 16; ++counter) { - /* is high CRC bit set? */ - if ((cur & 0x80000000) == 0) high_crc_set = 0; - else high_crc_set = 1; - - cur = cur << 1; - - if ((next & 0x0001) == 0) low_data_set = 0; - else low_data_set = 1; - - next = next >> 1; - - /* do the XOR */ - if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY; - } - return cur; -} - -static unsigned int -bmac_crc(unsigned short *address) -{ - unsigned int newcrc; - - XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2])); - newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */ - newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */ - newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */ - - return(newcrc); -} - -/* - * Add requested mcast addr to BMac's hash table filter. - * - */ - -static void -bmac_addhash(struct bmac_data *bp, unsigned char *addr) -{ - unsigned int crc; - unsigned short mask; - - if (!(*addr)) return; - crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */ - crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */ - if (bp->hash_use_count[crc]++) return; /* This bit is already set */ - mask = crc % 16; - mask = (unsigned char)1 << mask; - bp->hash_use_count[crc/16] |= mask; -} - -static void -bmac_removehash(struct bmac_data *bp, unsigned char *addr) -{ - unsigned int crc; - unsigned char mask; - - /* Now, delete the address from the filter copy, as indicated */ - crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */ - crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */ - if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */ - if (--bp->hash_use_count[crc]) return; /* That bit is still in use */ - mask = crc % 16; - mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */ - bp->hash_table_mask[crc/16] &= mask; -} - -/* - * Sync the adapter with the software copy of the multicast mask - * (logical address filter). - */ - -static void -bmac_rx_off(struct net_device *dev) -{ - unsigned short rx_cfg; - - rx_cfg = bmread(dev, RXCFG); - rx_cfg &= ~RxMACEnable; - bmwrite(dev, RXCFG, rx_cfg); - do { - rx_cfg = bmread(dev, RXCFG); - } while (rx_cfg & RxMACEnable); -} - -unsigned short -bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable) -{ - unsigned short rx_cfg; - - rx_cfg = bmread(dev, RXCFG); - rx_cfg |= RxMACEnable; - if (hash_enable) rx_cfg |= RxHashFilterEnable; - else rx_cfg &= ~RxHashFilterEnable; - if (promisc_enable) rx_cfg |= RxPromiscEnable; - else rx_cfg &= ~RxPromiscEnable; - bmwrite(dev, RXRST, RxResetValue); - bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */ - bmwrite(dev, RXFIFOCSR, RxFIFOEnable ); - bmwrite(dev, RXCFG, rx_cfg ); - return rx_cfg; -} - -static void -bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp) -{ - bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */ - bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */ - bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */ - bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */ -} - -#if 0 -static void -bmac_add_multi(struct net_device *dev, - struct bmac_data *bp, unsigned char *addr) -{ - /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */ - bmac_addhash(bp, addr); - bmac_rx_off(dev); - bmac_update_hash_table_mask(dev, bp); - bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0); - /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */ -} - -static void -bmac_remove_multi(struct net_device *dev, - struct bmac_data *bp, unsigned char *addr) -{ - bmac_removehash(bp, addr); - bmac_rx_off(dev); - bmac_update_hash_table_mask(dev, bp); - bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0); -} -#endif - -/* Set or clear the multicast filter for this adaptor. - num_addrs == -1 Promiscuous mode, receive all packets - num_addrs == 0 Normal mode, clear multicast list - num_addrs > 0 Multicast mode, receive normal and MC packets, and do - best-effort filtering. - */ -static void bmac_set_multicast(struct net_device *dev) -{ - struct netdev_hw_addr *ha; - struct bmac_data *bp = netdev_priv(dev); - int num_addrs = netdev_mc_count(dev); - unsigned short rx_cfg; - int i; - - if (bp->sleeping) - return; - - XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs)); - - if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { - for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff; - bmac_update_hash_table_mask(dev, bp); - rx_cfg = bmac_rx_on(dev, 1, 0); - XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n")); - } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) { - rx_cfg = bmread(dev, RXCFG); - rx_cfg |= RxPromiscEnable; - bmwrite(dev, RXCFG, rx_cfg); - rx_cfg = bmac_rx_on(dev, 0, 1); - XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg)); - } else { - for (i=0; i<4; i++) bp->hash_table_mask[i] = 0; - for (i=0; i<64; i++) bp->hash_use_count[i] = 0; - if (num_addrs == 0) { - rx_cfg = bmac_rx_on(dev, 0, 0); - XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg)); - } else { - netdev_for_each_mc_addr(ha, dev) - bmac_addhash(bp, ha->addr); - bmac_update_hash_table_mask(dev, bp); - rx_cfg = bmac_rx_on(dev, 1, 0); - XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg)); - } - } - /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */ -} -#else /* ifdef SUNHME_MULTICAST */ - -/* The version of set_multicast below was lifted from sunhme.c */ - -static void bmac_set_multicast(struct net_device *dev) -{ - struct netdev_hw_addr *ha; - int i; - unsigned short rx_cfg; - u32 crc; - - if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { - bmwrite(dev, BHASH0, 0xffff); - bmwrite(dev, BHASH1, 0xffff); - bmwrite(dev, BHASH2, 0xffff); - bmwrite(dev, BHASH3, 0xffff); - } else if(dev->flags & IFF_PROMISC) { - rx_cfg = bmread(dev, RXCFG); - rx_cfg |= RxPromiscEnable; - bmwrite(dev, RXCFG, rx_cfg); - } else { - u16 hash_table[4]; - - rx_cfg = bmread(dev, RXCFG); - rx_cfg &= ~RxPromiscEnable; - bmwrite(dev, RXCFG, rx_cfg); - - for(i = 0; i < 4; i++) hash_table[i] = 0; - - netdev_for_each_mc_addr(ha, dev) { - crc = ether_crc_le(6, ha->addr); - crc >>= 26; - hash_table[crc >> 4] |= 1 << (crc & 0xf); - } - bmwrite(dev, BHASH0, hash_table[0]); - bmwrite(dev, BHASH1, hash_table[1]); - bmwrite(dev, BHASH2, hash_table[2]); - bmwrite(dev, BHASH3, hash_table[3]); - } -} -#endif /* SUNHME_MULTICAST */ - -static int miscintcount; - -static irqreturn_t bmac_misc_intr(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - unsigned int status = bmread(dev, STATUS); - if (miscintcount++ < 10) { - XXDEBUG(("bmac_misc_intr\n")); - } - /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */ - /* bmac_txdma_intr_inner(irq, dev_id); */ - /* if (status & FrameReceived) dev->stats.rx_dropped++; */ - if (status & RxErrorMask) dev->stats.rx_errors++; - if (status & RxCRCCntExp) dev->stats.rx_crc_errors++; - if (status & RxLenCntExp) dev->stats.rx_length_errors++; - if (status & RxOverFlow) dev->stats.rx_over_errors++; - if (status & RxAlignCntExp) dev->stats.rx_frame_errors++; - - /* if (status & FrameSent) dev->stats.tx_dropped++; */ - if (status & TxErrorMask) dev->stats.tx_errors++; - if (status & TxUnderrun) dev->stats.tx_fifo_errors++; - if (status & TxNormalCollExp) dev->stats.collisions++; - return IRQ_HANDLED; -} - -/* - * Procedure for reading EEPROM - */ -#define SROMAddressLength 5 -#define DataInOn 0x0008 -#define DataInOff 0x0000 -#define Clk 0x0002 -#define ChipSelect 0x0001 -#define SDIShiftCount 3 -#define SD0ShiftCount 2 -#define DelayValue 1000 /* number of microseconds */ -#define SROMStartOffset 10 /* this is in words */ -#define SROMReadCount 3 /* number of words to read from SROM */ -#define SROMAddressBits 6 -#define EnetAddressOffset 20 - -static unsigned char -bmac_clock_out_bit(struct net_device *dev) -{ - unsigned short data; - unsigned short val; - - bmwrite(dev, SROMCSR, ChipSelect | Clk); - udelay(DelayValue); - - data = bmread(dev, SROMCSR); - udelay(DelayValue); - val = (data >> SD0ShiftCount) & 1; - - bmwrite(dev, SROMCSR, ChipSelect); - udelay(DelayValue); - - return val; -} - -static void -bmac_clock_in_bit(struct net_device *dev, unsigned int val) -{ - unsigned short data; - - if (val != 0 && val != 1) return; - - data = (val << SDIShiftCount); - bmwrite(dev, SROMCSR, data | ChipSelect ); - udelay(DelayValue); - - bmwrite(dev, SROMCSR, data | ChipSelect | Clk ); - udelay(DelayValue); - - bmwrite(dev, SROMCSR, data | ChipSelect); - udelay(DelayValue); -} - -static void -reset_and_select_srom(struct net_device *dev) -{ - /* first reset */ - bmwrite(dev, SROMCSR, 0); - udelay(DelayValue); - - /* send it the read command (110) */ - bmac_clock_in_bit(dev, 1); - bmac_clock_in_bit(dev, 1); - bmac_clock_in_bit(dev, 0); -} - -static unsigned short -read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len) -{ - unsigned short data, val; - int i; - - /* send out the address we want to read from */ - for (i = 0; i < addr_len; i++) { - val = addr >> (addr_len-i-1); - bmac_clock_in_bit(dev, val & 1); - } - - /* Now read in the 16-bit data */ - data = 0; - for (i = 0; i < 16; i++) { - val = bmac_clock_out_bit(dev); - data <<= 1; - data |= val; - } - bmwrite(dev, SROMCSR, 0); - - return data; -} - -/* - * It looks like Cogent and SMC use different methods for calculating - * checksums. What a pain.. - */ - -static int -bmac_verify_checksum(struct net_device *dev) -{ - unsigned short data, storedCS; - - reset_and_select_srom(dev); - data = read_srom(dev, 3, SROMAddressBits); - storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00); - - return 0; -} - - -static void -bmac_get_station_address(struct net_device *dev, unsigned char *ea) -{ - int i; - unsigned short data; - - for (i = 0; i < 6; i++) - { - reset_and_select_srom(dev); - data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits); - ea[2*i] = bitrev8(data & 0x0ff); - ea[2*i+1] = bitrev8((data >> 8) & 0x0ff); - } -} - -static void bmac_reset_and_enable(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - unsigned long flags; - struct sk_buff *skb; - unsigned char *data; - - spin_lock_irqsave(&bp->lock, flags); - bmac_enable_and_reset_chip(dev); - bmac_init_tx_ring(bp); - bmac_init_rx_ring(bp); - bmac_init_chip(dev); - bmac_start_chip(dev); - bmwrite(dev, INTDISABLE, EnableNormal); - bp->sleeping = 0; - - /* - * It seems that the bmac can't receive until it's transmitted - * a packet. So we give it a dummy packet to transmit. - */ - skb = dev_alloc_skb(ETHERMINPACKET); - if (skb != NULL) { - data = skb_put(skb, ETHERMINPACKET); - memset(data, 0, ETHERMINPACKET); - memcpy(data, dev->dev_addr, 6); - memcpy(data+6, dev->dev_addr, 6); - bmac_transmit_packet(skb, dev); - } - spin_unlock_irqrestore(&bp->lock, flags); -} - -static const struct ethtool_ops bmac_ethtool_ops = { - .get_link = ethtool_op_get_link, -}; - -static const struct net_device_ops bmac_netdev_ops = { - .ndo_open = bmac_open, - .ndo_stop = bmac_close, - .ndo_start_xmit = bmac_output, - .ndo_set_multicast_list = bmac_set_multicast, - .ndo_set_mac_address = bmac_set_address, - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, -}; - -static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match) -{ - int j, rev, ret; - struct bmac_data *bp; - const unsigned char *prop_addr; - unsigned char addr[6]; - struct net_device *dev; - int is_bmac_plus = ((int)match->data) != 0; - - if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { - printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n"); - return -ENODEV; - } - prop_addr = of_get_property(macio_get_of_node(mdev), - "mac-address", NULL); - if (prop_addr == NULL) { - prop_addr = of_get_property(macio_get_of_node(mdev), - "local-mac-address", NULL); - if (prop_addr == NULL) { - printk(KERN_ERR "BMAC: Can't get mac-address\n"); - return -ENODEV; - } - } - memcpy(addr, prop_addr, sizeof(addr)); - - dev = alloc_etherdev(PRIV_BYTES); - if (!dev) { - printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n"); - return -ENOMEM; - } - - bp = netdev_priv(dev); - SET_NETDEV_DEV(dev, &mdev->ofdev.dev); - macio_set_drvdata(mdev, dev); - - bp->mdev = mdev; - spin_lock_init(&bp->lock); - - if (macio_request_resources(mdev, "bmac")) { - printk(KERN_ERR "BMAC: can't request IO resource !\n"); - goto out_free; - } - - dev->base_addr = (unsigned long) - ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0)); - if (dev->base_addr == 0) - goto out_release; - - dev->irq = macio_irq(mdev, 0); - - bmac_enable_and_reset_chip(dev); - bmwrite(dev, INTDISABLE, DisableAll); - - rev = addr[0] == 0 && addr[1] == 0xA0; - for (j = 0; j < 6; ++j) - dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; - - /* Enable chip without interrupts for now */ - bmac_enable_and_reset_chip(dev); - bmwrite(dev, INTDISABLE, DisableAll); - - dev->netdev_ops = &bmac_netdev_ops; - dev->ethtool_ops = &bmac_ethtool_ops; - - bmac_get_station_address(dev, addr); - if (bmac_verify_checksum(dev) != 0) - goto err_out_iounmap; - - bp->is_bmac_plus = is_bmac_plus; - bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1)); - if (!bp->tx_dma) - goto err_out_iounmap; - bp->tx_dma_intr = macio_irq(mdev, 1); - bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2)); - if (!bp->rx_dma) - goto err_out_iounmap_tx; - bp->rx_dma_intr = macio_irq(mdev, 2); - - bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1); - bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1; - - bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1); - skb_queue_head_init(bp->queue); - - init_timer(&bp->tx_timeout); - - ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev); - if (ret) { - printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq); - goto err_out_iounmap_rx; - } - ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev); - if (ret) { - printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr); - goto err_out_irq0; - } - ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev); - if (ret) { - printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr); - goto err_out_irq1; - } - - /* Mask chip interrupts and disable chip, will be - * re-enabled on open() - */ - disable_irq(dev->irq); - pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); - - if (register_netdev(dev) != 0) { - printk(KERN_ERR "BMAC: Ethernet registration failed\n"); - goto err_out_irq2; - } - - printk(KERN_INFO "%s: BMAC%s at %pM", - dev->name, (is_bmac_plus ? "+" : ""), dev->dev_addr); - XXDEBUG((", base_addr=%#0lx", dev->base_addr)); - printk("\n"); - - return 0; - -err_out_irq2: - free_irq(bp->rx_dma_intr, dev); -err_out_irq1: - free_irq(bp->tx_dma_intr, dev); -err_out_irq0: - free_irq(dev->irq, dev); -err_out_iounmap_rx: - iounmap(bp->rx_dma); -err_out_iounmap_tx: - iounmap(bp->tx_dma); -err_out_iounmap: - iounmap((void __iomem *)dev->base_addr); -out_release: - macio_release_resources(mdev); -out_free: - pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); - free_netdev(dev); - - return -ENODEV; -} - -static int bmac_open(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - /* XXDEBUG(("bmac: enter open\n")); */ - /* reset the chip */ - bp->opened = 1; - bmac_reset_and_enable(dev); - enable_irq(dev->irq); - return 0; -} - -static int bmac_close(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - volatile struct dbdma_regs __iomem *td = bp->tx_dma; - unsigned short config; - int i; - - bp->sleeping = 1; - - /* disable rx and tx */ - config = bmread(dev, RXCFG); - bmwrite(dev, RXCFG, (config & ~RxMACEnable)); - - config = bmread(dev, TXCFG); - bmwrite(dev, TXCFG, (config & ~TxMACEnable)); - - bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */ - - /* disable rx and tx dma */ - st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ - st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ - - /* free some skb's */ - XXDEBUG(("bmac: free rx bufs\n")); - for (i=0; irx_bufs[i] != NULL) { - dev_kfree_skb(bp->rx_bufs[i]); - bp->rx_bufs[i] = NULL; - } - } - XXDEBUG(("bmac: free tx bufs\n")); - for (i = 0; itx_bufs[i] != NULL) { - dev_kfree_skb(bp->tx_bufs[i]); - bp->tx_bufs[i] = NULL; - } - } - XXDEBUG(("bmac: all bufs freed\n")); - - bp->opened = 0; - disable_irq(dev->irq); - pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); - - return 0; -} - -static void -bmac_start(struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - int i; - struct sk_buff *skb; - unsigned long flags; - - if (bp->sleeping) - return; - - spin_lock_irqsave(&bp->lock, flags); - while (1) { - i = bp->tx_fill + 1; - if (i >= N_TX_RING) - i = 0; - if (i == bp->tx_empty) - break; - skb = skb_dequeue(bp->queue); - if (skb == NULL) - break; - bmac_transmit_packet(skb, dev); - } - spin_unlock_irqrestore(&bp->lock, flags); -} - -static int -bmac_output(struct sk_buff *skb, struct net_device *dev) -{ - struct bmac_data *bp = netdev_priv(dev); - skb_queue_tail(bp->queue, skb); - bmac_start(dev); - return NETDEV_TX_OK; -} - -static void bmac_tx_timeout(unsigned long data) -{ - struct net_device *dev = (struct net_device *) data; - struct bmac_data *bp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *td = bp->tx_dma; - volatile struct dbdma_regs __iomem *rd = bp->rx_dma; - volatile struct dbdma_cmd *cp; - unsigned long flags; - unsigned short config, oldConfig; - int i; - - XXDEBUG(("bmac: tx_timeout called\n")); - spin_lock_irqsave(&bp->lock, flags); - bp->timeout_active = 0; - - /* update various counters */ -/* bmac_handle_misc_intrs(bp, 0); */ - - cp = &bp->tx_cmds[bp->tx_empty]; -/* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */ -/* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */ -/* mb->pr, mb->xmtfs, mb->fifofc)); */ - - /* turn off both tx and rx and reset the chip */ - config = bmread(dev, RXCFG); - bmwrite(dev, RXCFG, (config & ~RxMACEnable)); - config = bmread(dev, TXCFG); - bmwrite(dev, TXCFG, (config & ~TxMACEnable)); - out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); - printk(KERN_ERR "bmac: transmit timeout - resetting\n"); - bmac_enable_and_reset_chip(dev); - - /* restart rx dma */ - cp = bus_to_virt(ld_le32(&rd->cmdptr)); - out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); - out_le16(&cp->xfer_status, 0); - out_le32(&rd->cmdptr, virt_to_bus(cp)); - out_le32(&rd->control, DBDMA_SET(RUN|WAKE)); - - /* fix up the transmit side */ - XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n", - bp->tx_empty, bp->tx_fill, bp->tx_fullup)); - i = bp->tx_empty; - ++dev->stats.tx_errors; - if (i != bp->tx_fill) { - dev_kfree_skb(bp->tx_bufs[i]); - bp->tx_bufs[i] = NULL; - if (++i >= N_TX_RING) i = 0; - bp->tx_empty = i; - } - bp->tx_fullup = 0; - netif_wake_queue(dev); - if (i != bp->tx_fill) { - cp = &bp->tx_cmds[i]; - out_le16(&cp->xfer_status, 0); - out_le16(&cp->command, OUTPUT_LAST); - out_le32(&td->cmdptr, virt_to_bus(cp)); - out_le32(&td->control, DBDMA_SET(RUN)); - /* bmac_set_timeout(dev); */ - XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i)); - } - - /* turn it back on */ - oldConfig = bmread(dev, RXCFG); - bmwrite(dev, RXCFG, oldConfig | RxMACEnable ); - oldConfig = bmread(dev, TXCFG); - bmwrite(dev, TXCFG, oldConfig | TxMACEnable ); - - spin_unlock_irqrestore(&bp->lock, flags); -} - -#if 0 -static void dump_dbdma(volatile struct dbdma_cmd *cp,int count) -{ - int i,*ip; - - for (i=0;i< count;i++) { - ip = (int*)(cp+i); - - printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n", - ld_le32(ip+0), - ld_le32(ip+1), - ld_le32(ip+2), - ld_le32(ip+3)); - } - -} -#endif - -#if 0 -static int -bmac_proc_info(char *buffer, char **start, off_t offset, int length) -{ - int len = 0; - off_t pos = 0; - off_t begin = 0; - int i; - - if (bmac_devs == NULL) - return -ENOSYS; - - len += sprintf(buffer, "BMAC counters & registers\n"); - - for (i = 0; i offset+length) break; - } - - *start = buffer + (offset - begin); - len -= (offset - begin); - - if (len > length) len = length; - - return len; -} -#endif - -static int __devexit bmac_remove(struct macio_dev *mdev) -{ - struct net_device *dev = macio_get_drvdata(mdev); - struct bmac_data *bp = netdev_priv(dev); - - unregister_netdev(dev); - - free_irq(dev->irq, dev); - free_irq(bp->tx_dma_intr, dev); - free_irq(bp->rx_dma_intr, dev); - - iounmap((void __iomem *)dev->base_addr); - iounmap(bp->tx_dma); - iounmap(bp->rx_dma); - - macio_release_resources(mdev); - - free_netdev(dev); - - return 0; -} - -static struct of_device_id bmac_match[] = -{ - { - .name = "bmac", - .data = (void *)0, - }, - { - .type = "network", - .compatible = "bmac+", - .data = (void *)1, - }, - {}, -}; -MODULE_DEVICE_TABLE (of, bmac_match); - -static struct macio_driver bmac_driver = -{ - .driver = { - .name = "bmac", - .owner = THIS_MODULE, - .of_match_table = bmac_match, - }, - .probe = bmac_probe, - .remove = bmac_remove, -#ifdef CONFIG_PM - .suspend = bmac_suspend, - .resume = bmac_resume, -#endif -}; - - -static int __init bmac_init(void) -{ - if (bmac_emergency_rxbuf == NULL) { - bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL); - if (bmac_emergency_rxbuf == NULL) { - printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n"); - return -ENOMEM; - } - } - - return macio_register_driver(&bmac_driver); -} - -static void __exit bmac_exit(void) -{ - macio_unregister_driver(&bmac_driver); - - kfree(bmac_emergency_rxbuf); - bmac_emergency_rxbuf = NULL; -} - -MODULE_AUTHOR("Randy Gobbel/Paul Mackerras"); -MODULE_DESCRIPTION("PowerMac BMAC ethernet driver."); -MODULE_LICENSE("GPL"); - -module_init(bmac_init); -module_exit(bmac_exit); diff --git a/drivers/net/bmac.h b/drivers/net/bmac.h deleted file mode 100644 index a1d19d867ba..00000000000 --- a/drivers/net/bmac.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * mace.h - definitions for the registers in the "Big Mac" - * Ethernet controller found in PowerMac G3 models. - * - * Copyright (C) 1998 Randy Gobbel. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal" - * (HME) controller. See sunhme.h - */ - - -/* register offsets */ - -/* global status and control */ -#define XIFC 0x000 /* low-level interface control */ -# define TxOutputEnable 0x0001 /* output driver enable */ -# define XIFLoopback 0x0002 /* Loopback-mode XIF enable */ -# define MIILoopback 0x0004 /* Loopback-mode MII enable */ -# define MIILoopbackBits 0x0006 -# define MIIBuffDisable 0x0008 /* MII receive buffer disable */ -# define SQETestEnable 0x0010 /* SQE test enable */ -# define SQETimeWindow 0x03e0 /* SQE time window */ -# define XIFLanceMode 0x0010 /* Lance mode enable */ -# define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */ -#define TXFIFOCSR 0x100 /* transmit FIFO control */ -# define TxFIFOEnable 0x0001 -#define TXTH 0x110 /* transmit threshold */ -# define TxThreshold 0x0004 -#define RXFIFOCSR 0x120 /* receive FIFO control */ -# define RxFIFOEnable 0x0001 -#define MEMADD 0x130 /* memory address, unknown function */ -#define MEMDATAHI 0x140 /* memory data high, presently unused in driver */ -#define MEMDATALO 0x150 /* memory data low, presently unused in driver */ -#define XCVRIF 0x160 /* transceiver interface control */ -# define COLActiveLow 0x0002 -# define SerialMode 0x0004 -# define ClkBit 0x0008 -# define LinkStatus 0x0100 -#define CHIPID 0x170 /* chip ID */ -#define MIFCSR 0x180 /* ??? */ -#define SROMCSR 0x190 /* SROM control */ -# define ChipSelect 0x0001 -# define Clk 0x0002 -#define TXPNTR 0x1a0 /* transmit pointer */ -#define RXPNTR 0x1b0 /* receive pointer */ -#define STATUS 0x200 /* status--reading this clears it */ -#define INTDISABLE 0x210 /* interrupt enable/disable control */ -/* bits below are the same in both STATUS and INTDISABLE registers */ -# define FrameReceived 0x00000001 /* Received a frame */ -# define RxFrameCntExp 0x00000002 /* Receive frame counter expired */ -# define RxAlignCntExp 0x00000004 /* Align-error counter expired */ -# define RxCRCCntExp 0x00000008 /* CRC-error counter expired */ -# define RxLenCntExp 0x00000010 /* Length-error counter expired */ -# define RxOverFlow 0x00000020 /* Receive FIFO overflow */ -# define RxCodeViolation 0x00000040 /* Code-violation counter expired */ -# define SQETestError 0x00000080 /* Test error in XIF for SQE */ -# define FrameSent 0x00000100 /* Transmitted a frame */ -# define TxUnderrun 0x00000200 /* Transmit FIFO underrun */ -# define TxMaxSizeError 0x00000400 /* Max-packet size error */ -# define TxNormalCollExp 0x00000800 /* Normal-collision counter expired */ -# define TxExcessCollExp 0x00001000 /* Excess-collision counter expired */ -# define TxLateCollExp 0x00002000 /* Late-collision counter expired */ -# define TxNetworkCollExp 0x00004000 /* First-collision counter expired */ -# define TxDeferTimerExp 0x00008000 /* Defer-timer expired */ -# define RxFIFOToHost 0x00010000 /* Data moved from FIFO to host */ -# define RxNoDescriptors 0x00020000 /* No more receive descriptors */ -# define RxDMAError 0x00040000 /* Error during receive DMA */ -# define RxDMALateErr 0x00080000 /* Receive DMA, data late */ -# define RxParityErr 0x00100000 /* Parity error during receive DMA */ -# define RxTagError 0x00200000 /* Tag error during receive DMA */ -# define TxEOPError 0x00400000 /* Tx descriptor did not have EOP set */ -# define MIFIntrEvent 0x00800000 /* MIF is signaling an interrupt */ -# define TxHostToFIFO 0x01000000 /* Data moved from host to FIFO */ -# define TxFIFOAllSent 0x02000000 /* Transmitted all packets in FIFO */ -# define TxDMAError 0x04000000 /* Error during transmit DMA */ -# define TxDMALateError 0x08000000 /* Late error during transmit DMA */ -# define TxParityError 0x10000000 /* Parity error during transmit DMA */ -# define TxTagError 0x20000000 /* Tag error during transmit DMA */ -# define PIOError 0x40000000 /* PIO access got an error */ -# define PIOParityError 0x80000000 /* PIO access got a parity error */ -# define DisableAll 0xffffffff -# define EnableAll 0x00000000 -/* # define NormalIntEvents ~(FrameReceived | FrameSent | TxUnderrun) */ -# define EnableNormal ~(FrameReceived | FrameSent) -# define EnableErrors (FrameReceived | FrameSent) -# define RxErrorMask (RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \ - RxLenCntExp | RxOverFlow | RxCodeViolation) -# define TxErrorMask (TxUnderrun | TxMaxSizeError | TxExcessCollExp | \ - TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp) - -/* transmit control */ -#define TXRST 0x420 /* transmit reset */ -# define TxResetBit 0x0001 -#define TXCFG 0x430 /* transmit configuration control*/ -# define TxMACEnable 0x0001 /* output driver enable */ -# define TxSlowMode 0x0020 /* enable slow mode */ -# define TxIgnoreColl 0x0040 /* ignore transmit collisions */ -# define TxNoFCS 0x0080 /* do not emit FCS */ -# define TxNoBackoff 0x0100 /* no backoff in case of collisions */ -# define TxFullDuplex 0x0200 /* enable full-duplex */ -# define TxNeverGiveUp 0x0400 /* don't give up on transmits */ -#define IPG1 0x440 /* Inter-packet gap 1 */ -#define IPG2 0x450 /* Inter-packet gap 2 */ -#define ALIMIT 0x460 /* Transmit attempt limit */ -#define SLOT 0x470 /* Transmit slot time */ -#define PALEN 0x480 /* Size of transmit preamble */ -#define PAPAT 0x490 /* Pattern for transmit preamble */ -#define TXSFD 0x4a0 /* Transmit frame delimiter */ -#define JAM 0x4b0 /* Jam size */ -#define TXMAX 0x4c0 /* Transmit max pkt size */ -#define TXMIN 0x4d0 /* Transmit min pkt size */ -#define PAREG 0x4e0 /* Count of transmit peak attempts */ -#define DCNT 0x4f0 /* Transmit defer timer */ -#define NCCNT 0x500 /* Transmit normal-collision counter */ -#define NTCNT 0x510 /* Transmit first-collision counter */ -#define EXCNT 0x520 /* Transmit excess-collision counter */ -#define LTCNT 0x530 /* Transmit late-collision counter */ -#define RSEED 0x540 /* Transmit random number seed */ -#define TXSM 0x550 /* Transmit state machine */ - -/* receive control */ -#define RXRST 0x620 /* receive reset */ -# define RxResetValue 0x0000 -#define RXCFG 0x630 /* receive configuration control */ -# define RxMACEnable 0x0001 /* receiver overall enable */ -# define RxCFGReserved 0x0004 -# define RxPadStripEnab 0x0020 /* enable pad byte stripping */ -# define RxPromiscEnable 0x0040 /* turn on promiscuous mode */ -# define RxNoErrCheck 0x0080 /* disable receive error checking */ -# define RxCRCNoStrip 0x0100 /* disable auto-CRC-stripping */ -# define RxRejectOwnPackets 0x0200 /* don't receive our own packets */ -# define RxGrpPromisck 0x0400 /* enable group promiscuous mode */ -# define RxHashFilterEnable 0x0800 /* enable hash filter */ -# define RxAddrFilterEnable 0x1000 /* enable address filter */ -#define RXMAX 0x640 /* Max receive packet size */ -#define RXMIN 0x650 /* Min receive packet size */ -#define MADD2 0x660 /* our enet address, high part */ -#define MADD1 0x670 /* our enet address, middle part */ -#define MADD0 0x680 /* our enet address, low part */ -#define FRCNT 0x690 /* receive frame counter */ -#define LECNT 0x6a0 /* Receive excess length error counter */ -#define AECNT 0x6b0 /* Receive misaligned error counter */ -#define FECNT 0x6c0 /* Receive CRC error counter */ -#define RXSM 0x6d0 /* Receive state machine */ -#define RXCV 0x6e0 /* Receive code violation */ - -#define BHASH3 0x700 /* multicast hash register */ -#define BHASH2 0x710 /* multicast hash register */ -#define BHASH1 0x720 /* multicast hash register */ -#define BHASH0 0x730 /* multicast hash register */ - -#define AFR2 0x740 /* address filtering setup? */ -#define AFR1 0x750 /* address filtering setup? */ -#define AFR0 0x760 /* address filtering setup? */ -#define AFCR 0x770 /* address filter compare register? */ -# define EnableAllCompares 0x0fff - -/* bits in XIFC */ diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c deleted file mode 100644 index 537a4b2e202..00000000000 --- a/drivers/net/cs89x0.c +++ /dev/null @@ -1,1913 +0,0 @@ -/* cs89x0.c: A Crystal Semiconductor (Now Cirrus Logic) CS89[02]0 - * driver for linux. - */ - -/* - Written 1996 by Russell Nelson, with reference to skeleton.c - written 1993-1994 by Donald Becker. - - This software may be used and distributed according to the terms - of the GNU General Public License, incorporated herein by reference. - - The author may be reached at nelson@crynwr.com, Crynwr - Software, 521 Pleasant Valley Rd., Potsdam, NY 13676 - - Changelog: - - Mike Cruse : mcruse@cti-ltd.com - : Changes for Linux 2.0 compatibility. - : Added dev_id parameter in net_interrupt(), - : request_irq() and free_irq(). Just NULL for now. - - Mike Cruse : Added MOD_INC_USE_COUNT and MOD_DEC_USE_COUNT macros - : in net_open() and net_close() so kerneld would know - : that the module is in use and wouldn't eject the - : driver prematurely. - - Mike Cruse : Rewrote init_module() and cleanup_module using 8390.c - : as an example. Disabled autoprobing in init_module(), - : not a good thing to do to other devices while Linux - : is running from all accounts. - - Russ Nelson : Jul 13 1998. Added RxOnly DMA support. - - Melody Lee : Aug 10 1999. Changes for Linux 2.2.5 compatibility. - : email: ethernet@crystal.cirrus.com - - Alan Cox : Removed 1.2 support, added 2.1 extra counters. - - Andrew Morton : Kernel 2.3.48 - : Handle kmalloc() failures - : Other resource allocation fixes - : Add SMP locks - : Integrate Russ Nelson's ALLOW_DMA functionality back in. - : If ALLOW_DMA is true, make DMA runtime selectable - : Folded in changes from Cirrus (Melody Lee - : ) - : Don't call netif_wake_queue() in net_send_packet() - : Fixed an out-of-mem bug in dma_rx() - : Updated Documentation/networking/cs89x0.txt - - Andrew Morton : Kernel 2.3.99-pre1 - : Use skb_reserve to longword align IP header (two places) - : Remove a delay loop from dma_rx() - : Replace '100' with HZ - : Clean up a couple of skb API abuses - : Added 'cs89x0_dma=N' kernel boot option - : Correctly initialise lp->lock in non-module compile - - Andrew Morton : Kernel 2.3.99-pre4-1 - : MOD_INC/DEC race fix (see - : http://www.uwsg.indiana.edu/hypermail/linux/kernel/0003.3/1532.html) - - Andrew Morton : Kernel 2.4.0-test7-pre2 - : Enhanced EEPROM support to cover more devices, - : abstracted IRQ mapping to support CONFIG_ARCH_CLPS7500 arch - : (Jason Gunthorpe ) - - Andrew Morton : Kernel 2.4.0-test11-pre4 - : Use dev->name in request_*() (Andrey Panin) - : Fix an error-path memleak in init_module() - : Preserve return value from request_irq() - : Fix type of `media' module parm (Keith Owens) - : Use SET_MODULE_OWNER() - : Tidied up strange request_irq() abuse in net_open(). - - Andrew Morton : Kernel 2.4.3-pre1 - : Request correct number of pages for DMA (Hugh Dickens) - : Select PP_ChipID _after_ unregister_netdev in cleanup_module() - : because unregister_netdev() calls get_stats. - : Make `version[]' __initdata - : Uninlined the read/write reg/word functions. - - Oskar Schirmer : oskar@scara.com - : HiCO.SH4 (superh) support added (irq#1, cs89x0_media=) - - Deepak Saxena : dsaxena@plexity.net - : Intel IXDP2x01 (XScale ixp2x00 NPU) platform support - - Dmitry Pervushin : dpervushin@ru.mvista.com - : PNX010X platform support - - Deepak Saxena : dsaxena@plexity.net - : Intel IXDP2351 platform support - - Dmitry Pervushin : dpervushin@ru.mvista.com - : PNX010X platform support - - Domenico Andreoli : cavokz@gmail.com - : QQ2440 platform support - -*/ - -/* Always include 'config.h' first in case the user wants to turn on - or override something. */ -#include - -/* - * Set this to zero to disable DMA code - * - * Note that even if DMA is turned off we still support the 'dma' and 'use_dma' - * module options so we don't break any startup scripts. - */ -#ifndef CONFIG_ISA_DMA_API -#define ALLOW_DMA 0 -#else -#define ALLOW_DMA 1 -#endif - -/* - * Set this to zero to remove all the debug statements via - * dead code elimination - */ -#define DEBUGGING 1 - -/* - Sources: - - Crynwr packet driver epktisa. - - Crystal Semiconductor data sheets. - -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#if ALLOW_DMA -#include -#endif - -#include "cs89x0.h" - -static char version[] __initdata = -"cs89x0.c: v2.4.3-pre1 Russell Nelson , Andrew Morton\n"; - -#define DRV_NAME "cs89x0" - -/* First, a few definitions that the brave might change. - A zero-terminated list of I/O addresses to be probed. Some special flags.. - Addr & 1 = Read back the address port, look for signature and reset - the page window before probing - Addr & 3 = Reset the page window and probe - The CLPS eval board has the Cirrus chip at 0x80090300, in ARM IO space, - but it is possible that a Cirrus board could be plugged into the ISA - slots. */ -/* The cs8900 has 4 IRQ pins, software selectable. cs8900_irq_map maps - them to system IRQ numbers. This mapping is card specific and is set to - the configuration of the Cirrus Eval board for this chip. */ -#if defined(CONFIG_MACH_IXDP2351) -static unsigned int netcard_portlist[] __used __initdata = {IXDP2351_VIRT_CS8900_BASE, 0}; -static unsigned int cs8900_irq_map[] = {IRQ_IXDP2351_CS8900, 0, 0, 0}; -#elif defined(CONFIG_ARCH_IXDP2X01) -static unsigned int netcard_portlist[] __used __initdata = {IXDP2X01_CS8900_VIRT_BASE, 0}; -static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0}; -#elif defined(CONFIG_MACH_QQ2440) -#include -static unsigned int netcard_portlist[] __used __initdata = { QQ2440_CS8900_VIRT_BASE + 0x300, 0 }; -static unsigned int cs8900_irq_map[] = { QQ2440_CS8900_IRQ, 0, 0, 0 }; -#elif defined(CONFIG_MACH_MX31ADS) -#include -static unsigned int netcard_portlist[] __used __initdata = { - PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300, 0 -}; -static unsigned cs8900_irq_map[] = {EXPIO_INT_ENET_INT, 0, 0, 0}; -#else -static unsigned int netcard_portlist[] __used __initdata = - { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; -static unsigned int cs8900_irq_map[] = {10,11,12,5}; -#endif - -#if DEBUGGING -static unsigned int net_debug = DEBUGGING; -#else -#define net_debug 0 /* gcc will remove all the debug code for us */ -#endif - -/* The number of low I/O ports used by the ethercard. */ -#define NETCARD_IO_EXTENT 16 - -/* we allow the user to override various values normally set in the EEPROM */ -#define FORCE_RJ45 0x0001 /* pick one of these three */ -#define FORCE_AUI 0x0002 -#define FORCE_BNC 0x0004 - -#define FORCE_AUTO 0x0010 /* pick one of these three */ -#define FORCE_HALF 0x0020 -#define FORCE_FULL 0x0030 - -/* Information that need to be kept for each board. */ -struct net_local { - int chip_type; /* one of: CS8900, CS8920, CS8920M */ - char chip_revision; /* revision letter of the chip ('A'...) */ - int send_cmd; /* the proper send command: TX_NOW, TX_AFTER_381, or TX_AFTER_ALL */ - int auto_neg_cnf; /* auto-negotiation word from EEPROM */ - int adapter_cnf; /* adapter configuration from EEPROM */ - int isa_config; /* ISA configuration from EEPROM */ - int irq_map; /* IRQ map from EEPROM */ - int rx_mode; /* what mode are we in? 0, RX_MULTCAST_ACCEPT, or RX_ALL_ACCEPT */ - int curr_rx_cfg; /* a copy of PP_RxCFG */ - int linectl; /* either 0 or LOW_RX_SQUELCH, depending on configuration. */ - int send_underrun; /* keep track of how many underruns in a row we get */ - int force; /* force various values; see FORCE* above. */ - spinlock_t lock; -#if ALLOW_DMA - int use_dma; /* Flag: we're using dma */ - int dma; /* DMA channel */ - int dmasize; /* 16 or 64 */ - unsigned char *dma_buff; /* points to the beginning of the buffer */ - unsigned char *end_dma_buff; /* points to the end of the buffer */ - unsigned char *rx_dma_ptr; /* points to the next packet */ -#endif -}; - -/* Index to functions, as function prototypes. */ - -static int cs89x0_probe1(struct net_device *dev, int ioaddr, int modular); -static int net_open(struct net_device *dev); -static netdev_tx_t net_send_packet(struct sk_buff *skb, struct net_device *dev); -static irqreturn_t net_interrupt(int irq, void *dev_id); -static void set_multicast_list(struct net_device *dev); -static void net_timeout(struct net_device *dev); -static void net_rx(struct net_device *dev); -static int net_close(struct net_device *dev); -static struct net_device_stats *net_get_stats(struct net_device *dev); -static void reset_chip(struct net_device *dev); -static int get_eeprom_data(struct net_device *dev, int off, int len, int *buffer); -static int get_eeprom_cksum(int off, int len, int *buffer); -static int set_mac_address(struct net_device *dev, void *addr); -static void count_rx_errors(int status, struct net_device *dev); -#ifdef CONFIG_NET_POLL_CONTROLLER -static void net_poll_controller(struct net_device *dev); -#endif -#if ALLOW_DMA -static void get_dma_channel(struct net_device *dev); -static void release_dma_buff(struct net_local *lp); -#endif - -/* Example routines you must write ;->. */ -#define tx_done(dev) 1 - -/* - * Permit 'cs89x0_dma=N' in the kernel boot environment - */ -#if !defined(MODULE) && (ALLOW_DMA != 0) -static int g_cs89x0_dma; - -static int __init dma_fn(char *str) -{ - g_cs89x0_dma = simple_strtol(str,NULL,0); - return 1; -} - -__setup("cs89x0_dma=", dma_fn); -#endif /* !defined(MODULE) && (ALLOW_DMA != 0) */ - -#ifndef MODULE -static int g_cs89x0_media__force; - -static int __init media_fn(char *str) -{ - if (!strcmp(str, "rj45")) g_cs89x0_media__force = FORCE_RJ45; - else if (!strcmp(str, "aui")) g_cs89x0_media__force = FORCE_AUI; - else if (!strcmp(str, "bnc")) g_cs89x0_media__force = FORCE_BNC; - return 1; -} - -__setup("cs89x0_media=", media_fn); - - -/* Check for a network adaptor of this type, and return '0' iff one exists. - If dev->base_addr == 0, probe all likely locations. - If dev->base_addr == 1, always return failure. - If dev->base_addr == 2, allocate space for the device and return success - (detachable devices only). - Return 0 on success. - */ - -struct net_device * __init cs89x0_probe(int unit) -{ - struct net_device *dev = alloc_etherdev(sizeof(struct net_local)); - unsigned *port; - int err = 0; - int irq; - int io; - - if (!dev) - return ERR_PTR(-ENODEV); - - sprintf(dev->name, "eth%d", unit); - netdev_boot_setup_check(dev); - io = dev->base_addr; - irq = dev->irq; - - if (net_debug) - printk("cs89x0:cs89x0_probe(0x%x)\n", io); - - if (io > 0x1ff) { /* Check a single specified location. */ - err = cs89x0_probe1(dev, io, 0); - } else if (io != 0) { /* Don't probe at all. */ - err = -ENXIO; - } else { - for (port = netcard_portlist; *port; port++) { - if (cs89x0_probe1(dev, *port, 0) == 0) - break; - dev->irq = irq; - } - if (!*port) - err = -ENODEV; - } - if (err) - goto out; - return dev; -out: - free_netdev(dev); - printk(KERN_WARNING "cs89x0: no cs8900 or cs8920 detected. Be sure to disable PnP with SETUP\n"); - return ERR_PTR(err); -} -#endif - -#if defined(CONFIG_MACH_IXDP2351) -static u16 -readword(unsigned long base_addr, int portno) -{ - return __raw_readw(base_addr + (portno << 1)); -} - -static void -writeword(unsigned long base_addr, int portno, u16 value) -{ - __raw_writew(value, base_addr + (portno << 1)); -} -#elif defined(CONFIG_ARCH_IXDP2X01) -static u16 -readword(unsigned long base_addr, int portno) -{ - return __raw_readl(base_addr + (portno << 1)); -} - -static void -writeword(unsigned long base_addr, int portno, u16 value) -{ - __raw_writel(value, base_addr + (portno << 1)); -} -#else -static u16 -readword(unsigned long base_addr, int portno) -{ - return inw(base_addr + portno); -} - -static void -writeword(unsigned long base_addr, int portno, u16 value) -{ - outw(value, base_addr + portno); -} -#endif - -static void -readwords(unsigned long base_addr, int portno, void *buf, int length) -{ - u8 *buf8 = (u8 *)buf; - - do { - u16 tmp16; - - tmp16 = readword(base_addr, portno); - *buf8++ = (u8)tmp16; - *buf8++ = (u8)(tmp16 >> 8); - } while (--length); -} - -static void -writewords(unsigned long base_addr, int portno, void *buf, int length) -{ - u8 *buf8 = (u8 *)buf; - - do { - u16 tmp16; - - tmp16 = *buf8++; - tmp16 |= (*buf8++) << 8; - writeword(base_addr, portno, tmp16); - } while (--length); -} - -static u16 -readreg(struct net_device *dev, u16 regno) -{ - writeword(dev->base_addr, ADD_PORT, regno); - return readword(dev->base_addr, DATA_PORT); -} - -static void -writereg(struct net_device *dev, u16 regno, u16 value) -{ - writeword(dev->base_addr, ADD_PORT, regno); - writeword(dev->base_addr, DATA_PORT, value); -} - -static int __init -wait_eeprom_ready(struct net_device *dev) -{ - int timeout = jiffies; - /* check to see if the EEPROM is ready, a timeout is used - - just in case EEPROM is ready when SI_BUSY in the - PP_SelfST is clear */ - while(readreg(dev, PP_SelfST) & SI_BUSY) - if (jiffies - timeout >= 40) - return -1; - return 0; -} - -static int __init -get_eeprom_data(struct net_device *dev, int off, int len, int *buffer) -{ - int i; - - if (net_debug > 3) printk("EEPROM data from %x for %x:\n",off,len); - for (i = 0; i < len; i++) { - if (wait_eeprom_ready(dev) < 0) return -1; - /* Now send the EEPROM read command and EEPROM location to read */ - writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD); - if (wait_eeprom_ready(dev) < 0) return -1; - buffer[i] = readreg(dev, PP_EEData); - if (net_debug > 3) printk("%04x ", buffer[i]); - } - if (net_debug > 3) printk("\n"); - return 0; -} - -static int __init -get_eeprom_cksum(int off, int len, int *buffer) -{ - int i, cksum; - - cksum = 0; - for (i = 0; i < len; i++) - cksum += buffer[i]; - cksum &= 0xffff; - if (cksum == 0) - return 0; - return -1; -} - -#ifdef CONFIG_NET_POLL_CONTROLLER -/* - * Polling receive - used by netconsole and other diagnostic tools - * to allow network i/o with interrupts disabled. - */ -static void net_poll_controller(struct net_device *dev) -{ - disable_irq(dev->irq); - net_interrupt(dev->irq, dev); - enable_irq(dev->irq); -} -#endif - -static const struct net_device_ops net_ops = { - .ndo_open = net_open, - .ndo_stop = net_close, - .ndo_tx_timeout = net_timeout, - .ndo_start_xmit = net_send_packet, - .ndo_get_stats = net_get_stats, - .ndo_set_multicast_list = set_multicast_list, - .ndo_set_mac_address = set_mac_address, -#ifdef CONFIG_NET_POLL_CONTROLLER - .ndo_poll_controller = net_poll_controller, -#endif - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, -}; - -/* This is the real probe routine. Linux has a history of friendly device - probes on the ISA bus. A good device probes avoids doing writes, and - verifies that the correct device exists and functions. - Return 0 on success. - */ - -static int __init -cs89x0_probe1(struct net_device *dev, int ioaddr, int modular) -{ - struct net_local *lp = netdev_priv(dev); - static unsigned version_printed; - int i; - int tmp; - unsigned rev_type = 0; - int eeprom_buff[CHKSUM_LEN]; - int retval; - - /* Initialize the device structure. */ - if (!modular) { - memset(lp, 0, sizeof(*lp)); - spin_lock_init(&lp->lock); -#ifndef MODULE -#if ALLOW_DMA - if (g_cs89x0_dma) { - lp->use_dma = 1; - lp->dma = g_cs89x0_dma; - lp->dmasize = 16; /* Could make this an option... */ - } -#endif - lp->force = g_cs89x0_media__force; -#endif - -#if defined(CONFIG_MACH_QQ2440) - lp->force |= FORCE_RJ45 | FORCE_FULL; -#endif - } - - /* Grab the region so we can find another board if autoIRQ fails. */ - /* WTF is going on here? */ - if (!request_region(ioaddr & ~3, NETCARD_IO_EXTENT, DRV_NAME)) { - printk(KERN_ERR "%s: request_region(0x%x, 0x%x) failed\n", - DRV_NAME, ioaddr, NETCARD_IO_EXTENT); - retval = -EBUSY; - goto out1; - } - - /* if they give us an odd I/O address, then do ONE write to - the address port, to get it back to address zero, where we - expect to find the EISA signature word. An IO with a base of 0x3 - will skip the test for the ADD_PORT. */ - if (ioaddr & 1) { - if (net_debug > 1) - printk(KERN_INFO "%s: odd ioaddr 0x%x\n", dev->name, ioaddr); - if ((ioaddr & 2) != 2) - if ((readword(ioaddr & ~3, ADD_PORT) & ADD_MASK) != ADD_SIG) { - printk(KERN_ERR "%s: bad signature 0x%x\n", - dev->name, readword(ioaddr & ~3, ADD_PORT)); - retval = -ENODEV; - goto out2; - } - } - - ioaddr &= ~3; - printk(KERN_DEBUG "PP_addr at %x[%x]: 0x%x\n", - ioaddr, ADD_PORT, readword(ioaddr, ADD_PORT)); - writeword(ioaddr, ADD_PORT, PP_ChipID); - - tmp = readword(ioaddr, DATA_PORT); - if (tmp != CHIP_EISA_ID_SIG) { - printk(KERN_DEBUG "%s: incorrect signature at %x[%x]: 0x%x!=" - CHIP_EISA_ID_SIG_STR "\n", - dev->name, ioaddr, DATA_PORT, tmp); - retval = -ENODEV; - goto out2; - } - - /* Fill in the 'dev' fields. */ - dev->base_addr = ioaddr; - - /* get the chip type */ - rev_type = readreg(dev, PRODUCT_ID_ADD); - lp->chip_type = rev_type &~ REVISON_BITS; - lp->chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A'; - - /* Check the chip type and revision in order to set the correct send command - CS8920 revision C and CS8900 revision F can use the faster send. */ - lp->send_cmd = TX_AFTER_381; - if (lp->chip_type == CS8900 && lp->chip_revision >= 'F') - lp->send_cmd = TX_NOW; - if (lp->chip_type != CS8900 && lp->chip_revision >= 'C') - lp->send_cmd = TX_NOW; - - if (net_debug && version_printed++ == 0) - printk(version); - - printk(KERN_INFO "%s: cs89%c0%s rev %c found at %#3lx ", - dev->name, - lp->chip_type==CS8900?'0':'2', - lp->chip_type==CS8920M?"M":"", - lp->chip_revision, - dev->base_addr); - - reset_chip(dev); - - /* Here we read the current configuration of the chip. If there - is no Extended EEPROM then the idea is to not disturb the chip - configuration, it should have been correctly setup by automatic - EEPROM read on reset. So, if the chip says it read the EEPROM - the driver will always do *something* instead of complain that - adapter_cnf is 0. */ - - - if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) == - (EEPROM_OK|EEPROM_PRESENT)) { - /* Load the MAC. */ - for (i=0; i < ETH_ALEN/2; i++) { - unsigned int Addr; - Addr = readreg(dev, PP_IA+i*2); - dev->dev_addr[i*2] = Addr & 0xFF; - dev->dev_addr[i*2+1] = Addr >> 8; - } - - /* Load the Adapter Configuration. - Note: Barring any more specific information from some - other source (ie EEPROM+Schematics), we would not know - how to operate a 10Base2 interface on the AUI port. - However, since we do read the status of HCB1 and use - settings that always result in calls to control_dc_dc(dev,0) - a BNC interface should work if the enable pin - (dc/dc converter) is on HCB1. It will be called AUI - however. */ - - lp->adapter_cnf = 0; - i = readreg(dev, PP_LineCTL); - /* Preserve the setting of the HCB1 pin. */ - if ((i & (HCB1 | HCB1_ENBL)) == (HCB1 | HCB1_ENBL)) - lp->adapter_cnf |= A_CNF_DC_DC_POLARITY; - /* Save the sqelch bit */ - if ((i & LOW_RX_SQUELCH) == LOW_RX_SQUELCH) - lp->adapter_cnf |= A_CNF_EXTND_10B_2 | A_CNF_LOW_RX_SQUELCH; - /* Check if the card is in 10Base-t only mode */ - if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == 0) - lp->adapter_cnf |= A_CNF_10B_T | A_CNF_MEDIA_10B_T; - /* Check if the card is in AUI only mode */ - if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == AUI_ONLY) - lp->adapter_cnf |= A_CNF_AUI | A_CNF_MEDIA_AUI; - /* Check if the card is in Auto mode. */ - if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == AUTO_AUI_10BASET) - lp->adapter_cnf |= A_CNF_AUI | A_CNF_10B_T | - A_CNF_MEDIA_AUI | A_CNF_MEDIA_10B_T | A_CNF_MEDIA_AUTO; - - if (net_debug > 1) - printk(KERN_INFO "%s: PP_LineCTL=0x%x, adapter_cnf=0x%x\n", - dev->name, i, lp->adapter_cnf); - - /* IRQ. Other chips already probe, see below. */ - if (lp->chip_type == CS8900) - lp->isa_config = readreg(dev, PP_CS8900_ISAINT) & INT_NO_MASK; - - printk( "[Cirrus EEPROM] "); - } - - printk("\n"); - - /* First check to see if an EEPROM is attached. */ - - if ((readreg(dev, PP_SelfST) & EEPROM_PRESENT) == 0) - printk(KERN_WARNING "cs89x0: No EEPROM, relying on command line....\n"); - else if (get_eeprom_data(dev, START_EEPROM_DATA,CHKSUM_LEN,eeprom_buff) < 0) { - printk(KERN_WARNING "\ncs89x0: EEPROM read failed, relying on command line.\n"); - } else if (get_eeprom_cksum(START_EEPROM_DATA,CHKSUM_LEN,eeprom_buff) < 0) { - /* Check if the chip was able to read its own configuration starting - at 0 in the EEPROM*/ - if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) != - (EEPROM_OK|EEPROM_PRESENT)) - printk(KERN_WARNING "cs89x0: Extended EEPROM checksum bad and no Cirrus EEPROM, relying on command line\n"); - - } else { - /* This reads an extended EEPROM that is not documented - in the CS8900 datasheet. */ - - /* get transmission control word but keep the autonegotiation bits */ - if (!lp->auto_neg_cnf) lp->auto_neg_cnf = eeprom_buff[AUTO_NEG_CNF_OFFSET/2]; - /* Store adapter configuration */ - if (!lp->adapter_cnf) lp->adapter_cnf = eeprom_buff[ADAPTER_CNF_OFFSET/2]; - /* Store ISA configuration */ - lp->isa_config = eeprom_buff[ISA_CNF_OFFSET/2]; - dev->mem_start = eeprom_buff[PACKET_PAGE_OFFSET/2] << 8; - - /* eeprom_buff has 32-bit ints, so we can't just memcpy it */ - /* store the initial memory base address */ - for (i = 0; i < ETH_ALEN/2; i++) { - dev->dev_addr[i*2] = eeprom_buff[i]; - dev->dev_addr[i*2+1] = eeprom_buff[i] >> 8; - } - if (net_debug > 1) - printk(KERN_DEBUG "%s: new adapter_cnf: 0x%x\n", - dev->name, lp->adapter_cnf); - } - - /* allow them to force multiple transceivers. If they force multiple, autosense */ - { - int count = 0; - if (lp->force & FORCE_RJ45) {lp->adapter_cnf |= A_CNF_10B_T; count++; } - if (lp->force & FORCE_AUI) {lp->adapter_cnf |= A_CNF_AUI; count++; } - if (lp->force & FORCE_BNC) {lp->adapter_cnf |= A_CNF_10B_2; count++; } - if (count > 1) {lp->adapter_cnf |= A_CNF_MEDIA_AUTO; } - else if (lp->force & FORCE_RJ45){lp->adapter_cnf |= A_CNF_MEDIA_10B_T; } - else if (lp->force & FORCE_AUI) {lp->adapter_cnf |= A_CNF_MEDIA_AUI; } - else if (lp->force & FORCE_BNC) {lp->adapter_cnf |= A_CNF_MEDIA_10B_2; } - } - - if (net_debug > 1) - printk(KERN_DEBUG "%s: after force 0x%x, adapter_cnf=0x%x\n", - dev->name, lp->force, lp->adapter_cnf); - - /* FIXME: We don't let you set dc-dc polarity or low RX squelch from the command line: add it here */ - - /* FIXME: We don't let you set the IMM bit from the command line: add it to lp->auto_neg_cnf here */ - - /* FIXME: we don't set the Ethernet address on the command line. Use - ifconfig IFACE hw ether AABBCCDDEEFF */ - - printk(KERN_INFO "cs89x0 media %s%s%s", - (lp->adapter_cnf & A_CNF_10B_T)?"RJ-45,":"", - (lp->adapter_cnf & A_CNF_AUI)?"AUI,":"", - (lp->adapter_cnf & A_CNF_10B_2)?"BNC,":""); - - lp->irq_map = 0xffff; - - /* If this is a CS8900 then no pnp soft */ - if (lp->chip_type != CS8900 && - /* Check if the ISA IRQ has been set */ - (i = readreg(dev, PP_CS8920_ISAINT) & 0xff, - (i != 0 && i < CS8920_NO_INTS))) { - if (!dev->irq) - dev->irq = i; - } else { - i = lp->isa_config & INT_NO_MASK; - if (lp->chip_type == CS8900) { -#ifdef CONFIG_CS89x0_NONISA_IRQ - i = cs8900_irq_map[0]; -#else - /* Translate the IRQ using the IRQ mapping table. */ - if (i >= ARRAY_SIZE(cs8900_irq_map)) - printk("\ncs89x0: invalid ISA interrupt number %d\n", i); - else - i = cs8900_irq_map[i]; - - lp->irq_map = CS8900_IRQ_MAP; /* fixed IRQ map for CS8900 */ - } else { - int irq_map_buff[IRQ_MAP_LEN/2]; - - if (get_eeprom_data(dev, IRQ_MAP_EEPROM_DATA, - IRQ_MAP_LEN/2, - irq_map_buff) >= 0) { - if ((irq_map_buff[0] & 0xff) == PNP_IRQ_FRMT) - lp->irq_map = (irq_map_buff[0]>>8) | (irq_map_buff[1] << 8); - } -#endif - } - if (!dev->irq) - dev->irq = i; - } - - printk(" IRQ %d", dev->irq); - -#if ALLOW_DMA - if (lp->use_dma) { - get_dma_channel(dev); - printk(", DMA %d", dev->dma); - } - else -#endif - { - printk(", programmed I/O"); - } - - /* print the ethernet address. */ - printk(", MAC %pM", dev->dev_addr); - - dev->netdev_ops = &net_ops; - dev->watchdog_timeo = HZ; - - printk("\n"); - if (net_debug) - printk("cs89x0_probe1() successful\n"); - - retval = register_netdev(dev); - if (retval) - goto out3; - return 0; -out3: - writeword(dev->base_addr, ADD_PORT, PP_ChipID); -out2: - release_region(ioaddr & ~3, NETCARD_IO_EXTENT); -out1: - return retval; -} - - -/********************************* - * This page contains DMA routines -**********************************/ - -#if ALLOW_DMA - -#define dma_page_eq(ptr1, ptr2) ((long)(ptr1)>>17 == (long)(ptr2)>>17) - -static void -get_dma_channel(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - - if (lp->dma) { - dev->dma = lp->dma; - lp->isa_config |= ISA_RxDMA; - } else { - if ((lp->isa_config & ANY_ISA_DMA) == 0) - return; - dev->dma = lp->isa_config & DMA_NO_MASK; - if (lp->chip_type == CS8900) - dev->dma += 5; - if (dev->dma < 5 || dev->dma > 7) { - lp->isa_config &= ~ANY_ISA_DMA; - return; - } - } -} - -static void -write_dma(struct net_device *dev, int chip_type, int dma) -{ - struct net_local *lp = netdev_priv(dev); - if ((lp->isa_config & ANY_ISA_DMA) == 0) - return; - if (chip_type == CS8900) { - writereg(dev, PP_CS8900_ISADMA, dma-5); - } else { - writereg(dev, PP_CS8920_ISADMA, dma); - } -} - -static void -set_dma_cfg(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - - if (lp->use_dma) { - if ((lp->isa_config & ANY_ISA_DMA) == 0) { - if (net_debug > 3) - printk("set_dma_cfg(): no DMA\n"); - return; - } - if (lp->isa_config & ISA_RxDMA) { - lp->curr_rx_cfg |= RX_DMA_ONLY; - if (net_debug > 3) - printk("set_dma_cfg(): RX_DMA_ONLY\n"); - } else { - lp->curr_rx_cfg |= AUTO_RX_DMA; /* not that we support it... */ - if (net_debug > 3) - printk("set_dma_cfg(): AUTO_RX_DMA\n"); - } - } -} - -static int -dma_bufcfg(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - if (lp->use_dma) - return (lp->isa_config & ANY_ISA_DMA)? RX_DMA_ENBL : 0; - else - return 0; -} - -static int -dma_busctl(struct net_device *dev) -{ - int retval = 0; - struct net_local *lp = netdev_priv(dev); - if (lp->use_dma) { - if (lp->isa_config & ANY_ISA_DMA) - retval |= RESET_RX_DMA; /* Reset the DMA pointer */ - if (lp->isa_config & DMA_BURST) - retval |= DMA_BURST_MODE; /* Does ISA config specify DMA burst ? */ - if (lp->dmasize == 64) - retval |= RX_DMA_SIZE_64K; /* did they ask for 64K? */ - retval |= MEMORY_ON; /* we need memory enabled to use DMA. */ - } - return retval; -} - -static void -dma_rx(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - struct sk_buff *skb; - int status, length; - unsigned char *bp = lp->rx_dma_ptr; - - status = bp[0] + (bp[1]<<8); - length = bp[2] + (bp[3]<<8); - bp += 4; - if (net_debug > 5) { - printk( "%s: receiving DMA packet at %lx, status %x, length %x\n", - dev->name, (unsigned long)bp, status, length); - } - if ((status & RX_OK) == 0) { - count_rx_errors(status, dev); - goto skip_this_frame; - } - - /* Malloc up new buffer. */ - skb = dev_alloc_skb(length + 2); - if (skb == NULL) { - if (net_debug) /* I don't think we want to do this to a stressed system */ - printk("%s: Memory squeeze, dropping packet.\n", dev->name); - dev->stats.rx_dropped++; - - /* AKPM: advance bp to the next frame */ -skip_this_frame: - bp += (length + 3) & ~3; - if (bp >= lp->end_dma_buff) bp -= lp->dmasize*1024; - lp->rx_dma_ptr = bp; - return; - } - skb_reserve(skb, 2); /* longword align L3 header */ - - if (bp + length > lp->end_dma_buff) { - int semi_cnt = lp->end_dma_buff - bp; - memcpy(skb_put(skb,semi_cnt), bp, semi_cnt); - memcpy(skb_put(skb,length - semi_cnt), lp->dma_buff, - length - semi_cnt); - } else { - memcpy(skb_put(skb,length), bp, length); - } - bp += (length + 3) & ~3; - if (bp >= lp->end_dma_buff) bp -= lp->dmasize*1024; - lp->rx_dma_ptr = bp; - - if (net_debug > 3) { - printk( "%s: received %d byte DMA packet of type %x\n", - dev->name, length, - (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); - } - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - dev->stats.rx_packets++; - dev->stats.rx_bytes += length; -} - -#endif /* ALLOW_DMA */ - -static void __init reset_chip(struct net_device *dev) -{ -#if !defined(CONFIG_MACH_MX31ADS) -#if !defined(CS89x0_NONISA_IRQ) - struct net_local *lp = netdev_priv(dev); - int ioaddr = dev->base_addr; -#endif /* CS89x0_NONISA_IRQ */ - int reset_start_time; - - writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); - - /* wait 30 ms */ - msleep(30); - -#if !defined(CS89x0_NONISA_IRQ) - if (lp->chip_type != CS8900) { - /* Hardware problem requires PNP registers to be reconfigured after a reset */ - writeword(ioaddr, ADD_PORT, PP_CS8920_ISAINT); - outb(dev->irq, ioaddr + DATA_PORT); - outb(0, ioaddr + DATA_PORT + 1); - - writeword(ioaddr, ADD_PORT, PP_CS8920_ISAMemB); - outb((dev->mem_start >> 16) & 0xff, ioaddr + DATA_PORT); - outb((dev->mem_start >> 8) & 0xff, ioaddr + DATA_PORT + 1); - } -#endif /* CS89x0_NONISA_IRQ */ - - /* Wait until the chip is reset */ - reset_start_time = jiffies; - while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) - ; -#endif /* !CONFIG_MACH_MX31ADS */ -} - - -static void -control_dc_dc(struct net_device *dev, int on_not_off) -{ - struct net_local *lp = netdev_priv(dev); - unsigned int selfcontrol; - int timenow = jiffies; - /* control the DC to DC convertor in the SelfControl register. - Note: This is hooked up to a general purpose pin, might not - always be a DC to DC convertor. */ - - selfcontrol = HCB1_ENBL; /* Enable the HCB1 bit as an output */ - if (((lp->adapter_cnf & A_CNF_DC_DC_POLARITY) != 0) ^ on_not_off) - selfcontrol |= HCB1; - else - selfcontrol &= ~HCB1; - writereg(dev, PP_SelfCTL, selfcontrol); - - /* Wait for the DC/DC converter to power up - 500ms */ - while (jiffies - timenow < HZ) - ; -} - -#define DETECTED_NONE 0 -#define DETECTED_RJ45H 1 -#define DETECTED_RJ45F 2 -#define DETECTED_AUI 3 -#define DETECTED_BNC 4 - -static int -detect_tp(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - int timenow = jiffies; - int fdx; - - if (net_debug > 1) printk("%s: Attempting TP\n", dev->name); - - /* If connected to another full duplex capable 10-Base-T card the link pulses - seem to be lost when the auto detect bit in the LineCTL is set. - To overcome this the auto detect bit will be cleared whilst testing the - 10-Base-T interface. This would not be necessary for the sparrow chip but - is simpler to do it anyway. */ - writereg(dev, PP_LineCTL, lp->linectl &~ AUI_ONLY); - control_dc_dc(dev, 0); - - /* Delay for the hardware to work out if the TP cable is present - 150ms */ - for (timenow = jiffies; jiffies - timenow < 15; ) - ; - if ((readreg(dev, PP_LineST) & LINK_OK) == 0) - return DETECTED_NONE; - - if (lp->chip_type == CS8900) { - switch (lp->force & 0xf0) { -#if 0 - case FORCE_AUTO: - printk("%s: cs8900 doesn't autonegotiate\n",dev->name); - return DETECTED_NONE; -#endif - /* CS8900 doesn't support AUTO, change to HALF*/ - case FORCE_AUTO: - lp->force &= ~FORCE_AUTO; - lp->force |= FORCE_HALF; - break; - case FORCE_HALF: - break; - case FORCE_FULL: - writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900); - break; - } - fdx = readreg(dev, PP_TestCTL) & FDX_8900; - } else { - switch (lp->force & 0xf0) { - case FORCE_AUTO: - lp->auto_neg_cnf = AUTO_NEG_ENABLE; - break; - case FORCE_HALF: - lp->auto_neg_cnf = 0; - break; - case FORCE_FULL: - lp->auto_neg_cnf = RE_NEG_NOW | ALLOW_FDX; - break; - } - - writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK); - - if ((lp->auto_neg_cnf & AUTO_NEG_BITS) == AUTO_NEG_ENABLE) { - printk(KERN_INFO "%s: negotiating duplex...\n",dev->name); - while (readreg(dev, PP_AutoNegST) & AUTO_NEG_BUSY) { - if (jiffies - timenow > 4000) { - printk(KERN_ERR "**** Full / half duplex auto-negotiation timed out ****\n"); - break; - } - } - } - fdx = readreg(dev, PP_AutoNegST) & FDX_ACTIVE; - } - if (fdx) - return DETECTED_RJ45F; - else - return DETECTED_RJ45H; -} - -/* send a test packet - return true if carrier bits are ok */ -static int -send_test_pkt(struct net_device *dev) -{ - char test_packet[] = { 0,0,0,0,0,0, 0,0,0,0,0,0, - 0, 46, /* A 46 in network order */ - 0, 0, /* DSAP=0 & SSAP=0 fields */ - 0xf3, 0 /* Control (Test Req + P bit set) */ }; - long timenow = jiffies; - - writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON); - - memcpy(test_packet, dev->dev_addr, ETH_ALEN); - memcpy(test_packet+ETH_ALEN, dev->dev_addr, ETH_ALEN); - - writeword(dev->base_addr, TX_CMD_PORT, TX_AFTER_ALL); - writeword(dev->base_addr, TX_LEN_PORT, ETH_ZLEN); - - /* Test to see if the chip has allocated memory for the packet */ - while (jiffies - timenow < 5) - if (readreg(dev, PP_BusST) & READY_FOR_TX_NOW) - break; - if (jiffies - timenow >= 5) - return 0; /* this shouldn't happen */ - - /* Write the contents of the packet */ - writewords(dev->base_addr, TX_FRAME_PORT,test_packet,(ETH_ZLEN+1) >>1); - - if (net_debug > 1) printk("Sending test packet "); - /* wait a couple of jiffies for packet to be received */ - for (timenow = jiffies; jiffies - timenow < 3; ) - ; - if ((readreg(dev, PP_TxEvent) & TX_SEND_OK_BITS) == TX_OK) { - if (net_debug > 1) printk("succeeded\n"); - return 1; - } - if (net_debug > 1) printk("failed\n"); - return 0; -} - - -static int -detect_aui(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - - if (net_debug > 1) printk("%s: Attempting AUI\n", dev->name); - control_dc_dc(dev, 0); - - writereg(dev, PP_LineCTL, (lp->linectl &~ AUTO_AUI_10BASET) | AUI_ONLY); - - if (send_test_pkt(dev)) - return DETECTED_AUI; - else - return DETECTED_NONE; -} - -static int -detect_bnc(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - - if (net_debug > 1) printk("%s: Attempting BNC\n", dev->name); - control_dc_dc(dev, 1); - - writereg(dev, PP_LineCTL, (lp->linectl &~ AUTO_AUI_10BASET) | AUI_ONLY); - - if (send_test_pkt(dev)) - return DETECTED_BNC; - else - return DETECTED_NONE; -} - - -static void -write_irq(struct net_device *dev, int chip_type, int irq) -{ - int i; - - if (chip_type == CS8900) { - /* Search the mapping table for the corresponding IRQ pin. */ - for (i = 0; i != ARRAY_SIZE(cs8900_irq_map); i++) - if (cs8900_irq_map[i] == irq) - break; - /* Not found */ - if (i == ARRAY_SIZE(cs8900_irq_map)) - i = 3; - writereg(dev, PP_CS8900_ISAINT, i); - } else { - writereg(dev, PP_CS8920_ISAINT, irq); - } -} - -/* Open/initialize the board. This is called (in the current kernel) - sometime after booting when the 'ifconfig' program is run. - - This routine should set everything up anew at each open, even - registers that "should" only need to be set once at boot, so that - there is non-reboot way to recover if something goes wrong. - */ - -/* AKPM: do we need to do any locking here? */ - -static int -net_open(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - int result = 0; - int i; - int ret; - - if (dev->irq < 2) { - /* Allow interrupts to be generated by the chip */ -/* Cirrus' release had this: */ -#if 0 - writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ ); -#endif -/* And 2.3.47 had this: */ - writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON); - - for (i = 2; i < CS8920_NO_INTS; i++) { - if ((1 << i) & lp->irq_map) { - if (request_irq(i, net_interrupt, 0, dev->name, dev) == 0) { - dev->irq = i; - write_irq(dev, lp->chip_type, i); - /* writereg(dev, PP_BufCFG, GENERATE_SW_INTERRUPT); */ - break; - } - } - } - - if (i >= CS8920_NO_INTS) { - writereg(dev, PP_BusCTL, 0); /* disable interrupts. */ - printk(KERN_ERR "cs89x0: can't get an interrupt\n"); - ret = -EAGAIN; - goto bad_out; - } - } - else - { -#ifndef CONFIG_CS89x0_NONISA_IRQ - if (((1 << dev->irq) & lp->irq_map) == 0) { - printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", - dev->name, dev->irq, lp->irq_map); - ret = -EAGAIN; - goto bad_out; - } -#endif -/* FIXME: Cirrus' release had this: */ - writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ ); -/* And 2.3.47 had this: */ -#if 0 - writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON); -#endif - write_irq(dev, lp->chip_type, dev->irq); - ret = request_irq(dev->irq, net_interrupt, 0, dev->name, dev); - if (ret) { - printk(KERN_ERR "cs89x0: request_irq(%d) failed\n", dev->irq); - goto bad_out; - } - } - -#if ALLOW_DMA - if (lp->use_dma) { - if (lp->isa_config & ANY_ISA_DMA) { - unsigned long flags; - lp->dma_buff = (unsigned char *)__get_dma_pages(GFP_KERNEL, - get_order(lp->dmasize * 1024)); - - if (!lp->dma_buff) { - printk(KERN_ERR "%s: cannot get %dK memory for DMA\n", dev->name, lp->dmasize); - goto release_irq; - } - if (net_debug > 1) { - printk( "%s: dma %lx %lx\n", - dev->name, - (unsigned long)lp->dma_buff, - (unsigned long)isa_virt_to_bus(lp->dma_buff)); - } - if ((unsigned long) lp->dma_buff >= MAX_DMA_ADDRESS || - !dma_page_eq(lp->dma_buff, lp->dma_buff+lp->dmasize*1024-1)) { - printk(KERN_ERR "%s: not usable as DMA buffer\n", dev->name); - goto release_irq; - } - memset(lp->dma_buff, 0, lp->dmasize * 1024); /* Why? */ - if (request_dma(dev->dma, dev->name)) { - printk(KERN_ERR "%s: cannot get dma channel %d\n", dev->name, dev->dma); - goto release_irq; - } - write_dma(dev, lp->chip_type, dev->dma); - lp->rx_dma_ptr = lp->dma_buff; - lp->end_dma_buff = lp->dma_buff + lp->dmasize*1024; - spin_lock_irqsave(&lp->lock, flags); - disable_dma(dev->dma); - clear_dma_ff(dev->dma); - set_dma_mode(dev->dma, DMA_RX_MODE); /* auto_init as well */ - set_dma_addr(dev->dma, isa_virt_to_bus(lp->dma_buff)); - set_dma_count(dev->dma, lp->dmasize*1024); - enable_dma(dev->dma); - spin_unlock_irqrestore(&lp->lock, flags); - } - } -#endif /* ALLOW_DMA */ - - /* set the Ethernet address */ - for (i=0; i < ETH_ALEN/2; i++) - writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); - - /* while we're testing the interface, leave interrupts disabled */ - writereg(dev, PP_BusCTL, MEMORY_ON); - - /* Set the LineCTL quintuplet based on adapter configuration read from EEPROM */ - if ((lp->adapter_cnf & A_CNF_EXTND_10B_2) && (lp->adapter_cnf & A_CNF_LOW_RX_SQUELCH)) - lp->linectl = LOW_RX_SQUELCH; - else - lp->linectl = 0; - - /* check to make sure that they have the "right" hardware available */ - switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) { - case A_CNF_MEDIA_10B_T: result = lp->adapter_cnf & A_CNF_10B_T; break; - case A_CNF_MEDIA_AUI: result = lp->adapter_cnf & A_CNF_AUI; break; - case A_CNF_MEDIA_10B_2: result = lp->adapter_cnf & A_CNF_10B_2; break; - default: result = lp->adapter_cnf & (A_CNF_10B_T | A_CNF_AUI | A_CNF_10B_2); - } - if (!result) { - printk(KERN_ERR "%s: EEPROM is configured for unavailable media\n", dev->name); -release_dma: -#if ALLOW_DMA - free_dma(dev->dma); -release_irq: - release_dma_buff(lp); -#endif - writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) & ~(SERIAL_TX_ON | SERIAL_RX_ON)); - free_irq(dev->irq, dev); - ret = -EAGAIN; - goto bad_out; - } - - /* set the hardware to the configured choice */ - switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) { - case A_CNF_MEDIA_10B_T: - result = detect_tp(dev); - if (result==DETECTED_NONE) { - printk(KERN_WARNING "%s: 10Base-T (RJ-45) has no cable\n", dev->name); - if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ - result = DETECTED_RJ45H; /* Yes! I don't care if I see a link pulse */ - } - break; - case A_CNF_MEDIA_AUI: - result = detect_aui(dev); - if (result==DETECTED_NONE) { - printk(KERN_WARNING "%s: 10Base-5 (AUI) has no cable\n", dev->name); - if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ - result = DETECTED_AUI; /* Yes! I don't care if I see a carrrier */ - } - break; - case A_CNF_MEDIA_10B_2: - result = detect_bnc(dev); - if (result==DETECTED_NONE) { - printk(KERN_WARNING "%s: 10Base-2 (BNC) has no cable\n", dev->name); - if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ - result = DETECTED_BNC; /* Yes! I don't care if I can xmit a packet */ - } - break; - case A_CNF_MEDIA_AUTO: - writereg(dev, PP_LineCTL, lp->linectl | AUTO_AUI_10BASET); - if (lp->adapter_cnf & A_CNF_10B_T) - if ((result = detect_tp(dev)) != DETECTED_NONE) - break; - if (lp->adapter_cnf & A_CNF_AUI) - if ((result = detect_aui(dev)) != DETECTED_NONE) - break; - if (lp->adapter_cnf & A_CNF_10B_2) - if ((result = detect_bnc(dev)) != DETECTED_NONE) - break; - printk(KERN_ERR "%s: no media detected\n", dev->name); - goto release_dma; - } - switch(result) { - case DETECTED_NONE: - printk(KERN_ERR "%s: no network cable attached to configured media\n", dev->name); - goto release_dma; - case DETECTED_RJ45H: - printk(KERN_INFO "%s: using half-duplex 10Base-T (RJ-45)\n", dev->name); - break; - case DETECTED_RJ45F: - printk(KERN_INFO "%s: using full-duplex 10Base-T (RJ-45)\n", dev->name); - break; - case DETECTED_AUI: - printk(KERN_INFO "%s: using 10Base-5 (AUI)\n", dev->name); - break; - case DETECTED_BNC: - printk(KERN_INFO "%s: using 10Base-2 (BNC)\n", dev->name); - break; - } - - /* Turn on both receive and transmit operations */ - writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); - - /* Receive only error free packets addressed to this card */ - lp->rx_mode = 0; - writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); - - lp->curr_rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL; - - if (lp->isa_config & STREAM_TRANSFER) - lp->curr_rx_cfg |= RX_STREAM_ENBL; -#if ALLOW_DMA - set_dma_cfg(dev); -#endif - writereg(dev, PP_RxCFG, lp->curr_rx_cfg); - - writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | - TX_LATE_COL_ENBL | TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL); - - writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL | -#if ALLOW_DMA - dma_bufcfg(dev) | -#endif - TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL); - - /* now that we've got our act together, enable everything */ - writereg(dev, PP_BusCTL, ENABLE_IRQ - | (dev->mem_start?MEMORY_ON : 0) /* turn memory on */ -#if ALLOW_DMA - | dma_busctl(dev) -#endif - ); - netif_start_queue(dev); - if (net_debug > 1) - printk("cs89x0: net_open() succeeded\n"); - return 0; -bad_out: - return ret; -} - -static void net_timeout(struct net_device *dev) -{ - /* If we get here, some higher level has decided we are broken. - There should really be a "kick me" function call instead. */ - if (net_debug > 0) printk("%s: transmit timed out, %s?\n", dev->name, - tx_done(dev) ? "IRQ conflict ?" : "network cable problem"); - /* Try to restart the adaptor. */ - netif_wake_queue(dev); -} - -static netdev_tx_t net_send_packet(struct sk_buff *skb,struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - unsigned long flags; - - if (net_debug > 3) { - printk("%s: sent %d byte packet of type %x\n", - dev->name, skb->len, - (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); - } - - /* keep the upload from being interrupted, since we - ask the chip to start transmitting before the - whole packet has been completely uploaded. */ - - spin_lock_irqsave(&lp->lock, flags); - netif_stop_queue(dev); - - /* initiate a transmit sequence */ - writeword(dev->base_addr, TX_CMD_PORT, lp->send_cmd); - writeword(dev->base_addr, TX_LEN_PORT, skb->len); - - /* Test to see if the chip has allocated memory for the packet */ - if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { - /* - * Gasp! It hasn't. But that shouldn't happen since - * we're waiting for TxOk, so return 1 and requeue this packet. - */ - - spin_unlock_irqrestore(&lp->lock, flags); - if (net_debug) printk("cs89x0: Tx buffer not free!\n"); - return NETDEV_TX_BUSY; - } - /* Write the contents of the packet */ - writewords(dev->base_addr, TX_FRAME_PORT,skb->data,(skb->len+1) >>1); - spin_unlock_irqrestore(&lp->lock, flags); - dev->stats.tx_bytes += skb->len; - dev_kfree_skb (skb); - - /* - * We DO NOT call netif_wake_queue() here. - * We also DO NOT call netif_start_queue(). - * - * Either of these would cause another bottom half run through - * net_send_packet() before this packet has fully gone out. That causes - * us to hit the "Gasp!" above and the send is rescheduled. it runs like - * a dog. We just return and wait for the Tx completion interrupt handler - * to restart the netdevice layer - */ - - return NETDEV_TX_OK; -} - -/* The typical workload of the driver: - Handle the network interface interrupts. */ - -static irqreturn_t net_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct net_local *lp; - int ioaddr, status; - int handled = 0; - - ioaddr = dev->base_addr; - lp = netdev_priv(dev); - - /* we MUST read all the events out of the ISQ, otherwise we'll never - get interrupted again. As a consequence, we can't have any limit - on the number of times we loop in the interrupt handler. The - hardware guarantees that eventually we'll run out of events. Of - course, if you're on a slow machine, and packets are arriving - faster than you can read them off, you're screwed. Hasta la - vista, baby! */ - while ((status = readword(dev->base_addr, ISQ_PORT))) { - if (net_debug > 4)printk("%s: event=%04x\n", dev->name, status); - handled = 1; - switch(status & ISQ_EVENT_MASK) { - case ISQ_RECEIVER_EVENT: - /* Got a packet(s). */ - net_rx(dev); - break; - case ISQ_TRANSMITTER_EVENT: - dev->stats.tx_packets++; - netif_wake_queue(dev); /* Inform upper layers. */ - if ((status & ( TX_OK | - TX_LOST_CRS | - TX_SQE_ERROR | - TX_LATE_COL | - TX_16_COL)) != TX_OK) { - if ((status & TX_OK) == 0) - dev->stats.tx_errors++; - if (status & TX_LOST_CRS) - dev->stats.tx_carrier_errors++; - if (status & TX_SQE_ERROR) - dev->stats.tx_heartbeat_errors++; - if (status & TX_LATE_COL) - dev->stats.tx_window_errors++; - if (status & TX_16_COL) - dev->stats.tx_aborted_errors++; - } - break; - case ISQ_BUFFER_EVENT: - if (status & READY_FOR_TX) { - /* we tried to transmit a packet earlier, - but inexplicably ran out of buffers. - That shouldn't happen since we only ever - load one packet. Shrug. Do the right - thing anyway. */ - netif_wake_queue(dev); /* Inform upper layers. */ - } - if (status & TX_UNDERRUN) { - if (net_debug > 0) printk("%s: transmit underrun\n", dev->name); - lp->send_underrun++; - if (lp->send_underrun == 3) lp->send_cmd = TX_AFTER_381; - else if (lp->send_underrun == 6) lp->send_cmd = TX_AFTER_ALL; - /* transmit cycle is done, although - frame wasn't transmitted - this - avoids having to wait for the upper - layers to timeout on us, in the - event of a tx underrun */ - netif_wake_queue(dev); /* Inform upper layers. */ - } -#if ALLOW_DMA - if (lp->use_dma && (status & RX_DMA)) { - int count = readreg(dev, PP_DmaFrameCnt); - while(count) { - if (net_debug > 5) - printk("%s: receiving %d DMA frames\n", dev->name, count); - if (net_debug > 2 && count >1) - printk("%s: receiving %d DMA frames\n", dev->name, count); - dma_rx(dev); - if (--count == 0) - count = readreg(dev, PP_DmaFrameCnt); - if (net_debug > 2 && count > 0) - printk("%s: continuing with %d DMA frames\n", dev->name, count); - } - } -#endif - break; - case ISQ_RX_MISS_EVENT: - dev->stats.rx_missed_errors += (status >> 6); - break; - case ISQ_TX_COL_EVENT: - dev->stats.collisions += (status >> 6); - break; - } - } - return IRQ_RETVAL(handled); -} - -static void -count_rx_errors(int status, struct net_device *dev) -{ - dev->stats.rx_errors++; - if (status & RX_RUNT) - dev->stats.rx_length_errors++; - if (status & RX_EXTRA_DATA) - dev->stats.rx_length_errors++; - if ((status & RX_CRC_ERROR) && !(status & (RX_EXTRA_DATA|RX_RUNT))) - /* per str 172 */ - dev->stats.rx_crc_errors++; - if (status & RX_DRIBBLE) - dev->stats.rx_frame_errors++; -} - -/* We have a good packet(s), get it/them out of the buffers. */ -static void -net_rx(struct net_device *dev) -{ - struct sk_buff *skb; - int status, length; - - int ioaddr = dev->base_addr; - status = readword(ioaddr, RX_FRAME_PORT); - length = readword(ioaddr, RX_FRAME_PORT); - - if ((status & RX_OK) == 0) { - count_rx_errors(status, dev); - return; - } - - /* Malloc up new buffer. */ - skb = dev_alloc_skb(length + 2); - if (skb == NULL) { -#if 0 /* Again, this seems a cruel thing to do */ - printk(KERN_WARNING "%s: Memory squeeze, dropping packet.\n", dev->name); -#endif - dev->stats.rx_dropped++; - return; - } - skb_reserve(skb, 2); /* longword align L3 header */ - - readwords(ioaddr, RX_FRAME_PORT, skb_put(skb, length), length >> 1); - if (length & 1) - skb->data[length-1] = readword(ioaddr, RX_FRAME_PORT); - - if (net_debug > 3) { - printk( "%s: received %d byte packet of type %x\n", - dev->name, length, - (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); - } - - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - dev->stats.rx_packets++; - dev->stats.rx_bytes += length; -} - -#if ALLOW_DMA -static void release_dma_buff(struct net_local *lp) -{ - if (lp->dma_buff) { - free_pages((unsigned long)(lp->dma_buff), get_order(lp->dmasize * 1024)); - lp->dma_buff = NULL; - } -} -#endif - -/* The inverse routine to net_open(). */ -static int -net_close(struct net_device *dev) -{ -#if ALLOW_DMA - struct net_local *lp = netdev_priv(dev); -#endif - - netif_stop_queue(dev); - - writereg(dev, PP_RxCFG, 0); - writereg(dev, PP_TxCFG, 0); - writereg(dev, PP_BufCFG, 0); - writereg(dev, PP_BusCTL, 0); - - free_irq(dev->irq, dev); - -#if ALLOW_DMA - if (lp->use_dma && lp->dma) { - free_dma(dev->dma); - release_dma_buff(lp); - } -#endif - - /* Update the statistics here. */ - return 0; -} - -/* Get the current statistics. This may be called with the card open or - closed. */ -static struct net_device_stats * -net_get_stats(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - unsigned long flags; - - spin_lock_irqsave(&lp->lock, flags); - /* Update the statistics from the device registers. */ - dev->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6); - dev->stats.collisions += (readreg(dev, PP_TxCol) >> 6); - spin_unlock_irqrestore(&lp->lock, flags); - - return &dev->stats; -} - -static void set_multicast_list(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - unsigned long flags; - - spin_lock_irqsave(&lp->lock, flags); - if(dev->flags&IFF_PROMISC) - { - lp->rx_mode = RX_ALL_ACCEPT; - } - else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) - { - /* The multicast-accept list is initialized to accept-all, and we - rely on higher-level filtering for now. */ - lp->rx_mode = RX_MULTCAST_ACCEPT; - } - else - lp->rx_mode = 0; - - writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode); - - /* in promiscuous mode, we accept errored packets, so we have to enable interrupts on them also */ - writereg(dev, PP_RxCFG, lp->curr_rx_cfg | - (lp->rx_mode == RX_ALL_ACCEPT? (RX_CRC_ERROR_ENBL|RX_RUNT_ENBL|RX_EXTRA_DATA_ENBL) : 0)); - spin_unlock_irqrestore(&lp->lock, flags); -} - - -static int set_mac_address(struct net_device *dev, void *p) -{ - int i; - struct sockaddr *addr = p; - - if (netif_running(dev)) - return -EBUSY; - - memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); - - if (net_debug) - printk("%s: Setting MAC address to %pM.\n", - dev->name, dev->dev_addr); - - /* set the Ethernet address */ - for (i=0; i < ETH_ALEN/2; i++) - writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); - - return 0; -} - -#ifdef MODULE - -static struct net_device *dev_cs89x0; - -/* - * Support the 'debug' module parm even if we're compiled for non-debug to - * avoid breaking someone's startup scripts - */ - -static int io; -static int irq; -static int debug; -static char media[8]; -static int duplex=-1; - -static int use_dma; /* These generate unused var warnings if ALLOW_DMA = 0 */ -static int dma; -static int dmasize=16; /* or 64 */ - -module_param(io, int, 0); -module_param(irq, int, 0); -module_param(debug, int, 0); -module_param_string(media, media, sizeof(media), 0); -module_param(duplex, int, 0); -module_param(dma , int, 0); -module_param(dmasize , int, 0); -module_param(use_dma , int, 0); -MODULE_PARM_DESC(io, "cs89x0 I/O base address"); -MODULE_PARM_DESC(irq, "cs89x0 IRQ number"); -#if DEBUGGING -MODULE_PARM_DESC(debug, "cs89x0 debug level (0-6)"); -#else -MODULE_PARM_DESC(debug, "(ignored)"); -#endif -MODULE_PARM_DESC(media, "Set cs89x0 adapter(s) media type(s) (rj45,bnc,aui)"); -/* No other value than -1 for duplex seems to be currently interpreted */ -MODULE_PARM_DESC(duplex, "(ignored)"); -#if ALLOW_DMA -MODULE_PARM_DESC(dma , "cs89x0 ISA DMA channel; ignored if use_dma=0"); -MODULE_PARM_DESC(dmasize , "cs89x0 DMA size in kB (16,64); ignored if use_dma=0"); -MODULE_PARM_DESC(use_dma , "cs89x0 using DMA (0-1)"); -#else -MODULE_PARM_DESC(dma , "(ignored)"); -MODULE_PARM_DESC(dmasize , "(ignored)"); -MODULE_PARM_DESC(use_dma , "(ignored)"); -#endif - -MODULE_AUTHOR("Mike Cruse, Russwll Nelson , Andrew Morton"); -MODULE_LICENSE("GPL"); - - -/* -* media=t - specify media type - or media=2 - or media=aui - or medai=auto -* duplex=0 - specify forced half/full/autonegotiate duplex -* debug=# - debug level - - -* Default Chip Configuration: - * DMA Burst = enabled - * IOCHRDY Enabled = enabled - * UseSA = enabled - * CS8900 defaults to half-duplex if not specified on command-line - * CS8920 defaults to autoneg if not specified on command-line - * Use reset defaults for other config parameters - -* Assumptions: - * media type specified is supported (circuitry is present) - * if memory address is > 1MB, then required mem decode hw is present - * if 10B-2, then agent other than driver will enable DC/DC converter - (hw or software util) - - -*/ - -int __init init_module(void) -{ - struct net_device *dev = alloc_etherdev(sizeof(struct net_local)); - struct net_local *lp; - int ret = 0; - -#if DEBUGGING - net_debug = debug; -#else - debug = 0; -#endif - if (!dev) - return -ENOMEM; - - dev->irq = irq; - dev->base_addr = io; - lp = netdev_priv(dev); - -#if ALLOW_DMA - if (use_dma) { - lp->use_dma = use_dma; - lp->dma = dma; - lp->dmasize = dmasize; - } -#endif - - spin_lock_init(&lp->lock); - - /* boy, they'd better get these right */ - if (!strcmp(media, "rj45")) - lp->adapter_cnf = A_CNF_MEDIA_10B_T | A_CNF_10B_T; - else if (!strcmp(media, "aui")) - lp->adapter_cnf = A_CNF_MEDIA_AUI | A_CNF_AUI; - else if (!strcmp(media, "bnc")) - lp->adapter_cnf = A_CNF_MEDIA_10B_2 | A_CNF_10B_2; - else - lp->adapter_cnf = A_CNF_MEDIA_10B_T | A_CNF_10B_T; - - if (duplex==-1) - lp->auto_neg_cnf = AUTO_NEG_ENABLE; - - if (io == 0) { - printk(KERN_ERR "cs89x0.c: Module autoprobing not allowed.\n"); - printk(KERN_ERR "cs89x0.c: Append io=0xNNN\n"); - ret = -EPERM; - goto out; - } else if (io <= 0x1ff) { - ret = -ENXIO; - goto out; - } - -#if ALLOW_DMA - if (use_dma && dmasize != 16 && dmasize != 64) { - printk(KERN_ERR "cs89x0.c: dma size must be either 16K or 64K, not %dK\n", dmasize); - ret = -EPERM; - goto out; - } -#endif - ret = cs89x0_probe1(dev, io, 1); - if (ret) - goto out; - - dev_cs89x0 = dev; - return 0; -out: - free_netdev(dev); - return ret; -} - -void __exit -cleanup_module(void) -{ - unregister_netdev(dev_cs89x0); - writeword(dev_cs89x0->base_addr, ADD_PORT, PP_ChipID); - release_region(dev_cs89x0->base_addr, NETCARD_IO_EXTENT); - free_netdev(dev_cs89x0); -} -#endif /* MODULE */ - -/* - * Local variables: - * version-control: t - * kept-new-versions: 5 - * c-indent-level: 8 - * tab-width: 8 - * End: - * - */ diff --git a/drivers/net/cs89x0.h b/drivers/net/cs89x0.h deleted file mode 100644 index 91423b70bb4..00000000000 --- a/drivers/net/cs89x0.h +++ /dev/null @@ -1,465 +0,0 @@ -/* Copyright, 1988-1992, Russell Nelson, Crynwr Software - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, version 1. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - - -#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ - /* offset 2h -> Model/Product Number */ - /* offset 3h -> Chip Revision Number */ - -#define PP_ISAIOB 0x0020 /* IO base address */ -#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ -#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ -#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ -#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ -#define PP_ISASOF 0x0026 /* ISA DMA offset */ -#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ -#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ -#define PP_CS8900_ISAMemB 0x002C /* Memory base */ -#define PP_CS8920_ISAMemB 0x0348 /* */ - -#define PP_ISABootBase 0x0030 /* Boot Prom base */ -#define PP_ISABootMask 0x0034 /* Boot Prom Mask */ - -/* EEPROM data and command registers */ -#define PP_EECMD 0x0040 /* NVR Interface Command register */ -#define PP_EEData 0x0042 /* NVR Interface Data Register */ -#define PP_DebugReg 0x0044 /* Debug Register */ - -#define PP_RxCFG 0x0102 /* Rx Bus config */ -#define PP_RxCTL 0x0104 /* Receive Control Register */ -#define PP_TxCFG 0x0106 /* Transmit Config Register */ -#define PP_TxCMD 0x0108 /* Transmit Command Register */ -#define PP_BufCFG 0x010A /* Bus configuration Register */ -#define PP_LineCTL 0x0112 /* Line Config Register */ -#define PP_SelfCTL 0x0114 /* Self Command Register */ -#define PP_BusCTL 0x0116 /* ISA bus control Register */ -#define PP_TestCTL 0x0118 /* Test Register */ -#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ - -#define PP_ISQ 0x0120 /* Interrupt Status */ -#define PP_RxEvent 0x0124 /* Rx Event Register */ -#define PP_TxEvent 0x0128 /* Tx Event Register */ -#define PP_BufEvent 0x012C /* Bus Event Register */ -#define PP_RxMiss 0x0130 /* Receive Miss Count */ -#define PP_TxCol 0x0132 /* Transmit Collision Count */ -#define PP_LineST 0x0134 /* Line State Register */ -#define PP_SelfST 0x0136 /* Self State register */ -#define PP_BusST 0x0138 /* Bus Status */ -#define PP_TDR 0x013C /* Time Domain Reflectometry */ -#define PP_AutoNegST 0x013E /* Auto Neg Status */ -#define PP_TxCommand 0x0144 /* Tx Command */ -#define PP_TxLength 0x0146 /* Tx Length */ -#define PP_LAF 0x0150 /* Hash Table */ -#define PP_IA 0x0158 /* Physical Address Register */ - -#define PP_RxStatus 0x0400 /* Receive start of frame */ -#define PP_RxLength 0x0402 /* Receive Length of frame */ -#define PP_RxFrame 0x0404 /* Receive frame pointer */ -#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ - -/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */ -/* can be used as the default I/O base to access the PacketPage Area. */ -#define DEFAULTIOBASE 0x0300 -#define FIRST_IO 0x020C /* First I/O port to check */ -#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ -#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ -#define ADD_SIG 0x3000 /* Expected ID signature */ - -/* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */ -#ifdef CONFIG_MAC -#define LCSLOTBASE 0xfee00000 -#define MMIOBASE 0x40000 -#endif - -#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ -#define CHIP_EISA_ID_SIG_STR "0x630E" - -#ifdef IBMEIPKT -#define EISA_ID_SIG 0x4D24 /* IBM */ -#define PART_NO_SIG 0x1010 /* IBM */ -#define MONGOOSE_BIT 0x0000 /* IBM */ -#else -#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */ -#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */ -#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */ -#endif - -#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ - -/* Mask to find out the types of registers */ -#define REG_TYPE_MASK 0x001F - -/* Eeprom Commands */ -#define ERSE_WR_ENBL 0x00F0 -#define ERSE_WR_DISABLE 0x0000 - -/* Defines Control/Config register quintuplet numbers */ -#define RX_BUF_CFG 0x0003 -#define RX_CONTROL 0x0005 -#define TX_CFG 0x0007 -#define TX_COMMAND 0x0009 -#define BUF_CFG 0x000B -#define LINE_CONTROL 0x0013 -#define SELF_CONTROL 0x0015 -#define BUS_CONTROL 0x0017 -#define TEST_CONTROL 0x0019 - -/* Defines Status/Count registers quintuplet numbers */ -#define RX_EVENT 0x0004 -#define TX_EVENT 0x0008 -#define BUF_EVENT 0x000C -#define RX_MISS_COUNT 0x0010 -#define TX_COL_COUNT 0x0012 -#define LINE_STATUS 0x0014 -#define SELF_STATUS 0x0016 -#define BUS_STATUS 0x0018 -#define TDR 0x001C - -/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */ -#define SKIP_1 0x0040 -#define RX_STREAM_ENBL 0x0080 -#define RX_OK_ENBL 0x0100 -#define RX_DMA_ONLY 0x0200 -#define AUTO_RX_DMA 0x0400 -#define BUFFER_CRC 0x0800 -#define RX_CRC_ERROR_ENBL 0x1000 -#define RX_RUNT_ENBL 0x2000 -#define RX_EXTRA_DATA_ENBL 0x4000 - -/* PP_RxCTL - Receive Control bit definition - Read/write */ -#define RX_IA_HASH_ACCEPT 0x0040 -#define RX_PROM_ACCEPT 0x0080 -#define RX_OK_ACCEPT 0x0100 -#define RX_MULTCAST_ACCEPT 0x0200 -#define RX_IA_ACCEPT 0x0400 -#define RX_BROADCAST_ACCEPT 0x0800 -#define RX_BAD_CRC_ACCEPT 0x1000 -#define RX_RUNT_ACCEPT 0x2000 -#define RX_EXTRA_DATA_ACCEPT 0x4000 -#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) -/* Default receive mode - individually addressed, broadcast, and error free */ -#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) - -/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */ -#define TX_LOST_CRS_ENBL 0x0040 -#define TX_SQE_ERROR_ENBL 0x0080 -#define TX_OK_ENBL 0x0100 -#define TX_LATE_COL_ENBL 0x0200 -#define TX_JBR_ENBL 0x0400 -#define TX_ANY_COL_ENBL 0x0800 -#define TX_16_COL_ENBL 0x8000 - -/* PP_TxCMD - Transmit Command bit definition - Read-only */ -#define TX_START_4_BYTES 0x0000 -#define TX_START_64_BYTES 0x0040 -#define TX_START_128_BYTES 0x0080 -#define TX_START_ALL_BYTES 0x00C0 -#define TX_FORCE 0x0100 -#define TX_ONE_COL 0x0200 -#define TX_TWO_PART_DEFF_DISABLE 0x0400 -#define TX_NO_CRC 0x1000 -#define TX_RUNT 0x2000 - -/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */ -#define GENERATE_SW_INTERRUPT 0x0040 -#define RX_DMA_ENBL 0x0080 -#define READY_FOR_TX_ENBL 0x0100 -#define TX_UNDERRUN_ENBL 0x0200 -#define RX_MISS_ENBL 0x0400 -#define RX_128_BYTE_ENBL 0x0800 -#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 -#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 -#define RX_DEST_MATCH_ENBL 0x8000 - -/* PP_LineCTL - Line Control bit definition - Read/write */ -#define SERIAL_RX_ON 0x0040 -#define SERIAL_TX_ON 0x0080 -#define AUI_ONLY 0x0100 -#define AUTO_AUI_10BASET 0x0200 -#define MODIFIED_BACKOFF 0x0800 -#define NO_AUTO_POLARITY 0x1000 -#define TWO_PART_DEFDIS 0x2000 -#define LOW_RX_SQUELCH 0x4000 - -/* PP_SelfCTL - Software Self Control bit definition - Read/write */ -#define POWER_ON_RESET 0x0040 -#define SW_STOP 0x0100 -#define SLEEP_ON 0x0200 -#define AUTO_WAKEUP 0x0400 -#define HCB0_ENBL 0x1000 -#define HCB1_ENBL 0x2000 -#define HCB0 0x4000 -#define HCB1 0x8000 - -/* PP_BusCTL - ISA Bus Control bit definition - Read/write */ -#define RESET_RX_DMA 0x0040 -#define MEMORY_ON 0x0400 -#define DMA_BURST_MODE 0x0800 -#define IO_CHANNEL_READY_ON 0x1000 -#define RX_DMA_SIZE_64K 0x2000 -#define ENABLE_IRQ 0x8000 - -/* PP_TestCTL - Test Control bit definition - Read/write */ -#define LINK_OFF 0x0080 -#define ENDEC_LOOPBACK 0x0200 -#define AUI_LOOPBACK 0x0400 -#define BACKOFF_OFF 0x0800 -#define FDX_8900 0x4000 -#define FAST_TEST 0x8000 - -/* PP_RxEvent - Receive Event Bit definition - Read-only */ -#define RX_IA_HASHED 0x0040 -#define RX_DRIBBLE 0x0080 -#define RX_OK 0x0100 -#define RX_HASHED 0x0200 -#define RX_IA 0x0400 -#define RX_BROADCAST 0x0800 -#define RX_CRC_ERROR 0x1000 -#define RX_RUNT 0x2000 -#define RX_EXTRA_DATA 0x4000 - -#define HASH_INDEX_MASK 0x0FC00 - -/* PP_TxEvent - Transmit Event Bit definition - Read-only */ -#define TX_LOST_CRS 0x0040 -#define TX_SQE_ERROR 0x0080 -#define TX_OK 0x0100 -#define TX_LATE_COL 0x0200 -#define TX_JBR 0x0400 -#define TX_16_COL 0x8000 -#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) -#define TX_COL_COUNT_MASK 0x7800 - -/* PP_BufEvent - Buffer Event Bit definition - Read-only */ -#define SW_INTERRUPT 0x0040 -#define RX_DMA 0x0080 -#define READY_FOR_TX 0x0100 -#define TX_UNDERRUN 0x0200 -#define RX_MISS 0x0400 -#define RX_128_BYTE 0x0800 -#define TX_COL_OVRFLW 0x1000 -#define RX_MISS_OVRFLW 0x2000 -#define RX_DEST_MATCH 0x8000 - -/* PP_LineST - Ethernet Line Status bit definition - Read-only */ -#define LINK_OK 0x0080 -#define AUI_ON 0x0100 -#define TENBASET_ON 0x0200 -#define POLARITY_OK 0x1000 -#define CRS_OK 0x4000 - -/* PP_SelfST - Chip Software Status bit definition */ -#define ACTIVE_33V 0x0040 -#define INIT_DONE 0x0080 -#define SI_BUSY 0x0100 -#define EEPROM_PRESENT 0x0200 -#define EEPROM_OK 0x0400 -#define EL_PRESENT 0x0800 -#define EE_SIZE_64 0x1000 - -/* PP_BusST - ISA Bus Status bit definition */ -#define TX_BID_ERROR 0x0080 -#define READY_FOR_TX_NOW 0x0100 - -/* PP_AutoNegCTL - Auto Negotiation Control bit definition */ -#define RE_NEG_NOW 0x0040 -#define ALLOW_FDX 0x0080 -#define AUTO_NEG_ENABLE 0x0100 -#define NLP_ENABLE 0x0200 -#define FORCE_FDX 0x8000 -#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) -#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) - -/* PP_AutoNegST - Auto Negotiation Status bit definition */ -#define AUTO_NEG_BUSY 0x0080 -#define FLP_LINK 0x0100 -#define FLP_LINK_GOOD 0x0800 -#define LINK_FAULT 0x1000 -#define HDX_ACTIVE 0x4000 -#define FDX_ACTIVE 0x8000 - -/* The following block defines the ISQ event types */ -#define ISQ_RECEIVER_EVENT 0x04 -#define ISQ_TRANSMITTER_EVENT 0x08 -#define ISQ_BUFFER_EVENT 0x0c -#define ISQ_RX_MISS_EVENT 0x10 -#define ISQ_TX_COL_EVENT 0x12 - -#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ -#define ISQ_HIST 16 /* small history buffer */ -#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ - -#define TXRXBUFSIZE 0x0600 -#define RXDMABUFSIZE 0x8000 -#define RXDMASIZE 0x4000 -#define TXRX_LENGTH_MASK 0x07FF - -/* rx options bits */ -#define RCV_WITH_RXON 1 /* Set SerRx ON */ -#define RCV_COUNTS 2 /* Use Framecnt1 */ -#define RCV_PONG 4 /* Pong respondent */ -#define RCV_DONG 8 /* Dong operation */ -#define RCV_POLLING 0x10 /* Poll RxEvent */ -#define RCV_ISQ 0x20 /* Use ISQ, int */ -#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ -#define RCV_DMA 0x200 /* Set RxDMA only */ -#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ -#define RCV_FIXED_DATA 0x800 /* Every frame same */ -#define RCV_IO 0x1000 /* Use ISA IO only */ -#define RCV_MEMORY 0x2000 /* Use ISA Memory */ - -#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ -#define PKT_START PP_TxFrame /* Start of packet RAM */ - -#define RX_FRAME_PORT 0x0000 -#define TX_FRAME_PORT RX_FRAME_PORT -#define TX_CMD_PORT 0x0004 -#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */ -#define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ -#define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */ -#define TX_LEN_PORT 0x0006 -#define ISQ_PORT 0x0008 -#define ADD_PORT 0x000A -#define DATA_PORT 0x000C - -#define EEPROM_WRITE_EN 0x00F0 -#define EEPROM_WRITE_DIS 0x0000 -#define EEPROM_WRITE_CMD 0x0100 -#define EEPROM_READ_CMD 0x0200 - -/* Receive Header */ -/* Description of header of each packet in receive area of memory */ -#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ -#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ -#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ -#define RBUF_LEN_HI 3 /* Length of received data - high byte */ -#define RBUF_HEAD_LEN 4 /* Length of this header */ - -#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ -#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ - -/* for bios scan */ -/* */ -#ifdef CSDEBUG -/* use these values for debugging bios scan */ -#define BIOS_START_SEG 0x00000 -#define BIOS_OFFSET_INC 0x0010 -#else -#define BIOS_START_SEG 0x0c000 -#define BIOS_OFFSET_INC 0x0200 -#endif - -#define BIOS_LAST_OFFSET 0x0fc00 - -/* Byte offsets into the EEPROM configuration buffer */ -#define ISA_CNF_OFFSET 0x6 -#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ -#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ - - /* the assumption here is that the bits in the eeprom are generally */ - /* in the same position as those in the autonegctl register. */ - /* Of course the IMM bit is not in that register so it must be */ - /* masked out */ -#define EE_FORCE_FDX 0x8000 -#define EE_NLP_ENABLE 0x0200 -#define EE_AUTO_NEG_ENABLE 0x0100 -#define EE_ALLOW_FDX 0x0080 -#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) - -#define IMM_BIT 0x0040 /* ignore missing media */ - -#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) -#define A_CNF_10B_T 0x0001 -#define A_CNF_AUI 0x0002 -#define A_CNF_10B_2 0x0004 -#define A_CNF_MEDIA_TYPE 0x0070 -#define A_CNF_MEDIA_AUTO 0x0070 -#define A_CNF_MEDIA_10B_T 0x0020 -#define A_CNF_MEDIA_AUI 0x0040 -#define A_CNF_MEDIA_10B_2 0x0010 -#define A_CNF_DC_DC_POLARITY 0x0080 -#define A_CNF_NO_AUTO_POLARITY 0x2000 -#define A_CNF_LOW_RX_SQUELCH 0x4000 -#define A_CNF_EXTND_10B_2 0x8000 - -#define PACKET_PAGE_OFFSET 0x8 - -/* Bit definitions for the ISA configuration word from the EEPROM */ -#define INT_NO_MASK 0x000F -#define DMA_NO_MASK 0x0070 -#define ISA_DMA_SIZE 0x0200 -#define ISA_AUTO_RxDMA 0x0400 -#define ISA_RxDMA 0x0800 -#define DMA_BURST 0x1000 -#define STREAM_TRANSFER 0x2000 -#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) - -/* DMA controller registers */ -#define DMA_BASE 0x00 /* DMA controller base */ -#define DMA_BASE_2 0x0C0 /* DMA controller base */ - -#define DMA_STAT 0x0D0 /* DMA controller status register */ -#define DMA_MASK 0x0D4 /* DMA controller mask register */ -#define DMA_MODE 0x0D6 /* DMA controller mode register */ -#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ - -/* DMA data */ -#define DMA_DISABLE 0x04 /* Disable channel n */ -#define DMA_ENABLE 0x00 /* Enable channel n */ -/* Demand transfers, incr. address, auto init, writes, ch. n */ -#define DMA_RX_MODE 0x14 -/* Demand transfers, incr. address, auto init, reads, ch. n */ -#define DMA_TX_MODE 0x18 - -#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ - -#define CS8900 0x0000 -#define CS8920 0x4000 -#define CS8920M 0x6000 -#define REVISON_BITS 0x1F00 -#define EEVER_NUMBER 0x12 -#define CHKSUM_LEN 0x14 -#define CHKSUM_VAL 0x0000 -#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ -#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ -#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ -#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ -#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ - -#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ - -#define PNP_ADD_PORT 0x0279 -#define PNP_WRITE_PORT 0x0A79 - -#define GET_PNP_ISA_STRUCT 0x40 -#define PNP_ISA_STRUCT_LEN 0x06 -#define PNP_CSN_CNT_OFF 0x01 -#define PNP_RD_PORT_OFF 0x02 -#define PNP_FUNCTION_OK 0x00 -#define PNP_WAKE 0x03 -#define PNP_RSRC_DATA 0x04 -#define PNP_RSRC_READY 0x01 -#define PNP_STATUS 0x05 -#define PNP_ACTIVATE 0x30 -#define PNP_CNF_IO_H 0x60 -#define PNP_CNF_IO_L 0x61 -#define PNP_CNF_INT 0x70 -#define PNP_CNF_DMA 0x74 -#define PNP_CNF_MEM 0x48 - -#define BIT0 1 -#define BIT15 0x8000 - diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index c38e9026fe0..c3c415d853b 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -14,6 +14,7 @@ if ETHERNET source "drivers/net/ethernet/3com/Kconfig" source "drivers/net/ethernet/8390/Kconfig" source "drivers/net/ethernet/amd/Kconfig" +source "drivers/net/ethernet/apple/Kconfig" source "drivers/net/ethernet/broadcom/Kconfig" source "drivers/net/ethernet/brocade/Kconfig" source "drivers/net/ethernet/chelsio/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 75d7a0280c5..b67b88d5afd 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_NET_VENDOR_3COM) += 3com/ obj-$(CONFIG_NET_VENDOR_8390) += 8390/ obj-$(CONFIG_NET_VENDOR_AMD) += amd/ +obj-$(CONFIG_NET_VENDOR_APPLE) += apple/ obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/ obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/ obj-$(CONFIG_NET_VENDOR_CHELSIO) += chelsio/ diff --git a/drivers/net/ethernet/apple/Kconfig b/drivers/net/ethernet/apple/Kconfig new file mode 100644 index 00000000000..fc796bc353d --- /dev/null +++ b/drivers/net/ethernet/apple/Kconfig @@ -0,0 +1,96 @@ +# +# Apple device configuration +# + +config NET_VENDOR_APPLE + bool "Apple devices" + depends on (PPC_PMAC && PPC32) || MAC || ISA || EISA || MACH_IXDP2351 \ + || ARCH_IXDP2X01 || MACH_MX31ADS || MACH_QQ2440 + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y + and read the Ethernet-HOWTO, available from + . + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about IBM devices. If you say Y, you will be asked for + your specific card in the following questions. + +if NET_VENDOR_APPLE + +config MACE + tristate "MACE (Power Mac ethernet) support" + depends on PPC_PMAC && PPC32 + select CRC32 + ---help--- + Power Macintoshes and clones with Ethernet built-in on the + motherboard will usually use a MACE (Medium Access Control for + Ethernet) interface. Say Y to include support for the MACE chip. + + To compile this driver as a module, choose M here: the module + will be called mace. + +config MACE_AAUI_PORT + bool "Use AAUI port instead of TP by default" + depends on MACE + ---help--- + Some Apple machines (notably the Apple Network Server) which use the + MACE ethernet chip have an Apple AUI port (small 15-pin connector), + instead of an 8-pin RJ45 connector for twisted-pair ethernet. Say + Y here if you have such a machine. If unsure, say N. + The driver will default to AAUI on ANS anyway, and if you use it as + a module, you can provide the port_aaui=0|1 to force the driver. + +config BMAC + tristate "BMAC (G3 ethernet) support" + depends on PPC_PMAC && PPC32 + select CRC32 + ---help--- + Say Y for support of BMAC Ethernet interfaces. These are used on G3 + computers. + + To compile this driver as a module, choose M here: the module + will be called bmac. + +config MAC89x0 + tristate "Macintosh CS89x0 based ethernet cards" + depends on MAC + ---help--- + Support for CS89x0 chipset based Ethernet cards. If you have a + Nubus or LC-PDS network (Ethernet) card of this type, say Y and + read the Ethernet-HOWTO, available from + . + + To compile this driver as a module, choose M here. This module will + be called mac89x0. + +config MACMACE + bool "Macintosh (AV) onboard MACE ethernet" + depends on MAC + select CRC32 + ---help--- + Support for the onboard AMD 79C940 MACE Ethernet controller used in + the 660AV and 840AV Macintosh. If you have one of these Macintoshes + say Y and read the Ethernet-HOWTO, available from + . + +config CS89x0 + tristate "CS89x0 support" + depends on (ISA || EISA || MACH_IXDP2351 \ + || ARCH_IXDP2X01 || MACH_MX31ADS || MACH_QQ2440) + ---help--- + Support for CS89x0 chipset based Ethernet cards. If you have a + network (Ethernet) card of this type, say Y and read the + Ethernet-HOWTO, available from + as well as + . + + To compile this driver as a module, choose M here. The module + will be called cs89x0. + +config CS89x0_NONISA_IRQ + def_bool y + depends on CS89x0 != n + depends on MACH_IXDP2351 || ARCH_IXDP2X01 || MACH_MX31ADS || MACH_QQ2440 + +endif # NET_VENDOR_APPLE diff --git a/drivers/net/ethernet/apple/Makefile b/drivers/net/ethernet/apple/Makefile new file mode 100644 index 00000000000..9d300864461 --- /dev/null +++ b/drivers/net/ethernet/apple/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the Apple network device drivers. +# + +obj-$(CONFIG_MACE) += mace.o +obj-$(CONFIG_BMAC) += bmac.o +obj-$(CONFIG_MAC89x0) += mac89x0.o +obj-$(CONFIG_CS89x0) += cs89x0.o +obj-$(CONFIG_MACMACE) += macmace.o diff --git a/drivers/net/ethernet/apple/bmac.c b/drivers/net/ethernet/apple/bmac.c new file mode 100644 index 00000000000..45e45e8d3d6 --- /dev/null +++ b/drivers/net/ethernet/apple/bmac.c @@ -0,0 +1,1685 @@ +/* + * Network device driver for the BMAC ethernet controller on + * Apple Powermacs. Assumes it's under a DBDMA controller. + * + * Copyright (C) 1998 Randy Gobbel. + * + * May 1999, Al Viro: proper release of /proc/net/bmac entry, switched to + * dynamic procfs inode. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bmac.h" + +#define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1)))) +#define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1))) + +/* + * CRC polynomial - used in working out multicast filter bits. + */ +#define ENET_CRCPOLY 0x04c11db7 + +/* switch to use multicast code lifted from sunhme driver */ +#define SUNHME_MULTICAST + +#define N_RX_RING 64 +#define N_TX_RING 32 +#define MAX_TX_ACTIVE 1 +#define ETHERCRC 4 +#define ETHERMINPACKET 64 +#define ETHERMTU 1500 +#define RX_BUFLEN (ETHERMTU + 14 + ETHERCRC + 2) +#define TX_TIMEOUT HZ /* 1 second */ + +/* Bits in transmit DMA status */ +#define TX_DMA_ERR 0x80 + +#define XXDEBUG(args) + +struct bmac_data { + /* volatile struct bmac *bmac; */ + struct sk_buff_head *queue; + volatile struct dbdma_regs __iomem *tx_dma; + int tx_dma_intr; + volatile struct dbdma_regs __iomem *rx_dma; + int rx_dma_intr; + volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ + volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ + struct macio_dev *mdev; + int is_bmac_plus; + struct sk_buff *rx_bufs[N_RX_RING]; + int rx_fill; + int rx_empty; + struct sk_buff *tx_bufs[N_TX_RING]; + int tx_fill; + int tx_empty; + unsigned char tx_fullup; + struct timer_list tx_timeout; + int timeout_active; + int sleeping; + int opened; + unsigned short hash_use_count[64]; + unsigned short hash_table_mask[4]; + spinlock_t lock; +}; + +#if 0 /* Move that to ethtool */ + +typedef struct bmac_reg_entry { + char *name; + unsigned short reg_offset; +} bmac_reg_entry_t; + +#define N_REG_ENTRIES 31 + +static bmac_reg_entry_t reg_entries[N_REG_ENTRIES] = { + {"MEMADD", MEMADD}, + {"MEMDATAHI", MEMDATAHI}, + {"MEMDATALO", MEMDATALO}, + {"TXPNTR", TXPNTR}, + {"RXPNTR", RXPNTR}, + {"IPG1", IPG1}, + {"IPG2", IPG2}, + {"ALIMIT", ALIMIT}, + {"SLOT", SLOT}, + {"PALEN", PALEN}, + {"PAPAT", PAPAT}, + {"TXSFD", TXSFD}, + {"JAM", JAM}, + {"TXCFG", TXCFG}, + {"TXMAX", TXMAX}, + {"TXMIN", TXMIN}, + {"PAREG", PAREG}, + {"DCNT", DCNT}, + {"NCCNT", NCCNT}, + {"NTCNT", NTCNT}, + {"EXCNT", EXCNT}, + {"LTCNT", LTCNT}, + {"TXSM", TXSM}, + {"RXCFG", RXCFG}, + {"RXMAX", RXMAX}, + {"RXMIN", RXMIN}, + {"FRCNT", FRCNT}, + {"AECNT", AECNT}, + {"FECNT", FECNT}, + {"RXSM", RXSM}, + {"RXCV", RXCV} +}; + +#endif + +static unsigned char *bmac_emergency_rxbuf; + +/* + * Number of bytes of private data per BMAC: allow enough for + * the rx and tx dma commands plus a branch dma command each, + * and another 16 bytes to allow us to align the dma command + * buffers on a 16 byte boundary. + */ +#define PRIV_BYTES (sizeof(struct bmac_data) \ + + (N_RX_RING + N_TX_RING + 4) * sizeof(struct dbdma_cmd) \ + + sizeof(struct sk_buff_head)) + +static int bmac_open(struct net_device *dev); +static int bmac_close(struct net_device *dev); +static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev); +static void bmac_set_multicast(struct net_device *dev); +static void bmac_reset_and_enable(struct net_device *dev); +static void bmac_start_chip(struct net_device *dev); +static void bmac_init_chip(struct net_device *dev); +static void bmac_init_registers(struct net_device *dev); +static void bmac_enable_and_reset_chip(struct net_device *dev); +static int bmac_set_address(struct net_device *dev, void *addr); +static irqreturn_t bmac_misc_intr(int irq, void *dev_id); +static irqreturn_t bmac_txdma_intr(int irq, void *dev_id); +static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id); +static void bmac_set_timeout(struct net_device *dev); +static void bmac_tx_timeout(unsigned long data); +static int bmac_output(struct sk_buff *skb, struct net_device *dev); +static void bmac_start(struct net_device *dev); + +#define DBDMA_SET(x) ( ((x) | (x) << 16) ) +#define DBDMA_CLEAR(x) ( (x) << 16) + +static inline void +dbdma_st32(volatile __u32 __iomem *a, unsigned long x) +{ + __asm__ volatile( "stwbrx %0,0,%1" : : "r" (x), "r" (a) : "memory"); +} + +static inline unsigned long +dbdma_ld32(volatile __u32 __iomem *a) +{ + __u32 swap; + __asm__ volatile ("lwbrx %0,0,%1" : "=r" (swap) : "r" (a)); + return swap; +} + +static void +dbdma_continue(volatile struct dbdma_regs __iomem *dmap) +{ + dbdma_st32(&dmap->control, + DBDMA_SET(RUN|WAKE) | DBDMA_CLEAR(PAUSE|DEAD)); + eieio(); +} + +static void +dbdma_reset(volatile struct dbdma_regs __iomem *dmap) +{ + dbdma_st32(&dmap->control, + DBDMA_CLEAR(ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)); + eieio(); + while (dbdma_ld32(&dmap->status) & RUN) + eieio(); +} + +static void +dbdma_setcmd(volatile struct dbdma_cmd *cp, + unsigned short cmd, unsigned count, unsigned long addr, + unsigned long cmd_dep) +{ + out_le16(&cp->command, cmd); + out_le16(&cp->req_count, count); + out_le32(&cp->phy_addr, addr); + out_le32(&cp->cmd_dep, cmd_dep); + out_le16(&cp->xfer_status, 0); + out_le16(&cp->res_count, 0); +} + +static inline +void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data ) +{ + out_le16((void __iomem *)dev->base_addr + reg_offset, data); +} + + +static inline +unsigned short bmread(struct net_device *dev, unsigned long reg_offset ) +{ + return in_le16((void __iomem *)dev->base_addr + reg_offset); +} + +static void +bmac_enable_and_reset_chip(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + volatile struct dbdma_regs __iomem *td = bp->tx_dma; + + if (rd) + dbdma_reset(rd); + if (td) + dbdma_reset(td); + + pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 1); +} + +#define MIFDELAY udelay(10) + +static unsigned int +bmac_mif_readbits(struct net_device *dev, int nb) +{ + unsigned int val = 0; + + while (--nb >= 0) { + bmwrite(dev, MIFCSR, 0); + MIFDELAY; + if (bmread(dev, MIFCSR) & 8) + val |= 1 << nb; + bmwrite(dev, MIFCSR, 1); + MIFDELAY; + } + bmwrite(dev, MIFCSR, 0); + MIFDELAY; + bmwrite(dev, MIFCSR, 1); + MIFDELAY; + return val; +} + +static void +bmac_mif_writebits(struct net_device *dev, unsigned int val, int nb) +{ + int b; + + while (--nb >= 0) { + b = (val & (1 << nb))? 6: 4; + bmwrite(dev, MIFCSR, b); + MIFDELAY; + bmwrite(dev, MIFCSR, b|1); + MIFDELAY; + } +} + +static unsigned int +bmac_mif_read(struct net_device *dev, unsigned int addr) +{ + unsigned int val; + + bmwrite(dev, MIFCSR, 4); + MIFDELAY; + bmac_mif_writebits(dev, ~0U, 32); + bmac_mif_writebits(dev, 6, 4); + bmac_mif_writebits(dev, addr, 10); + bmwrite(dev, MIFCSR, 2); + MIFDELAY; + bmwrite(dev, MIFCSR, 1); + MIFDELAY; + val = bmac_mif_readbits(dev, 17); + bmwrite(dev, MIFCSR, 4); + MIFDELAY; + return val; +} + +static void +bmac_mif_write(struct net_device *dev, unsigned int addr, unsigned int val) +{ + bmwrite(dev, MIFCSR, 4); + MIFDELAY; + bmac_mif_writebits(dev, ~0U, 32); + bmac_mif_writebits(dev, 5, 4); + bmac_mif_writebits(dev, addr, 10); + bmac_mif_writebits(dev, 2, 2); + bmac_mif_writebits(dev, val, 16); + bmac_mif_writebits(dev, 3, 2); +} + +static void +bmac_init_registers(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + volatile unsigned short regValue; + unsigned short *pWord16; + int i; + + /* XXDEBUG(("bmac: enter init_registers\n")); */ + + bmwrite(dev, RXRST, RxResetValue); + bmwrite(dev, TXRST, TxResetBit); + + i = 100; + do { + --i; + udelay(10000); + regValue = bmread(dev, TXRST); /* wait for reset to clear..acknowledge */ + } while ((regValue & TxResetBit) && i > 0); + + if (!bp->is_bmac_plus) { + regValue = bmread(dev, XCVRIF); + regValue |= ClkBit | SerialMode | COLActiveLow; + bmwrite(dev, XCVRIF, regValue); + udelay(10000); + } + + bmwrite(dev, RSEED, (unsigned short)0x1968); + + regValue = bmread(dev, XIFC); + regValue |= TxOutputEnable; + bmwrite(dev, XIFC, regValue); + + bmread(dev, PAREG); + + /* set collision counters to 0 */ + bmwrite(dev, NCCNT, 0); + bmwrite(dev, NTCNT, 0); + bmwrite(dev, EXCNT, 0); + bmwrite(dev, LTCNT, 0); + + /* set rx counters to 0 */ + bmwrite(dev, FRCNT, 0); + bmwrite(dev, LECNT, 0); + bmwrite(dev, AECNT, 0); + bmwrite(dev, FECNT, 0); + bmwrite(dev, RXCV, 0); + + /* set tx fifo information */ + bmwrite(dev, TXTH, 4); /* 4 octets before tx starts */ + + bmwrite(dev, TXFIFOCSR, 0); /* first disable txFIFO */ + bmwrite(dev, TXFIFOCSR, TxFIFOEnable ); + + /* set rx fifo information */ + bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */ + bmwrite(dev, RXFIFOCSR, RxFIFOEnable ); + + //bmwrite(dev, TXCFG, TxMACEnable); /* TxNeverGiveUp maybe later */ + bmread(dev, STATUS); /* read it just to clear it */ + + /* zero out the chip Hash Filter registers */ + for (i=0; i<4; i++) bp->hash_table_mask[i] = 0; + bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */ + bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */ + bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */ + bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */ + + pWord16 = (unsigned short *)dev->dev_addr; + bmwrite(dev, MADD0, *pWord16++); + bmwrite(dev, MADD1, *pWord16++); + bmwrite(dev, MADD2, *pWord16); + + bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets); + + bmwrite(dev, INTDISABLE, EnableNormal); +} + +#if 0 +static void +bmac_disable_interrupts(struct net_device *dev) +{ + bmwrite(dev, INTDISABLE, DisableAll); +} + +static void +bmac_enable_interrupts(struct net_device *dev) +{ + bmwrite(dev, INTDISABLE, EnableNormal); +} +#endif + + +static void +bmac_start_chip(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + unsigned short oldConfig; + + /* enable rx dma channel */ + dbdma_continue(rd); + + oldConfig = bmread(dev, TXCFG); + bmwrite(dev, TXCFG, oldConfig | TxMACEnable ); + + /* turn on rx plus any other bits already on (promiscuous possibly) */ + oldConfig = bmread(dev, RXCFG); + bmwrite(dev, RXCFG, oldConfig | RxMACEnable ); + udelay(20000); +} + +static void +bmac_init_phy(struct net_device *dev) +{ + unsigned int addr; + struct bmac_data *bp = netdev_priv(dev); + + printk(KERN_DEBUG "phy registers:"); + for (addr = 0; addr < 32; ++addr) { + if ((addr & 7) == 0) + printk(KERN_DEBUG); + printk(KERN_CONT " %.4x", bmac_mif_read(dev, addr)); + } + printk(KERN_CONT "\n"); + + if (bp->is_bmac_plus) { + unsigned int capable, ctrl; + + ctrl = bmac_mif_read(dev, 0); + capable = ((bmac_mif_read(dev, 1) & 0xf800) >> 6) | 1; + if (bmac_mif_read(dev, 4) != capable || + (ctrl & 0x1000) == 0) { + bmac_mif_write(dev, 4, capable); + bmac_mif_write(dev, 0, 0x1200); + } else + bmac_mif_write(dev, 0, 0x1000); + } +} + +static void bmac_init_chip(struct net_device *dev) +{ + bmac_init_phy(dev); + bmac_init_registers(dev); +} + +#ifdef CONFIG_PM +static int bmac_suspend(struct macio_dev *mdev, pm_message_t state) +{ + struct net_device* dev = macio_get_drvdata(mdev); + struct bmac_data *bp = netdev_priv(dev); + unsigned long flags; + unsigned short config; + int i; + + netif_device_detach(dev); + /* prolly should wait for dma to finish & turn off the chip */ + spin_lock_irqsave(&bp->lock, flags); + if (bp->timeout_active) { + del_timer(&bp->tx_timeout); + bp->timeout_active = 0; + } + disable_irq(dev->irq); + disable_irq(bp->tx_dma_intr); + disable_irq(bp->rx_dma_intr); + bp->sleeping = 1; + spin_unlock_irqrestore(&bp->lock, flags); + if (bp->opened) { + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + volatile struct dbdma_regs __iomem *td = bp->tx_dma; + + config = bmread(dev, RXCFG); + bmwrite(dev, RXCFG, (config & ~RxMACEnable)); + config = bmread(dev, TXCFG); + bmwrite(dev, TXCFG, (config & ~TxMACEnable)); + bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */ + /* disable rx and tx dma */ + st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ + st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ + /* free some skb's */ + for (i=0; irx_bufs[i] != NULL) { + dev_kfree_skb(bp->rx_bufs[i]); + bp->rx_bufs[i] = NULL; + } + } + for (i = 0; itx_bufs[i] != NULL) { + dev_kfree_skb(bp->tx_bufs[i]); + bp->tx_bufs[i] = NULL; + } + } + } + pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); + return 0; +} + +static int bmac_resume(struct macio_dev *mdev) +{ + struct net_device* dev = macio_get_drvdata(mdev); + struct bmac_data *bp = netdev_priv(dev); + + /* see if this is enough */ + if (bp->opened) + bmac_reset_and_enable(dev); + + enable_irq(dev->irq); + enable_irq(bp->tx_dma_intr); + enable_irq(bp->rx_dma_intr); + netif_device_attach(dev); + + return 0; +} +#endif /* CONFIG_PM */ + +static int bmac_set_address(struct net_device *dev, void *addr) +{ + struct bmac_data *bp = netdev_priv(dev); + unsigned char *p = addr; + unsigned short *pWord16; + unsigned long flags; + int i; + + XXDEBUG(("bmac: enter set_address\n")); + spin_lock_irqsave(&bp->lock, flags); + + for (i = 0; i < 6; ++i) { + dev->dev_addr[i] = p[i]; + } + /* load up the hardware address */ + pWord16 = (unsigned short *)dev->dev_addr; + bmwrite(dev, MADD0, *pWord16++); + bmwrite(dev, MADD1, *pWord16++); + bmwrite(dev, MADD2, *pWord16); + + spin_unlock_irqrestore(&bp->lock, flags); + XXDEBUG(("bmac: exit set_address\n")); + return 0; +} + +static inline void bmac_set_timeout(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&bp->lock, flags); + if (bp->timeout_active) + del_timer(&bp->tx_timeout); + bp->tx_timeout.expires = jiffies + TX_TIMEOUT; + bp->tx_timeout.function = bmac_tx_timeout; + bp->tx_timeout.data = (unsigned long) dev; + add_timer(&bp->tx_timeout); + bp->timeout_active = 1; + spin_unlock_irqrestore(&bp->lock, flags); +} + +static void +bmac_construct_xmt(struct sk_buff *skb, volatile struct dbdma_cmd *cp) +{ + void *vaddr; + unsigned long baddr; + unsigned long len; + + len = skb->len; + vaddr = skb->data; + baddr = virt_to_bus(vaddr); + + dbdma_setcmd(cp, (OUTPUT_LAST | INTR_ALWAYS | WAIT_IFCLR), len, baddr, 0); +} + +static void +bmac_construct_rxbuff(struct sk_buff *skb, volatile struct dbdma_cmd *cp) +{ + unsigned char *addr = skb? skb->data: bmac_emergency_rxbuf; + + dbdma_setcmd(cp, (INPUT_LAST | INTR_ALWAYS), RX_BUFLEN, + virt_to_bus(addr), 0); +} + +static void +bmac_init_tx_ring(struct bmac_data *bp) +{ + volatile struct dbdma_regs __iomem *td = bp->tx_dma; + + memset((char *)bp->tx_cmds, 0, (N_TX_RING+1) * sizeof(struct dbdma_cmd)); + + bp->tx_empty = 0; + bp->tx_fill = 0; + bp->tx_fullup = 0; + + /* put a branch at the end of the tx command list */ + dbdma_setcmd(&bp->tx_cmds[N_TX_RING], + (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->tx_cmds)); + + /* reset tx dma */ + dbdma_reset(td); + out_le32(&td->wait_sel, 0x00200020); + out_le32(&td->cmdptr, virt_to_bus(bp->tx_cmds)); +} + +static int +bmac_init_rx_ring(struct bmac_data *bp) +{ + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + int i; + struct sk_buff *skb; + + /* initialize list of sk_buffs for receiving and set up recv dma */ + memset((char *)bp->rx_cmds, 0, + (N_RX_RING + 1) * sizeof(struct dbdma_cmd)); + for (i = 0; i < N_RX_RING; i++) { + if ((skb = bp->rx_bufs[i]) == NULL) { + bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2); + if (skb != NULL) + skb_reserve(skb, 2); + } + bmac_construct_rxbuff(skb, &bp->rx_cmds[i]); + } + + bp->rx_empty = 0; + bp->rx_fill = i; + + /* Put a branch back to the beginning of the receive command list */ + dbdma_setcmd(&bp->rx_cmds[N_RX_RING], + (DBDMA_NOP | BR_ALWAYS), 0, 0, virt_to_bus(bp->rx_cmds)); + + /* start rx dma */ + dbdma_reset(rd); + out_le32(&rd->cmdptr, virt_to_bus(bp->rx_cmds)); + + return 1; +} + + +static int bmac_transmit_packet(struct sk_buff *skb, struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *td = bp->tx_dma; + int i; + + /* see if there's a free slot in the tx ring */ + /* XXDEBUG(("bmac_xmit_start: empty=%d fill=%d\n", */ + /* bp->tx_empty, bp->tx_fill)); */ + i = bp->tx_fill + 1; + if (i >= N_TX_RING) + i = 0; + if (i == bp->tx_empty) { + netif_stop_queue(dev); + bp->tx_fullup = 1; + XXDEBUG(("bmac_transmit_packet: tx ring full\n")); + return -1; /* can't take it at the moment */ + } + + dbdma_setcmd(&bp->tx_cmds[i], DBDMA_STOP, 0, 0, 0); + + bmac_construct_xmt(skb, &bp->tx_cmds[bp->tx_fill]); + + bp->tx_bufs[bp->tx_fill] = skb; + bp->tx_fill = i; + + dev->stats.tx_bytes += skb->len; + + dbdma_continue(td); + + return 0; +} + +static int rxintcount; + +static irqreturn_t bmac_rxdma_intr(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + volatile struct dbdma_cmd *cp; + int i, nb, stat; + struct sk_buff *skb; + unsigned int residual; + int last; + unsigned long flags; + + spin_lock_irqsave(&bp->lock, flags); + + if (++rxintcount < 10) { + XXDEBUG(("bmac_rxdma_intr\n")); + } + + last = -1; + i = bp->rx_empty; + + while (1) { + cp = &bp->rx_cmds[i]; + stat = ld_le16(&cp->xfer_status); + residual = ld_le16(&cp->res_count); + if ((stat & ACTIVE) == 0) + break; + nb = RX_BUFLEN - residual - 2; + if (nb < (ETHERMINPACKET - ETHERCRC)) { + skb = NULL; + dev->stats.rx_length_errors++; + dev->stats.rx_errors++; + } else { + skb = bp->rx_bufs[i]; + bp->rx_bufs[i] = NULL; + } + if (skb != NULL) { + nb -= ETHERCRC; + skb_put(skb, nb); + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + ++dev->stats.rx_packets; + dev->stats.rx_bytes += nb; + } else { + ++dev->stats.rx_dropped; + } + if ((skb = bp->rx_bufs[i]) == NULL) { + bp->rx_bufs[i] = skb = dev_alloc_skb(RX_BUFLEN+2); + if (skb != NULL) + skb_reserve(bp->rx_bufs[i], 2); + } + bmac_construct_rxbuff(skb, &bp->rx_cmds[i]); + st_le16(&cp->res_count, 0); + st_le16(&cp->xfer_status, 0); + last = i; + if (++i >= N_RX_RING) i = 0; + } + + if (last != -1) { + bp->rx_fill = last; + bp->rx_empty = i; + } + + dbdma_continue(rd); + spin_unlock_irqrestore(&bp->lock, flags); + + if (rxintcount < 10) { + XXDEBUG(("bmac_rxdma_intr done\n")); + } + return IRQ_HANDLED; +} + +static int txintcount; + +static irqreturn_t bmac_txdma_intr(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_cmd *cp; + int stat; + unsigned long flags; + + spin_lock_irqsave(&bp->lock, flags); + + if (txintcount++ < 10) { + XXDEBUG(("bmac_txdma_intr\n")); + } + + /* del_timer(&bp->tx_timeout); */ + /* bp->timeout_active = 0; */ + + while (1) { + cp = &bp->tx_cmds[bp->tx_empty]; + stat = ld_le16(&cp->xfer_status); + if (txintcount < 10) { + XXDEBUG(("bmac_txdma_xfer_stat=%#0x\n", stat)); + } + if (!(stat & ACTIVE)) { + /* + * status field might not have been filled by DBDMA + */ + if (cp == bus_to_virt(in_le32(&bp->tx_dma->cmdptr))) + break; + } + + if (bp->tx_bufs[bp->tx_empty]) { + ++dev->stats.tx_packets; + dev_kfree_skb_irq(bp->tx_bufs[bp->tx_empty]); + } + bp->tx_bufs[bp->tx_empty] = NULL; + bp->tx_fullup = 0; + netif_wake_queue(dev); + if (++bp->tx_empty >= N_TX_RING) + bp->tx_empty = 0; + if (bp->tx_empty == bp->tx_fill) + break; + } + + spin_unlock_irqrestore(&bp->lock, flags); + + if (txintcount < 10) { + XXDEBUG(("bmac_txdma_intr done->bmac_start\n")); + } + + bmac_start(dev); + return IRQ_HANDLED; +} + +#ifndef SUNHME_MULTICAST +/* Real fast bit-reversal algorithm, 6-bit values */ +static int reverse6[64] = { + 0x0,0x20,0x10,0x30,0x8,0x28,0x18,0x38, + 0x4,0x24,0x14,0x34,0xc,0x2c,0x1c,0x3c, + 0x2,0x22,0x12,0x32,0xa,0x2a,0x1a,0x3a, + 0x6,0x26,0x16,0x36,0xe,0x2e,0x1e,0x3e, + 0x1,0x21,0x11,0x31,0x9,0x29,0x19,0x39, + 0x5,0x25,0x15,0x35,0xd,0x2d,0x1d,0x3d, + 0x3,0x23,0x13,0x33,0xb,0x2b,0x1b,0x3b, + 0x7,0x27,0x17,0x37,0xf,0x2f,0x1f,0x3f +}; + +static unsigned int +crc416(unsigned int curval, unsigned short nxtval) +{ + register unsigned int counter, cur = curval, next = nxtval; + register int high_crc_set, low_data_set; + + /* Swap bytes */ + next = ((next & 0x00FF) << 8) | (next >> 8); + + /* Compute bit-by-bit */ + for (counter = 0; counter < 16; ++counter) { + /* is high CRC bit set? */ + if ((cur & 0x80000000) == 0) high_crc_set = 0; + else high_crc_set = 1; + + cur = cur << 1; + + if ((next & 0x0001) == 0) low_data_set = 0; + else low_data_set = 1; + + next = next >> 1; + + /* do the XOR */ + if (high_crc_set ^ low_data_set) cur = cur ^ ENET_CRCPOLY; + } + return cur; +} + +static unsigned int +bmac_crc(unsigned short *address) +{ + unsigned int newcrc; + + XXDEBUG(("bmac_crc: addr=%#04x, %#04x, %#04x\n", *address, address[1], address[2])); + newcrc = crc416(0xffffffff, *address); /* address bits 47 - 32 */ + newcrc = crc416(newcrc, address[1]); /* address bits 31 - 16 */ + newcrc = crc416(newcrc, address[2]); /* address bits 15 - 0 */ + + return(newcrc); +} + +/* + * Add requested mcast addr to BMac's hash table filter. + * + */ + +static void +bmac_addhash(struct bmac_data *bp, unsigned char *addr) +{ + unsigned int crc; + unsigned short mask; + + if (!(*addr)) return; + crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */ + crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */ + if (bp->hash_use_count[crc]++) return; /* This bit is already set */ + mask = crc % 16; + mask = (unsigned char)1 << mask; + bp->hash_use_count[crc/16] |= mask; +} + +static void +bmac_removehash(struct bmac_data *bp, unsigned char *addr) +{ + unsigned int crc; + unsigned char mask; + + /* Now, delete the address from the filter copy, as indicated */ + crc = bmac_crc((unsigned short *)addr) & 0x3f; /* Big-endian alert! */ + crc = reverse6[crc]; /* Hyperfast bit-reversing algorithm */ + if (bp->hash_use_count[crc] == 0) return; /* That bit wasn't in use! */ + if (--bp->hash_use_count[crc]) return; /* That bit is still in use */ + mask = crc % 16; + mask = ((unsigned char)1 << mask) ^ 0xffff; /* To turn off bit */ + bp->hash_table_mask[crc/16] &= mask; +} + +/* + * Sync the adapter with the software copy of the multicast mask + * (logical address filter). + */ + +static void +bmac_rx_off(struct net_device *dev) +{ + unsigned short rx_cfg; + + rx_cfg = bmread(dev, RXCFG); + rx_cfg &= ~RxMACEnable; + bmwrite(dev, RXCFG, rx_cfg); + do { + rx_cfg = bmread(dev, RXCFG); + } while (rx_cfg & RxMACEnable); +} + +unsigned short +bmac_rx_on(struct net_device *dev, int hash_enable, int promisc_enable) +{ + unsigned short rx_cfg; + + rx_cfg = bmread(dev, RXCFG); + rx_cfg |= RxMACEnable; + if (hash_enable) rx_cfg |= RxHashFilterEnable; + else rx_cfg &= ~RxHashFilterEnable; + if (promisc_enable) rx_cfg |= RxPromiscEnable; + else rx_cfg &= ~RxPromiscEnable; + bmwrite(dev, RXRST, RxResetValue); + bmwrite(dev, RXFIFOCSR, 0); /* first disable rxFIFO */ + bmwrite(dev, RXFIFOCSR, RxFIFOEnable ); + bmwrite(dev, RXCFG, rx_cfg ); + return rx_cfg; +} + +static void +bmac_update_hash_table_mask(struct net_device *dev, struct bmac_data *bp) +{ + bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */ + bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */ + bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */ + bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */ +} + +#if 0 +static void +bmac_add_multi(struct net_device *dev, + struct bmac_data *bp, unsigned char *addr) +{ + /* XXDEBUG(("bmac: enter bmac_add_multi\n")); */ + bmac_addhash(bp, addr); + bmac_rx_off(dev); + bmac_update_hash_table_mask(dev, bp); + bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0); + /* XXDEBUG(("bmac: exit bmac_add_multi\n")); */ +} + +static void +bmac_remove_multi(struct net_device *dev, + struct bmac_data *bp, unsigned char *addr) +{ + bmac_removehash(bp, addr); + bmac_rx_off(dev); + bmac_update_hash_table_mask(dev, bp); + bmac_rx_on(dev, 1, (dev->flags & IFF_PROMISC)? 1 : 0); +} +#endif + +/* Set or clear the multicast filter for this adaptor. + num_addrs == -1 Promiscuous mode, receive all packets + num_addrs == 0 Normal mode, clear multicast list + num_addrs > 0 Multicast mode, receive normal and MC packets, and do + best-effort filtering. + */ +static void bmac_set_multicast(struct net_device *dev) +{ + struct netdev_hw_addr *ha; + struct bmac_data *bp = netdev_priv(dev); + int num_addrs = netdev_mc_count(dev); + unsigned short rx_cfg; + int i; + + if (bp->sleeping) + return; + + XXDEBUG(("bmac: enter bmac_set_multicast, n_addrs=%d\n", num_addrs)); + + if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { + for (i=0; i<4; i++) bp->hash_table_mask[i] = 0xffff; + bmac_update_hash_table_mask(dev, bp); + rx_cfg = bmac_rx_on(dev, 1, 0); + XXDEBUG(("bmac: all multi, rx_cfg=%#08x\n")); + } else if ((dev->flags & IFF_PROMISC) || (num_addrs < 0)) { + rx_cfg = bmread(dev, RXCFG); + rx_cfg |= RxPromiscEnable; + bmwrite(dev, RXCFG, rx_cfg); + rx_cfg = bmac_rx_on(dev, 0, 1); + XXDEBUG(("bmac: promisc mode enabled, rx_cfg=%#08x\n", rx_cfg)); + } else { + for (i=0; i<4; i++) bp->hash_table_mask[i] = 0; + for (i=0; i<64; i++) bp->hash_use_count[i] = 0; + if (num_addrs == 0) { + rx_cfg = bmac_rx_on(dev, 0, 0); + XXDEBUG(("bmac: multi disabled, rx_cfg=%#08x\n", rx_cfg)); + } else { + netdev_for_each_mc_addr(ha, dev) + bmac_addhash(bp, ha->addr); + bmac_update_hash_table_mask(dev, bp); + rx_cfg = bmac_rx_on(dev, 1, 0); + XXDEBUG(("bmac: multi enabled, rx_cfg=%#08x\n", rx_cfg)); + } + } + /* XXDEBUG(("bmac: exit bmac_set_multicast\n")); */ +} +#else /* ifdef SUNHME_MULTICAST */ + +/* The version of set_multicast below was lifted from sunhme.c */ + +static void bmac_set_multicast(struct net_device *dev) +{ + struct netdev_hw_addr *ha; + int i; + unsigned short rx_cfg; + u32 crc; + + if((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 64)) { + bmwrite(dev, BHASH0, 0xffff); + bmwrite(dev, BHASH1, 0xffff); + bmwrite(dev, BHASH2, 0xffff); + bmwrite(dev, BHASH3, 0xffff); + } else if(dev->flags & IFF_PROMISC) { + rx_cfg = bmread(dev, RXCFG); + rx_cfg |= RxPromiscEnable; + bmwrite(dev, RXCFG, rx_cfg); + } else { + u16 hash_table[4]; + + rx_cfg = bmread(dev, RXCFG); + rx_cfg &= ~RxPromiscEnable; + bmwrite(dev, RXCFG, rx_cfg); + + for(i = 0; i < 4; i++) hash_table[i] = 0; + + netdev_for_each_mc_addr(ha, dev) { + crc = ether_crc_le(6, ha->addr); + crc >>= 26; + hash_table[crc >> 4] |= 1 << (crc & 0xf); + } + bmwrite(dev, BHASH0, hash_table[0]); + bmwrite(dev, BHASH1, hash_table[1]); + bmwrite(dev, BHASH2, hash_table[2]); + bmwrite(dev, BHASH3, hash_table[3]); + } +} +#endif /* SUNHME_MULTICAST */ + +static int miscintcount; + +static irqreturn_t bmac_misc_intr(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + unsigned int status = bmread(dev, STATUS); + if (miscintcount++ < 10) { + XXDEBUG(("bmac_misc_intr\n")); + } + /* XXDEBUG(("bmac_misc_intr, status=%#08x\n", status)); */ + /* bmac_txdma_intr_inner(irq, dev_id); */ + /* if (status & FrameReceived) dev->stats.rx_dropped++; */ + if (status & RxErrorMask) dev->stats.rx_errors++; + if (status & RxCRCCntExp) dev->stats.rx_crc_errors++; + if (status & RxLenCntExp) dev->stats.rx_length_errors++; + if (status & RxOverFlow) dev->stats.rx_over_errors++; + if (status & RxAlignCntExp) dev->stats.rx_frame_errors++; + + /* if (status & FrameSent) dev->stats.tx_dropped++; */ + if (status & TxErrorMask) dev->stats.tx_errors++; + if (status & TxUnderrun) dev->stats.tx_fifo_errors++; + if (status & TxNormalCollExp) dev->stats.collisions++; + return IRQ_HANDLED; +} + +/* + * Procedure for reading EEPROM + */ +#define SROMAddressLength 5 +#define DataInOn 0x0008 +#define DataInOff 0x0000 +#define Clk 0x0002 +#define ChipSelect 0x0001 +#define SDIShiftCount 3 +#define SD0ShiftCount 2 +#define DelayValue 1000 /* number of microseconds */ +#define SROMStartOffset 10 /* this is in words */ +#define SROMReadCount 3 /* number of words to read from SROM */ +#define SROMAddressBits 6 +#define EnetAddressOffset 20 + +static unsigned char +bmac_clock_out_bit(struct net_device *dev) +{ + unsigned short data; + unsigned short val; + + bmwrite(dev, SROMCSR, ChipSelect | Clk); + udelay(DelayValue); + + data = bmread(dev, SROMCSR); + udelay(DelayValue); + val = (data >> SD0ShiftCount) & 1; + + bmwrite(dev, SROMCSR, ChipSelect); + udelay(DelayValue); + + return val; +} + +static void +bmac_clock_in_bit(struct net_device *dev, unsigned int val) +{ + unsigned short data; + + if (val != 0 && val != 1) return; + + data = (val << SDIShiftCount); + bmwrite(dev, SROMCSR, data | ChipSelect ); + udelay(DelayValue); + + bmwrite(dev, SROMCSR, data | ChipSelect | Clk ); + udelay(DelayValue); + + bmwrite(dev, SROMCSR, data | ChipSelect); + udelay(DelayValue); +} + +static void +reset_and_select_srom(struct net_device *dev) +{ + /* first reset */ + bmwrite(dev, SROMCSR, 0); + udelay(DelayValue); + + /* send it the read command (110) */ + bmac_clock_in_bit(dev, 1); + bmac_clock_in_bit(dev, 1); + bmac_clock_in_bit(dev, 0); +} + +static unsigned short +read_srom(struct net_device *dev, unsigned int addr, unsigned int addr_len) +{ + unsigned short data, val; + int i; + + /* send out the address we want to read from */ + for (i = 0; i < addr_len; i++) { + val = addr >> (addr_len-i-1); + bmac_clock_in_bit(dev, val & 1); + } + + /* Now read in the 16-bit data */ + data = 0; + for (i = 0; i < 16; i++) { + val = bmac_clock_out_bit(dev); + data <<= 1; + data |= val; + } + bmwrite(dev, SROMCSR, 0); + + return data; +} + +/* + * It looks like Cogent and SMC use different methods for calculating + * checksums. What a pain.. + */ + +static int +bmac_verify_checksum(struct net_device *dev) +{ + unsigned short data, storedCS; + + reset_and_select_srom(dev); + data = read_srom(dev, 3, SROMAddressBits); + storedCS = ((data >> 8) & 0x0ff) | ((data << 8) & 0xff00); + + return 0; +} + + +static void +bmac_get_station_address(struct net_device *dev, unsigned char *ea) +{ + int i; + unsigned short data; + + for (i = 0; i < 6; i++) + { + reset_and_select_srom(dev); + data = read_srom(dev, i + EnetAddressOffset/2, SROMAddressBits); + ea[2*i] = bitrev8(data & 0x0ff); + ea[2*i+1] = bitrev8((data >> 8) & 0x0ff); + } +} + +static void bmac_reset_and_enable(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + unsigned long flags; + struct sk_buff *skb; + unsigned char *data; + + spin_lock_irqsave(&bp->lock, flags); + bmac_enable_and_reset_chip(dev); + bmac_init_tx_ring(bp); + bmac_init_rx_ring(bp); + bmac_init_chip(dev); + bmac_start_chip(dev); + bmwrite(dev, INTDISABLE, EnableNormal); + bp->sleeping = 0; + + /* + * It seems that the bmac can't receive until it's transmitted + * a packet. So we give it a dummy packet to transmit. + */ + skb = dev_alloc_skb(ETHERMINPACKET); + if (skb != NULL) { + data = skb_put(skb, ETHERMINPACKET); + memset(data, 0, ETHERMINPACKET); + memcpy(data, dev->dev_addr, 6); + memcpy(data+6, dev->dev_addr, 6); + bmac_transmit_packet(skb, dev); + } + spin_unlock_irqrestore(&bp->lock, flags); +} + +static const struct ethtool_ops bmac_ethtool_ops = { + .get_link = ethtool_op_get_link, +}; + +static const struct net_device_ops bmac_netdev_ops = { + .ndo_open = bmac_open, + .ndo_stop = bmac_close, + .ndo_start_xmit = bmac_output, + .ndo_set_multicast_list = bmac_set_multicast, + .ndo_set_mac_address = bmac_set_address, + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, +}; + +static int __devinit bmac_probe(struct macio_dev *mdev, const struct of_device_id *match) +{ + int j, rev, ret; + struct bmac_data *bp; + const unsigned char *prop_addr; + unsigned char addr[6]; + struct net_device *dev; + int is_bmac_plus = ((int)match->data) != 0; + + if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { + printk(KERN_ERR "BMAC: can't use, need 3 addrs and 3 intrs\n"); + return -ENODEV; + } + prop_addr = of_get_property(macio_get_of_node(mdev), + "mac-address", NULL); + if (prop_addr == NULL) { + prop_addr = of_get_property(macio_get_of_node(mdev), + "local-mac-address", NULL); + if (prop_addr == NULL) { + printk(KERN_ERR "BMAC: Can't get mac-address\n"); + return -ENODEV; + } + } + memcpy(addr, prop_addr, sizeof(addr)); + + dev = alloc_etherdev(PRIV_BYTES); + if (!dev) { + printk(KERN_ERR "BMAC: alloc_etherdev failed, out of memory\n"); + return -ENOMEM; + } + + bp = netdev_priv(dev); + SET_NETDEV_DEV(dev, &mdev->ofdev.dev); + macio_set_drvdata(mdev, dev); + + bp->mdev = mdev; + spin_lock_init(&bp->lock); + + if (macio_request_resources(mdev, "bmac")) { + printk(KERN_ERR "BMAC: can't request IO resource !\n"); + goto out_free; + } + + dev->base_addr = (unsigned long) + ioremap(macio_resource_start(mdev, 0), macio_resource_len(mdev, 0)); + if (dev->base_addr == 0) + goto out_release; + + dev->irq = macio_irq(mdev, 0); + + bmac_enable_and_reset_chip(dev); + bmwrite(dev, INTDISABLE, DisableAll); + + rev = addr[0] == 0 && addr[1] == 0xA0; + for (j = 0; j < 6; ++j) + dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; + + /* Enable chip without interrupts for now */ + bmac_enable_and_reset_chip(dev); + bmwrite(dev, INTDISABLE, DisableAll); + + dev->netdev_ops = &bmac_netdev_ops; + dev->ethtool_ops = &bmac_ethtool_ops; + + bmac_get_station_address(dev, addr); + if (bmac_verify_checksum(dev) != 0) + goto err_out_iounmap; + + bp->is_bmac_plus = is_bmac_plus; + bp->tx_dma = ioremap(macio_resource_start(mdev, 1), macio_resource_len(mdev, 1)); + if (!bp->tx_dma) + goto err_out_iounmap; + bp->tx_dma_intr = macio_irq(mdev, 1); + bp->rx_dma = ioremap(macio_resource_start(mdev, 2), macio_resource_len(mdev, 2)); + if (!bp->rx_dma) + goto err_out_iounmap_tx; + bp->rx_dma_intr = macio_irq(mdev, 2); + + bp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(bp + 1); + bp->rx_cmds = bp->tx_cmds + N_TX_RING + 1; + + bp->queue = (struct sk_buff_head *)(bp->rx_cmds + N_RX_RING + 1); + skb_queue_head_init(bp->queue); + + init_timer(&bp->tx_timeout); + + ret = request_irq(dev->irq, bmac_misc_intr, 0, "BMAC-misc", dev); + if (ret) { + printk(KERN_ERR "BMAC: can't get irq %d\n", dev->irq); + goto err_out_iounmap_rx; + } + ret = request_irq(bp->tx_dma_intr, bmac_txdma_intr, 0, "BMAC-txdma", dev); + if (ret) { + printk(KERN_ERR "BMAC: can't get irq %d\n", bp->tx_dma_intr); + goto err_out_irq0; + } + ret = request_irq(bp->rx_dma_intr, bmac_rxdma_intr, 0, "BMAC-rxdma", dev); + if (ret) { + printk(KERN_ERR "BMAC: can't get irq %d\n", bp->rx_dma_intr); + goto err_out_irq1; + } + + /* Mask chip interrupts and disable chip, will be + * re-enabled on open() + */ + disable_irq(dev->irq); + pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); + + if (register_netdev(dev) != 0) { + printk(KERN_ERR "BMAC: Ethernet registration failed\n"); + goto err_out_irq2; + } + + printk(KERN_INFO "%s: BMAC%s at %pM", + dev->name, (is_bmac_plus ? "+" : ""), dev->dev_addr); + XXDEBUG((", base_addr=%#0lx", dev->base_addr)); + printk("\n"); + + return 0; + +err_out_irq2: + free_irq(bp->rx_dma_intr, dev); +err_out_irq1: + free_irq(bp->tx_dma_intr, dev); +err_out_irq0: + free_irq(dev->irq, dev); +err_out_iounmap_rx: + iounmap(bp->rx_dma); +err_out_iounmap_tx: + iounmap(bp->tx_dma); +err_out_iounmap: + iounmap((void __iomem *)dev->base_addr); +out_release: + macio_release_resources(mdev); +out_free: + pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); + free_netdev(dev); + + return -ENODEV; +} + +static int bmac_open(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + /* XXDEBUG(("bmac: enter open\n")); */ + /* reset the chip */ + bp->opened = 1; + bmac_reset_and_enable(dev); + enable_irq(dev->irq); + return 0; +} + +static int bmac_close(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + volatile struct dbdma_regs __iomem *td = bp->tx_dma; + unsigned short config; + int i; + + bp->sleeping = 1; + + /* disable rx and tx */ + config = bmread(dev, RXCFG); + bmwrite(dev, RXCFG, (config & ~RxMACEnable)); + + config = bmread(dev, TXCFG); + bmwrite(dev, TXCFG, (config & ~TxMACEnable)); + + bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */ + + /* disable rx and tx dma */ + st_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ + st_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE)); /* clear run bit */ + + /* free some skb's */ + XXDEBUG(("bmac: free rx bufs\n")); + for (i=0; irx_bufs[i] != NULL) { + dev_kfree_skb(bp->rx_bufs[i]); + bp->rx_bufs[i] = NULL; + } + } + XXDEBUG(("bmac: free tx bufs\n")); + for (i = 0; itx_bufs[i] != NULL) { + dev_kfree_skb(bp->tx_bufs[i]); + bp->tx_bufs[i] = NULL; + } + } + XXDEBUG(("bmac: all bufs freed\n")); + + bp->opened = 0; + disable_irq(dev->irq); + pmac_call_feature(PMAC_FTR_BMAC_ENABLE, macio_get_of_node(bp->mdev), 0, 0); + + return 0; +} + +static void +bmac_start(struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + int i; + struct sk_buff *skb; + unsigned long flags; + + if (bp->sleeping) + return; + + spin_lock_irqsave(&bp->lock, flags); + while (1) { + i = bp->tx_fill + 1; + if (i >= N_TX_RING) + i = 0; + if (i == bp->tx_empty) + break; + skb = skb_dequeue(bp->queue); + if (skb == NULL) + break; + bmac_transmit_packet(skb, dev); + } + spin_unlock_irqrestore(&bp->lock, flags); +} + +static int +bmac_output(struct sk_buff *skb, struct net_device *dev) +{ + struct bmac_data *bp = netdev_priv(dev); + skb_queue_tail(bp->queue, skb); + bmac_start(dev); + return NETDEV_TX_OK; +} + +static void bmac_tx_timeout(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct bmac_data *bp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *td = bp->tx_dma; + volatile struct dbdma_regs __iomem *rd = bp->rx_dma; + volatile struct dbdma_cmd *cp; + unsigned long flags; + unsigned short config, oldConfig; + int i; + + XXDEBUG(("bmac: tx_timeout called\n")); + spin_lock_irqsave(&bp->lock, flags); + bp->timeout_active = 0; + + /* update various counters */ +/* bmac_handle_misc_intrs(bp, 0); */ + + cp = &bp->tx_cmds[bp->tx_empty]; +/* XXDEBUG((KERN_DEBUG "bmac: tx dmastat=%x %x runt=%d pr=%x fs=%x fc=%x\n", */ +/* ld_le32(&td->status), ld_le16(&cp->xfer_status), bp->tx_bad_runt, */ +/* mb->pr, mb->xmtfs, mb->fifofc)); */ + + /* turn off both tx and rx and reset the chip */ + config = bmread(dev, RXCFG); + bmwrite(dev, RXCFG, (config & ~RxMACEnable)); + config = bmread(dev, TXCFG); + bmwrite(dev, TXCFG, (config & ~TxMACEnable)); + out_le32(&td->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); + printk(KERN_ERR "bmac: transmit timeout - resetting\n"); + bmac_enable_and_reset_chip(dev); + + /* restart rx dma */ + cp = bus_to_virt(ld_le32(&rd->cmdptr)); + out_le32(&rd->control, DBDMA_CLEAR(RUN|PAUSE|FLUSH|WAKE|ACTIVE|DEAD)); + out_le16(&cp->xfer_status, 0); + out_le32(&rd->cmdptr, virt_to_bus(cp)); + out_le32(&rd->control, DBDMA_SET(RUN|WAKE)); + + /* fix up the transmit side */ + XXDEBUG((KERN_DEBUG "bmac: tx empty=%d fill=%d fullup=%d\n", + bp->tx_empty, bp->tx_fill, bp->tx_fullup)); + i = bp->tx_empty; + ++dev->stats.tx_errors; + if (i != bp->tx_fill) { + dev_kfree_skb(bp->tx_bufs[i]); + bp->tx_bufs[i] = NULL; + if (++i >= N_TX_RING) i = 0; + bp->tx_empty = i; + } + bp->tx_fullup = 0; + netif_wake_queue(dev); + if (i != bp->tx_fill) { + cp = &bp->tx_cmds[i]; + out_le16(&cp->xfer_status, 0); + out_le16(&cp->command, OUTPUT_LAST); + out_le32(&td->cmdptr, virt_to_bus(cp)); + out_le32(&td->control, DBDMA_SET(RUN)); + /* bmac_set_timeout(dev); */ + XXDEBUG((KERN_DEBUG "bmac: starting %d\n", i)); + } + + /* turn it back on */ + oldConfig = bmread(dev, RXCFG); + bmwrite(dev, RXCFG, oldConfig | RxMACEnable ); + oldConfig = bmread(dev, TXCFG); + bmwrite(dev, TXCFG, oldConfig | TxMACEnable ); + + spin_unlock_irqrestore(&bp->lock, flags); +} + +#if 0 +static void dump_dbdma(volatile struct dbdma_cmd *cp,int count) +{ + int i,*ip; + + for (i=0;i< count;i++) { + ip = (int*)(cp+i); + + printk("dbdma req 0x%x addr 0x%x baddr 0x%x xfer/res 0x%x\n", + ld_le32(ip+0), + ld_le32(ip+1), + ld_le32(ip+2), + ld_le32(ip+3)); + } + +} +#endif + +#if 0 +static int +bmac_proc_info(char *buffer, char **start, off_t offset, int length) +{ + int len = 0; + off_t pos = 0; + off_t begin = 0; + int i; + + if (bmac_devs == NULL) + return -ENOSYS; + + len += sprintf(buffer, "BMAC counters & registers\n"); + + for (i = 0; i offset+length) break; + } + + *start = buffer + (offset - begin); + len -= (offset - begin); + + if (len > length) len = length; + + return len; +} +#endif + +static int __devexit bmac_remove(struct macio_dev *mdev) +{ + struct net_device *dev = macio_get_drvdata(mdev); + struct bmac_data *bp = netdev_priv(dev); + + unregister_netdev(dev); + + free_irq(dev->irq, dev); + free_irq(bp->tx_dma_intr, dev); + free_irq(bp->rx_dma_intr, dev); + + iounmap((void __iomem *)dev->base_addr); + iounmap(bp->tx_dma); + iounmap(bp->rx_dma); + + macio_release_resources(mdev); + + free_netdev(dev); + + return 0; +} + +static struct of_device_id bmac_match[] = +{ + { + .name = "bmac", + .data = (void *)0, + }, + { + .type = "network", + .compatible = "bmac+", + .data = (void *)1, + }, + {}, +}; +MODULE_DEVICE_TABLE (of, bmac_match); + +static struct macio_driver bmac_driver = +{ + .driver = { + .name = "bmac", + .owner = THIS_MODULE, + .of_match_table = bmac_match, + }, + .probe = bmac_probe, + .remove = bmac_remove, +#ifdef CONFIG_PM + .suspend = bmac_suspend, + .resume = bmac_resume, +#endif +}; + + +static int __init bmac_init(void) +{ + if (bmac_emergency_rxbuf == NULL) { + bmac_emergency_rxbuf = kmalloc(RX_BUFLEN, GFP_KERNEL); + if (bmac_emergency_rxbuf == NULL) { + printk(KERN_ERR "BMAC: can't allocate emergency RX buffer\n"); + return -ENOMEM; + } + } + + return macio_register_driver(&bmac_driver); +} + +static void __exit bmac_exit(void) +{ + macio_unregister_driver(&bmac_driver); + + kfree(bmac_emergency_rxbuf); + bmac_emergency_rxbuf = NULL; +} + +MODULE_AUTHOR("Randy Gobbel/Paul Mackerras"); +MODULE_DESCRIPTION("PowerMac BMAC ethernet driver."); +MODULE_LICENSE("GPL"); + +module_init(bmac_init); +module_exit(bmac_exit); diff --git a/drivers/net/ethernet/apple/bmac.h b/drivers/net/ethernet/apple/bmac.h new file mode 100644 index 00000000000..a1d19d867ba --- /dev/null +++ b/drivers/net/ethernet/apple/bmac.h @@ -0,0 +1,164 @@ +/* + * mace.h - definitions for the registers in the "Big Mac" + * Ethernet controller found in PowerMac G3 models. + * + * Copyright (C) 1998 Randy Gobbel. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal" + * (HME) controller. See sunhme.h + */ + + +/* register offsets */ + +/* global status and control */ +#define XIFC 0x000 /* low-level interface control */ +# define TxOutputEnable 0x0001 /* output driver enable */ +# define XIFLoopback 0x0002 /* Loopback-mode XIF enable */ +# define MIILoopback 0x0004 /* Loopback-mode MII enable */ +# define MIILoopbackBits 0x0006 +# define MIIBuffDisable 0x0008 /* MII receive buffer disable */ +# define SQETestEnable 0x0010 /* SQE test enable */ +# define SQETimeWindow 0x03e0 /* SQE time window */ +# define XIFLanceMode 0x0010 /* Lance mode enable */ +# define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */ +#define TXFIFOCSR 0x100 /* transmit FIFO control */ +# define TxFIFOEnable 0x0001 +#define TXTH 0x110 /* transmit threshold */ +# define TxThreshold 0x0004 +#define RXFIFOCSR 0x120 /* receive FIFO control */ +# define RxFIFOEnable 0x0001 +#define MEMADD 0x130 /* memory address, unknown function */ +#define MEMDATAHI 0x140 /* memory data high, presently unused in driver */ +#define MEMDATALO 0x150 /* memory data low, presently unused in driver */ +#define XCVRIF 0x160 /* transceiver interface control */ +# define COLActiveLow 0x0002 +# define SerialMode 0x0004 +# define ClkBit 0x0008 +# define LinkStatus 0x0100 +#define CHIPID 0x170 /* chip ID */ +#define MIFCSR 0x180 /* ??? */ +#define SROMCSR 0x190 /* SROM control */ +# define ChipSelect 0x0001 +# define Clk 0x0002 +#define TXPNTR 0x1a0 /* transmit pointer */ +#define RXPNTR 0x1b0 /* receive pointer */ +#define STATUS 0x200 /* status--reading this clears it */ +#define INTDISABLE 0x210 /* interrupt enable/disable control */ +/* bits below are the same in both STATUS and INTDISABLE registers */ +# define FrameReceived 0x00000001 /* Received a frame */ +# define RxFrameCntExp 0x00000002 /* Receive frame counter expired */ +# define RxAlignCntExp 0x00000004 /* Align-error counter expired */ +# define RxCRCCntExp 0x00000008 /* CRC-error counter expired */ +# define RxLenCntExp 0x00000010 /* Length-error counter expired */ +# define RxOverFlow 0x00000020 /* Receive FIFO overflow */ +# define RxCodeViolation 0x00000040 /* Code-violation counter expired */ +# define SQETestError 0x00000080 /* Test error in XIF for SQE */ +# define FrameSent 0x00000100 /* Transmitted a frame */ +# define TxUnderrun 0x00000200 /* Transmit FIFO underrun */ +# define TxMaxSizeError 0x00000400 /* Max-packet size error */ +# define TxNormalCollExp 0x00000800 /* Normal-collision counter expired */ +# define TxExcessCollExp 0x00001000 /* Excess-collision counter expired */ +# define TxLateCollExp 0x00002000 /* Late-collision counter expired */ +# define TxNetworkCollExp 0x00004000 /* First-collision counter expired */ +# define TxDeferTimerExp 0x00008000 /* Defer-timer expired */ +# define RxFIFOToHost 0x00010000 /* Data moved from FIFO to host */ +# define RxNoDescriptors 0x00020000 /* No more receive descriptors */ +# define RxDMAError 0x00040000 /* Error during receive DMA */ +# define RxDMALateErr 0x00080000 /* Receive DMA, data late */ +# define RxParityErr 0x00100000 /* Parity error during receive DMA */ +# define RxTagError 0x00200000 /* Tag error during receive DMA */ +# define TxEOPError 0x00400000 /* Tx descriptor did not have EOP set */ +# define MIFIntrEvent 0x00800000 /* MIF is signaling an interrupt */ +# define TxHostToFIFO 0x01000000 /* Data moved from host to FIFO */ +# define TxFIFOAllSent 0x02000000 /* Transmitted all packets in FIFO */ +# define TxDMAError 0x04000000 /* Error during transmit DMA */ +# define TxDMALateError 0x08000000 /* Late error during transmit DMA */ +# define TxParityError 0x10000000 /* Parity error during transmit DMA */ +# define TxTagError 0x20000000 /* Tag error during transmit DMA */ +# define PIOError 0x40000000 /* PIO access got an error */ +# define PIOParityError 0x80000000 /* PIO access got a parity error */ +# define DisableAll 0xffffffff +# define EnableAll 0x00000000 +/* # define NormalIntEvents ~(FrameReceived | FrameSent | TxUnderrun) */ +# define EnableNormal ~(FrameReceived | FrameSent) +# define EnableErrors (FrameReceived | FrameSent) +# define RxErrorMask (RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \ + RxLenCntExp | RxOverFlow | RxCodeViolation) +# define TxErrorMask (TxUnderrun | TxMaxSizeError | TxExcessCollExp | \ + TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp) + +/* transmit control */ +#define TXRST 0x420 /* transmit reset */ +# define TxResetBit 0x0001 +#define TXCFG 0x430 /* transmit configuration control*/ +# define TxMACEnable 0x0001 /* output driver enable */ +# define TxSlowMode 0x0020 /* enable slow mode */ +# define TxIgnoreColl 0x0040 /* ignore transmit collisions */ +# define TxNoFCS 0x0080 /* do not emit FCS */ +# define TxNoBackoff 0x0100 /* no backoff in case of collisions */ +# define TxFullDuplex 0x0200 /* enable full-duplex */ +# define TxNeverGiveUp 0x0400 /* don't give up on transmits */ +#define IPG1 0x440 /* Inter-packet gap 1 */ +#define IPG2 0x450 /* Inter-packet gap 2 */ +#define ALIMIT 0x460 /* Transmit attempt limit */ +#define SLOT 0x470 /* Transmit slot time */ +#define PALEN 0x480 /* Size of transmit preamble */ +#define PAPAT 0x490 /* Pattern for transmit preamble */ +#define TXSFD 0x4a0 /* Transmit frame delimiter */ +#define JAM 0x4b0 /* Jam size */ +#define TXMAX 0x4c0 /* Transmit max pkt size */ +#define TXMIN 0x4d0 /* Transmit min pkt size */ +#define PAREG 0x4e0 /* Count of transmit peak attempts */ +#define DCNT 0x4f0 /* Transmit defer timer */ +#define NCCNT 0x500 /* Transmit normal-collision counter */ +#define NTCNT 0x510 /* Transmit first-collision counter */ +#define EXCNT 0x520 /* Transmit excess-collision counter */ +#define LTCNT 0x530 /* Transmit late-collision counter */ +#define RSEED 0x540 /* Transmit random number seed */ +#define TXSM 0x550 /* Transmit state machine */ + +/* receive control */ +#define RXRST 0x620 /* receive reset */ +# define RxResetValue 0x0000 +#define RXCFG 0x630 /* receive configuration control */ +# define RxMACEnable 0x0001 /* receiver overall enable */ +# define RxCFGReserved 0x0004 +# define RxPadStripEnab 0x0020 /* enable pad byte stripping */ +# define RxPromiscEnable 0x0040 /* turn on promiscuous mode */ +# define RxNoErrCheck 0x0080 /* disable receive error checking */ +# define RxCRCNoStrip 0x0100 /* disable auto-CRC-stripping */ +# define RxRejectOwnPackets 0x0200 /* don't receive our own packets */ +# define RxGrpPromisck 0x0400 /* enable group promiscuous mode */ +# define RxHashFilterEnable 0x0800 /* enable hash filter */ +# define RxAddrFilterEnable 0x1000 /* enable address filter */ +#define RXMAX 0x640 /* Max receive packet size */ +#define RXMIN 0x650 /* Min receive packet size */ +#define MADD2 0x660 /* our enet address, high part */ +#define MADD1 0x670 /* our enet address, middle part */ +#define MADD0 0x680 /* our enet address, low part */ +#define FRCNT 0x690 /* receive frame counter */ +#define LECNT 0x6a0 /* Receive excess length error counter */ +#define AECNT 0x6b0 /* Receive misaligned error counter */ +#define FECNT 0x6c0 /* Receive CRC error counter */ +#define RXSM 0x6d0 /* Receive state machine */ +#define RXCV 0x6e0 /* Receive code violation */ + +#define BHASH3 0x700 /* multicast hash register */ +#define BHASH2 0x710 /* multicast hash register */ +#define BHASH1 0x720 /* multicast hash register */ +#define BHASH0 0x730 /* multicast hash register */ + +#define AFR2 0x740 /* address filtering setup? */ +#define AFR1 0x750 /* address filtering setup? */ +#define AFR0 0x760 /* address filtering setup? */ +#define AFCR 0x770 /* address filter compare register? */ +# define EnableAllCompares 0x0fff + +/* bits in XIFC */ diff --git a/drivers/net/ethernet/apple/cs89x0.c b/drivers/net/ethernet/apple/cs89x0.c new file mode 100644 index 00000000000..537a4b2e202 --- /dev/null +++ b/drivers/net/ethernet/apple/cs89x0.c @@ -0,0 +1,1913 @@ +/* cs89x0.c: A Crystal Semiconductor (Now Cirrus Logic) CS89[02]0 + * driver for linux. + */ + +/* + Written 1996 by Russell Nelson, with reference to skeleton.c + written 1993-1994 by Donald Becker. + + This software may be used and distributed according to the terms + of the GNU General Public License, incorporated herein by reference. + + The author may be reached at nelson@crynwr.com, Crynwr + Software, 521 Pleasant Valley Rd., Potsdam, NY 13676 + + Changelog: + + Mike Cruse : mcruse@cti-ltd.com + : Changes for Linux 2.0 compatibility. + : Added dev_id parameter in net_interrupt(), + : request_irq() and free_irq(). Just NULL for now. + + Mike Cruse : Added MOD_INC_USE_COUNT and MOD_DEC_USE_COUNT macros + : in net_open() and net_close() so kerneld would know + : that the module is in use and wouldn't eject the + : driver prematurely. + + Mike Cruse : Rewrote init_module() and cleanup_module using 8390.c + : as an example. Disabled autoprobing in init_module(), + : not a good thing to do to other devices while Linux + : is running from all accounts. + + Russ Nelson : Jul 13 1998. Added RxOnly DMA support. + + Melody Lee : Aug 10 1999. Changes for Linux 2.2.5 compatibility. + : email: ethernet@crystal.cirrus.com + + Alan Cox : Removed 1.2 support, added 2.1 extra counters. + + Andrew Morton : Kernel 2.3.48 + : Handle kmalloc() failures + : Other resource allocation fixes + : Add SMP locks + : Integrate Russ Nelson's ALLOW_DMA functionality back in. + : If ALLOW_DMA is true, make DMA runtime selectable + : Folded in changes from Cirrus (Melody Lee + : ) + : Don't call netif_wake_queue() in net_send_packet() + : Fixed an out-of-mem bug in dma_rx() + : Updated Documentation/networking/cs89x0.txt + + Andrew Morton : Kernel 2.3.99-pre1 + : Use skb_reserve to longword align IP header (two places) + : Remove a delay loop from dma_rx() + : Replace '100' with HZ + : Clean up a couple of skb API abuses + : Added 'cs89x0_dma=N' kernel boot option + : Correctly initialise lp->lock in non-module compile + + Andrew Morton : Kernel 2.3.99-pre4-1 + : MOD_INC/DEC race fix (see + : http://www.uwsg.indiana.edu/hypermail/linux/kernel/0003.3/1532.html) + + Andrew Morton : Kernel 2.4.0-test7-pre2 + : Enhanced EEPROM support to cover more devices, + : abstracted IRQ mapping to support CONFIG_ARCH_CLPS7500 arch + : (Jason Gunthorpe ) + + Andrew Morton : Kernel 2.4.0-test11-pre4 + : Use dev->name in request_*() (Andrey Panin) + : Fix an error-path memleak in init_module() + : Preserve return value from request_irq() + : Fix type of `media' module parm (Keith Owens) + : Use SET_MODULE_OWNER() + : Tidied up strange request_irq() abuse in net_open(). + + Andrew Morton : Kernel 2.4.3-pre1 + : Request correct number of pages for DMA (Hugh Dickens) + : Select PP_ChipID _after_ unregister_netdev in cleanup_module() + : because unregister_netdev() calls get_stats. + : Make `version[]' __initdata + : Uninlined the read/write reg/word functions. + + Oskar Schirmer : oskar@scara.com + : HiCO.SH4 (superh) support added (irq#1, cs89x0_media=) + + Deepak Saxena : dsaxena@plexity.net + : Intel IXDP2x01 (XScale ixp2x00 NPU) platform support + + Dmitry Pervushin : dpervushin@ru.mvista.com + : PNX010X platform support + + Deepak Saxena : dsaxena@plexity.net + : Intel IXDP2351 platform support + + Dmitry Pervushin : dpervushin@ru.mvista.com + : PNX010X platform support + + Domenico Andreoli : cavokz@gmail.com + : QQ2440 platform support + +*/ + +/* Always include 'config.h' first in case the user wants to turn on + or override something. */ +#include + +/* + * Set this to zero to disable DMA code + * + * Note that even if DMA is turned off we still support the 'dma' and 'use_dma' + * module options so we don't break any startup scripts. + */ +#ifndef CONFIG_ISA_DMA_API +#define ALLOW_DMA 0 +#else +#define ALLOW_DMA 1 +#endif + +/* + * Set this to zero to remove all the debug statements via + * dead code elimination + */ +#define DEBUGGING 1 + +/* + Sources: + + Crynwr packet driver epktisa. + + Crystal Semiconductor data sheets. + +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#if ALLOW_DMA +#include +#endif + +#include "cs89x0.h" + +static char version[] __initdata = +"cs89x0.c: v2.4.3-pre1 Russell Nelson , Andrew Morton\n"; + +#define DRV_NAME "cs89x0" + +/* First, a few definitions that the brave might change. + A zero-terminated list of I/O addresses to be probed. Some special flags.. + Addr & 1 = Read back the address port, look for signature and reset + the page window before probing + Addr & 3 = Reset the page window and probe + The CLPS eval board has the Cirrus chip at 0x80090300, in ARM IO space, + but it is possible that a Cirrus board could be plugged into the ISA + slots. */ +/* The cs8900 has 4 IRQ pins, software selectable. cs8900_irq_map maps + them to system IRQ numbers. This mapping is card specific and is set to + the configuration of the Cirrus Eval board for this chip. */ +#if defined(CONFIG_MACH_IXDP2351) +static unsigned int netcard_portlist[] __used __initdata = {IXDP2351_VIRT_CS8900_BASE, 0}; +static unsigned int cs8900_irq_map[] = {IRQ_IXDP2351_CS8900, 0, 0, 0}; +#elif defined(CONFIG_ARCH_IXDP2X01) +static unsigned int netcard_portlist[] __used __initdata = {IXDP2X01_CS8900_VIRT_BASE, 0}; +static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0}; +#elif defined(CONFIG_MACH_QQ2440) +#include +static unsigned int netcard_portlist[] __used __initdata = { QQ2440_CS8900_VIRT_BASE + 0x300, 0 }; +static unsigned int cs8900_irq_map[] = { QQ2440_CS8900_IRQ, 0, 0, 0 }; +#elif defined(CONFIG_MACH_MX31ADS) +#include +static unsigned int netcard_portlist[] __used __initdata = { + PBC_BASE_ADDRESS + PBC_CS8900A_IOBASE + 0x300, 0 +}; +static unsigned cs8900_irq_map[] = {EXPIO_INT_ENET_INT, 0, 0, 0}; +#else +static unsigned int netcard_portlist[] __used __initdata = + { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; +static unsigned int cs8900_irq_map[] = {10,11,12,5}; +#endif + +#if DEBUGGING +static unsigned int net_debug = DEBUGGING; +#else +#define net_debug 0 /* gcc will remove all the debug code for us */ +#endif + +/* The number of low I/O ports used by the ethercard. */ +#define NETCARD_IO_EXTENT 16 + +/* we allow the user to override various values normally set in the EEPROM */ +#define FORCE_RJ45 0x0001 /* pick one of these three */ +#define FORCE_AUI 0x0002 +#define FORCE_BNC 0x0004 + +#define FORCE_AUTO 0x0010 /* pick one of these three */ +#define FORCE_HALF 0x0020 +#define FORCE_FULL 0x0030 + +/* Information that need to be kept for each board. */ +struct net_local { + int chip_type; /* one of: CS8900, CS8920, CS8920M */ + char chip_revision; /* revision letter of the chip ('A'...) */ + int send_cmd; /* the proper send command: TX_NOW, TX_AFTER_381, or TX_AFTER_ALL */ + int auto_neg_cnf; /* auto-negotiation word from EEPROM */ + int adapter_cnf; /* adapter configuration from EEPROM */ + int isa_config; /* ISA configuration from EEPROM */ + int irq_map; /* IRQ map from EEPROM */ + int rx_mode; /* what mode are we in? 0, RX_MULTCAST_ACCEPT, or RX_ALL_ACCEPT */ + int curr_rx_cfg; /* a copy of PP_RxCFG */ + int linectl; /* either 0 or LOW_RX_SQUELCH, depending on configuration. */ + int send_underrun; /* keep track of how many underruns in a row we get */ + int force; /* force various values; see FORCE* above. */ + spinlock_t lock; +#if ALLOW_DMA + int use_dma; /* Flag: we're using dma */ + int dma; /* DMA channel */ + int dmasize; /* 16 or 64 */ + unsigned char *dma_buff; /* points to the beginning of the buffer */ + unsigned char *end_dma_buff; /* points to the end of the buffer */ + unsigned char *rx_dma_ptr; /* points to the next packet */ +#endif +}; + +/* Index to functions, as function prototypes. */ + +static int cs89x0_probe1(struct net_device *dev, int ioaddr, int modular); +static int net_open(struct net_device *dev); +static netdev_tx_t net_send_packet(struct sk_buff *skb, struct net_device *dev); +static irqreturn_t net_interrupt(int irq, void *dev_id); +static void set_multicast_list(struct net_device *dev); +static void net_timeout(struct net_device *dev); +static void net_rx(struct net_device *dev); +static int net_close(struct net_device *dev); +static struct net_device_stats *net_get_stats(struct net_device *dev); +static void reset_chip(struct net_device *dev); +static int get_eeprom_data(struct net_device *dev, int off, int len, int *buffer); +static int get_eeprom_cksum(int off, int len, int *buffer); +static int set_mac_address(struct net_device *dev, void *addr); +static void count_rx_errors(int status, struct net_device *dev); +#ifdef CONFIG_NET_POLL_CONTROLLER +static void net_poll_controller(struct net_device *dev); +#endif +#if ALLOW_DMA +static void get_dma_channel(struct net_device *dev); +static void release_dma_buff(struct net_local *lp); +#endif + +/* Example routines you must write ;->. */ +#define tx_done(dev) 1 + +/* + * Permit 'cs89x0_dma=N' in the kernel boot environment + */ +#if !defined(MODULE) && (ALLOW_DMA != 0) +static int g_cs89x0_dma; + +static int __init dma_fn(char *str) +{ + g_cs89x0_dma = simple_strtol(str,NULL,0); + return 1; +} + +__setup("cs89x0_dma=", dma_fn); +#endif /* !defined(MODULE) && (ALLOW_DMA != 0) */ + +#ifndef MODULE +static int g_cs89x0_media__force; + +static int __init media_fn(char *str) +{ + if (!strcmp(str, "rj45")) g_cs89x0_media__force = FORCE_RJ45; + else if (!strcmp(str, "aui")) g_cs89x0_media__force = FORCE_AUI; + else if (!strcmp(str, "bnc")) g_cs89x0_media__force = FORCE_BNC; + return 1; +} + +__setup("cs89x0_media=", media_fn); + + +/* Check for a network adaptor of this type, and return '0' iff one exists. + If dev->base_addr == 0, probe all likely locations. + If dev->base_addr == 1, always return failure. + If dev->base_addr == 2, allocate space for the device and return success + (detachable devices only). + Return 0 on success. + */ + +struct net_device * __init cs89x0_probe(int unit) +{ + struct net_device *dev = alloc_etherdev(sizeof(struct net_local)); + unsigned *port; + int err = 0; + int irq; + int io; + + if (!dev) + return ERR_PTR(-ENODEV); + + sprintf(dev->name, "eth%d", unit); + netdev_boot_setup_check(dev); + io = dev->base_addr; + irq = dev->irq; + + if (net_debug) + printk("cs89x0:cs89x0_probe(0x%x)\n", io); + + if (io > 0x1ff) { /* Check a single specified location. */ + err = cs89x0_probe1(dev, io, 0); + } else if (io != 0) { /* Don't probe at all. */ + err = -ENXIO; + } else { + for (port = netcard_portlist; *port; port++) { + if (cs89x0_probe1(dev, *port, 0) == 0) + break; + dev->irq = irq; + } + if (!*port) + err = -ENODEV; + } + if (err) + goto out; + return dev; +out: + free_netdev(dev); + printk(KERN_WARNING "cs89x0: no cs8900 or cs8920 detected. Be sure to disable PnP with SETUP\n"); + return ERR_PTR(err); +} +#endif + +#if defined(CONFIG_MACH_IXDP2351) +static u16 +readword(unsigned long base_addr, int portno) +{ + return __raw_readw(base_addr + (portno << 1)); +} + +static void +writeword(unsigned long base_addr, int portno, u16 value) +{ + __raw_writew(value, base_addr + (portno << 1)); +} +#elif defined(CONFIG_ARCH_IXDP2X01) +static u16 +readword(unsigned long base_addr, int portno) +{ + return __raw_readl(base_addr + (portno << 1)); +} + +static void +writeword(unsigned long base_addr, int portno, u16 value) +{ + __raw_writel(value, base_addr + (portno << 1)); +} +#else +static u16 +readword(unsigned long base_addr, int portno) +{ + return inw(base_addr + portno); +} + +static void +writeword(unsigned long base_addr, int portno, u16 value) +{ + outw(value, base_addr + portno); +} +#endif + +static void +readwords(unsigned long base_addr, int portno, void *buf, int length) +{ + u8 *buf8 = (u8 *)buf; + + do { + u16 tmp16; + + tmp16 = readword(base_addr, portno); + *buf8++ = (u8)tmp16; + *buf8++ = (u8)(tmp16 >> 8); + } while (--length); +} + +static void +writewords(unsigned long base_addr, int portno, void *buf, int length) +{ + u8 *buf8 = (u8 *)buf; + + do { + u16 tmp16; + + tmp16 = *buf8++; + tmp16 |= (*buf8++) << 8; + writeword(base_addr, portno, tmp16); + } while (--length); +} + +static u16 +readreg(struct net_device *dev, u16 regno) +{ + writeword(dev->base_addr, ADD_PORT, regno); + return readword(dev->base_addr, DATA_PORT); +} + +static void +writereg(struct net_device *dev, u16 regno, u16 value) +{ + writeword(dev->base_addr, ADD_PORT, regno); + writeword(dev->base_addr, DATA_PORT, value); +} + +static int __init +wait_eeprom_ready(struct net_device *dev) +{ + int timeout = jiffies; + /* check to see if the EEPROM is ready, a timeout is used - + just in case EEPROM is ready when SI_BUSY in the + PP_SelfST is clear */ + while(readreg(dev, PP_SelfST) & SI_BUSY) + if (jiffies - timeout >= 40) + return -1; + return 0; +} + +static int __init +get_eeprom_data(struct net_device *dev, int off, int len, int *buffer) +{ + int i; + + if (net_debug > 3) printk("EEPROM data from %x for %x:\n",off,len); + for (i = 0; i < len; i++) { + if (wait_eeprom_ready(dev) < 0) return -1; + /* Now send the EEPROM read command and EEPROM location to read */ + writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD); + if (wait_eeprom_ready(dev) < 0) return -1; + buffer[i] = readreg(dev, PP_EEData); + if (net_debug > 3) printk("%04x ", buffer[i]); + } + if (net_debug > 3) printk("\n"); + return 0; +} + +static int __init +get_eeprom_cksum(int off, int len, int *buffer) +{ + int i, cksum; + + cksum = 0; + for (i = 0; i < len; i++) + cksum += buffer[i]; + cksum &= 0xffff; + if (cksum == 0) + return 0; + return -1; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +/* + * Polling receive - used by netconsole and other diagnostic tools + * to allow network i/o with interrupts disabled. + */ +static void net_poll_controller(struct net_device *dev) +{ + disable_irq(dev->irq); + net_interrupt(dev->irq, dev); + enable_irq(dev->irq); +} +#endif + +static const struct net_device_ops net_ops = { + .ndo_open = net_open, + .ndo_stop = net_close, + .ndo_tx_timeout = net_timeout, + .ndo_start_xmit = net_send_packet, + .ndo_get_stats = net_get_stats, + .ndo_set_multicast_list = set_multicast_list, + .ndo_set_mac_address = set_mac_address, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = net_poll_controller, +#endif + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, +}; + +/* This is the real probe routine. Linux has a history of friendly device + probes on the ISA bus. A good device probes avoids doing writes, and + verifies that the correct device exists and functions. + Return 0 on success. + */ + +static int __init +cs89x0_probe1(struct net_device *dev, int ioaddr, int modular) +{ + struct net_local *lp = netdev_priv(dev); + static unsigned version_printed; + int i; + int tmp; + unsigned rev_type = 0; + int eeprom_buff[CHKSUM_LEN]; + int retval; + + /* Initialize the device structure. */ + if (!modular) { + memset(lp, 0, sizeof(*lp)); + spin_lock_init(&lp->lock); +#ifndef MODULE +#if ALLOW_DMA + if (g_cs89x0_dma) { + lp->use_dma = 1; + lp->dma = g_cs89x0_dma; + lp->dmasize = 16; /* Could make this an option... */ + } +#endif + lp->force = g_cs89x0_media__force; +#endif + +#if defined(CONFIG_MACH_QQ2440) + lp->force |= FORCE_RJ45 | FORCE_FULL; +#endif + } + + /* Grab the region so we can find another board if autoIRQ fails. */ + /* WTF is going on here? */ + if (!request_region(ioaddr & ~3, NETCARD_IO_EXTENT, DRV_NAME)) { + printk(KERN_ERR "%s: request_region(0x%x, 0x%x) failed\n", + DRV_NAME, ioaddr, NETCARD_IO_EXTENT); + retval = -EBUSY; + goto out1; + } + + /* if they give us an odd I/O address, then do ONE write to + the address port, to get it back to address zero, where we + expect to find the EISA signature word. An IO with a base of 0x3 + will skip the test for the ADD_PORT. */ + if (ioaddr & 1) { + if (net_debug > 1) + printk(KERN_INFO "%s: odd ioaddr 0x%x\n", dev->name, ioaddr); + if ((ioaddr & 2) != 2) + if ((readword(ioaddr & ~3, ADD_PORT) & ADD_MASK) != ADD_SIG) { + printk(KERN_ERR "%s: bad signature 0x%x\n", + dev->name, readword(ioaddr & ~3, ADD_PORT)); + retval = -ENODEV; + goto out2; + } + } + + ioaddr &= ~3; + printk(KERN_DEBUG "PP_addr at %x[%x]: 0x%x\n", + ioaddr, ADD_PORT, readword(ioaddr, ADD_PORT)); + writeword(ioaddr, ADD_PORT, PP_ChipID); + + tmp = readword(ioaddr, DATA_PORT); + if (tmp != CHIP_EISA_ID_SIG) { + printk(KERN_DEBUG "%s: incorrect signature at %x[%x]: 0x%x!=" + CHIP_EISA_ID_SIG_STR "\n", + dev->name, ioaddr, DATA_PORT, tmp); + retval = -ENODEV; + goto out2; + } + + /* Fill in the 'dev' fields. */ + dev->base_addr = ioaddr; + + /* get the chip type */ + rev_type = readreg(dev, PRODUCT_ID_ADD); + lp->chip_type = rev_type &~ REVISON_BITS; + lp->chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A'; + + /* Check the chip type and revision in order to set the correct send command + CS8920 revision C and CS8900 revision F can use the faster send. */ + lp->send_cmd = TX_AFTER_381; + if (lp->chip_type == CS8900 && lp->chip_revision >= 'F') + lp->send_cmd = TX_NOW; + if (lp->chip_type != CS8900 && lp->chip_revision >= 'C') + lp->send_cmd = TX_NOW; + + if (net_debug && version_printed++ == 0) + printk(version); + + printk(KERN_INFO "%s: cs89%c0%s rev %c found at %#3lx ", + dev->name, + lp->chip_type==CS8900?'0':'2', + lp->chip_type==CS8920M?"M":"", + lp->chip_revision, + dev->base_addr); + + reset_chip(dev); + + /* Here we read the current configuration of the chip. If there + is no Extended EEPROM then the idea is to not disturb the chip + configuration, it should have been correctly setup by automatic + EEPROM read on reset. So, if the chip says it read the EEPROM + the driver will always do *something* instead of complain that + adapter_cnf is 0. */ + + + if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) == + (EEPROM_OK|EEPROM_PRESENT)) { + /* Load the MAC. */ + for (i=0; i < ETH_ALEN/2; i++) { + unsigned int Addr; + Addr = readreg(dev, PP_IA+i*2); + dev->dev_addr[i*2] = Addr & 0xFF; + dev->dev_addr[i*2+1] = Addr >> 8; + } + + /* Load the Adapter Configuration. + Note: Barring any more specific information from some + other source (ie EEPROM+Schematics), we would not know + how to operate a 10Base2 interface on the AUI port. + However, since we do read the status of HCB1 and use + settings that always result in calls to control_dc_dc(dev,0) + a BNC interface should work if the enable pin + (dc/dc converter) is on HCB1. It will be called AUI + however. */ + + lp->adapter_cnf = 0; + i = readreg(dev, PP_LineCTL); + /* Preserve the setting of the HCB1 pin. */ + if ((i & (HCB1 | HCB1_ENBL)) == (HCB1 | HCB1_ENBL)) + lp->adapter_cnf |= A_CNF_DC_DC_POLARITY; + /* Save the sqelch bit */ + if ((i & LOW_RX_SQUELCH) == LOW_RX_SQUELCH) + lp->adapter_cnf |= A_CNF_EXTND_10B_2 | A_CNF_LOW_RX_SQUELCH; + /* Check if the card is in 10Base-t only mode */ + if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == 0) + lp->adapter_cnf |= A_CNF_10B_T | A_CNF_MEDIA_10B_T; + /* Check if the card is in AUI only mode */ + if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == AUI_ONLY) + lp->adapter_cnf |= A_CNF_AUI | A_CNF_MEDIA_AUI; + /* Check if the card is in Auto mode. */ + if ((i & (AUI_ONLY | AUTO_AUI_10BASET)) == AUTO_AUI_10BASET) + lp->adapter_cnf |= A_CNF_AUI | A_CNF_10B_T | + A_CNF_MEDIA_AUI | A_CNF_MEDIA_10B_T | A_CNF_MEDIA_AUTO; + + if (net_debug > 1) + printk(KERN_INFO "%s: PP_LineCTL=0x%x, adapter_cnf=0x%x\n", + dev->name, i, lp->adapter_cnf); + + /* IRQ. Other chips already probe, see below. */ + if (lp->chip_type == CS8900) + lp->isa_config = readreg(dev, PP_CS8900_ISAINT) & INT_NO_MASK; + + printk( "[Cirrus EEPROM] "); + } + + printk("\n"); + + /* First check to see if an EEPROM is attached. */ + + if ((readreg(dev, PP_SelfST) & EEPROM_PRESENT) == 0) + printk(KERN_WARNING "cs89x0: No EEPROM, relying on command line....\n"); + else if (get_eeprom_data(dev, START_EEPROM_DATA,CHKSUM_LEN,eeprom_buff) < 0) { + printk(KERN_WARNING "\ncs89x0: EEPROM read failed, relying on command line.\n"); + } else if (get_eeprom_cksum(START_EEPROM_DATA,CHKSUM_LEN,eeprom_buff) < 0) { + /* Check if the chip was able to read its own configuration starting + at 0 in the EEPROM*/ + if ((readreg(dev, PP_SelfST) & (EEPROM_OK | EEPROM_PRESENT)) != + (EEPROM_OK|EEPROM_PRESENT)) + printk(KERN_WARNING "cs89x0: Extended EEPROM checksum bad and no Cirrus EEPROM, relying on command line\n"); + + } else { + /* This reads an extended EEPROM that is not documented + in the CS8900 datasheet. */ + + /* get transmission control word but keep the autonegotiation bits */ + if (!lp->auto_neg_cnf) lp->auto_neg_cnf = eeprom_buff[AUTO_NEG_CNF_OFFSET/2]; + /* Store adapter configuration */ + if (!lp->adapter_cnf) lp->adapter_cnf = eeprom_buff[ADAPTER_CNF_OFFSET/2]; + /* Store ISA configuration */ + lp->isa_config = eeprom_buff[ISA_CNF_OFFSET/2]; + dev->mem_start = eeprom_buff[PACKET_PAGE_OFFSET/2] << 8; + + /* eeprom_buff has 32-bit ints, so we can't just memcpy it */ + /* store the initial memory base address */ + for (i = 0; i < ETH_ALEN/2; i++) { + dev->dev_addr[i*2] = eeprom_buff[i]; + dev->dev_addr[i*2+1] = eeprom_buff[i] >> 8; + } + if (net_debug > 1) + printk(KERN_DEBUG "%s: new adapter_cnf: 0x%x\n", + dev->name, lp->adapter_cnf); + } + + /* allow them to force multiple transceivers. If they force multiple, autosense */ + { + int count = 0; + if (lp->force & FORCE_RJ45) {lp->adapter_cnf |= A_CNF_10B_T; count++; } + if (lp->force & FORCE_AUI) {lp->adapter_cnf |= A_CNF_AUI; count++; } + if (lp->force & FORCE_BNC) {lp->adapter_cnf |= A_CNF_10B_2; count++; } + if (count > 1) {lp->adapter_cnf |= A_CNF_MEDIA_AUTO; } + else if (lp->force & FORCE_RJ45){lp->adapter_cnf |= A_CNF_MEDIA_10B_T; } + else if (lp->force & FORCE_AUI) {lp->adapter_cnf |= A_CNF_MEDIA_AUI; } + else if (lp->force & FORCE_BNC) {lp->adapter_cnf |= A_CNF_MEDIA_10B_2; } + } + + if (net_debug > 1) + printk(KERN_DEBUG "%s: after force 0x%x, adapter_cnf=0x%x\n", + dev->name, lp->force, lp->adapter_cnf); + + /* FIXME: We don't let you set dc-dc polarity or low RX squelch from the command line: add it here */ + + /* FIXME: We don't let you set the IMM bit from the command line: add it to lp->auto_neg_cnf here */ + + /* FIXME: we don't set the Ethernet address on the command line. Use + ifconfig IFACE hw ether AABBCCDDEEFF */ + + printk(KERN_INFO "cs89x0 media %s%s%s", + (lp->adapter_cnf & A_CNF_10B_T)?"RJ-45,":"", + (lp->adapter_cnf & A_CNF_AUI)?"AUI,":"", + (lp->adapter_cnf & A_CNF_10B_2)?"BNC,":""); + + lp->irq_map = 0xffff; + + /* If this is a CS8900 then no pnp soft */ + if (lp->chip_type != CS8900 && + /* Check if the ISA IRQ has been set */ + (i = readreg(dev, PP_CS8920_ISAINT) & 0xff, + (i != 0 && i < CS8920_NO_INTS))) { + if (!dev->irq) + dev->irq = i; + } else { + i = lp->isa_config & INT_NO_MASK; + if (lp->chip_type == CS8900) { +#ifdef CONFIG_CS89x0_NONISA_IRQ + i = cs8900_irq_map[0]; +#else + /* Translate the IRQ using the IRQ mapping table. */ + if (i >= ARRAY_SIZE(cs8900_irq_map)) + printk("\ncs89x0: invalid ISA interrupt number %d\n", i); + else + i = cs8900_irq_map[i]; + + lp->irq_map = CS8900_IRQ_MAP; /* fixed IRQ map for CS8900 */ + } else { + int irq_map_buff[IRQ_MAP_LEN/2]; + + if (get_eeprom_data(dev, IRQ_MAP_EEPROM_DATA, + IRQ_MAP_LEN/2, + irq_map_buff) >= 0) { + if ((irq_map_buff[0] & 0xff) == PNP_IRQ_FRMT) + lp->irq_map = (irq_map_buff[0]>>8) | (irq_map_buff[1] << 8); + } +#endif + } + if (!dev->irq) + dev->irq = i; + } + + printk(" IRQ %d", dev->irq); + +#if ALLOW_DMA + if (lp->use_dma) { + get_dma_channel(dev); + printk(", DMA %d", dev->dma); + } + else +#endif + { + printk(", programmed I/O"); + } + + /* print the ethernet address. */ + printk(", MAC %pM", dev->dev_addr); + + dev->netdev_ops = &net_ops; + dev->watchdog_timeo = HZ; + + printk("\n"); + if (net_debug) + printk("cs89x0_probe1() successful\n"); + + retval = register_netdev(dev); + if (retval) + goto out3; + return 0; +out3: + writeword(dev->base_addr, ADD_PORT, PP_ChipID); +out2: + release_region(ioaddr & ~3, NETCARD_IO_EXTENT); +out1: + return retval; +} + + +/********************************* + * This page contains DMA routines +**********************************/ + +#if ALLOW_DMA + +#define dma_page_eq(ptr1, ptr2) ((long)(ptr1)>>17 == (long)(ptr2)>>17) + +static void +get_dma_channel(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + + if (lp->dma) { + dev->dma = lp->dma; + lp->isa_config |= ISA_RxDMA; + } else { + if ((lp->isa_config & ANY_ISA_DMA) == 0) + return; + dev->dma = lp->isa_config & DMA_NO_MASK; + if (lp->chip_type == CS8900) + dev->dma += 5; + if (dev->dma < 5 || dev->dma > 7) { + lp->isa_config &= ~ANY_ISA_DMA; + return; + } + } +} + +static void +write_dma(struct net_device *dev, int chip_type, int dma) +{ + struct net_local *lp = netdev_priv(dev); + if ((lp->isa_config & ANY_ISA_DMA) == 0) + return; + if (chip_type == CS8900) { + writereg(dev, PP_CS8900_ISADMA, dma-5); + } else { + writereg(dev, PP_CS8920_ISADMA, dma); + } +} + +static void +set_dma_cfg(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + + if (lp->use_dma) { + if ((lp->isa_config & ANY_ISA_DMA) == 0) { + if (net_debug > 3) + printk("set_dma_cfg(): no DMA\n"); + return; + } + if (lp->isa_config & ISA_RxDMA) { + lp->curr_rx_cfg |= RX_DMA_ONLY; + if (net_debug > 3) + printk("set_dma_cfg(): RX_DMA_ONLY\n"); + } else { + lp->curr_rx_cfg |= AUTO_RX_DMA; /* not that we support it... */ + if (net_debug > 3) + printk("set_dma_cfg(): AUTO_RX_DMA\n"); + } + } +} + +static int +dma_bufcfg(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + if (lp->use_dma) + return (lp->isa_config & ANY_ISA_DMA)? RX_DMA_ENBL : 0; + else + return 0; +} + +static int +dma_busctl(struct net_device *dev) +{ + int retval = 0; + struct net_local *lp = netdev_priv(dev); + if (lp->use_dma) { + if (lp->isa_config & ANY_ISA_DMA) + retval |= RESET_RX_DMA; /* Reset the DMA pointer */ + if (lp->isa_config & DMA_BURST) + retval |= DMA_BURST_MODE; /* Does ISA config specify DMA burst ? */ + if (lp->dmasize == 64) + retval |= RX_DMA_SIZE_64K; /* did they ask for 64K? */ + retval |= MEMORY_ON; /* we need memory enabled to use DMA. */ + } + return retval; +} + +static void +dma_rx(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + struct sk_buff *skb; + int status, length; + unsigned char *bp = lp->rx_dma_ptr; + + status = bp[0] + (bp[1]<<8); + length = bp[2] + (bp[3]<<8); + bp += 4; + if (net_debug > 5) { + printk( "%s: receiving DMA packet at %lx, status %x, length %x\n", + dev->name, (unsigned long)bp, status, length); + } + if ((status & RX_OK) == 0) { + count_rx_errors(status, dev); + goto skip_this_frame; + } + + /* Malloc up new buffer. */ + skb = dev_alloc_skb(length + 2); + if (skb == NULL) { + if (net_debug) /* I don't think we want to do this to a stressed system */ + printk("%s: Memory squeeze, dropping packet.\n", dev->name); + dev->stats.rx_dropped++; + + /* AKPM: advance bp to the next frame */ +skip_this_frame: + bp += (length + 3) & ~3; + if (bp >= lp->end_dma_buff) bp -= lp->dmasize*1024; + lp->rx_dma_ptr = bp; + return; + } + skb_reserve(skb, 2); /* longword align L3 header */ + + if (bp + length > lp->end_dma_buff) { + int semi_cnt = lp->end_dma_buff - bp; + memcpy(skb_put(skb,semi_cnt), bp, semi_cnt); + memcpy(skb_put(skb,length - semi_cnt), lp->dma_buff, + length - semi_cnt); + } else { + memcpy(skb_put(skb,length), bp, length); + } + bp += (length + 3) & ~3; + if (bp >= lp->end_dma_buff) bp -= lp->dmasize*1024; + lp->rx_dma_ptr = bp; + + if (net_debug > 3) { + printk( "%s: received %d byte DMA packet of type %x\n", + dev->name, length, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); + } + skb->protocol=eth_type_trans(skb,dev); + netif_rx(skb); + dev->stats.rx_packets++; + dev->stats.rx_bytes += length; +} + +#endif /* ALLOW_DMA */ + +static void __init reset_chip(struct net_device *dev) +{ +#if !defined(CONFIG_MACH_MX31ADS) +#if !defined(CS89x0_NONISA_IRQ) + struct net_local *lp = netdev_priv(dev); + int ioaddr = dev->base_addr; +#endif /* CS89x0_NONISA_IRQ */ + int reset_start_time; + + writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); + + /* wait 30 ms */ + msleep(30); + +#if !defined(CS89x0_NONISA_IRQ) + if (lp->chip_type != CS8900) { + /* Hardware problem requires PNP registers to be reconfigured after a reset */ + writeword(ioaddr, ADD_PORT, PP_CS8920_ISAINT); + outb(dev->irq, ioaddr + DATA_PORT); + outb(0, ioaddr + DATA_PORT + 1); + + writeword(ioaddr, ADD_PORT, PP_CS8920_ISAMemB); + outb((dev->mem_start >> 16) & 0xff, ioaddr + DATA_PORT); + outb((dev->mem_start >> 8) & 0xff, ioaddr + DATA_PORT + 1); + } +#endif /* CS89x0_NONISA_IRQ */ + + /* Wait until the chip is reset */ + reset_start_time = jiffies; + while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) + ; +#endif /* !CONFIG_MACH_MX31ADS */ +} + + +static void +control_dc_dc(struct net_device *dev, int on_not_off) +{ + struct net_local *lp = netdev_priv(dev); + unsigned int selfcontrol; + int timenow = jiffies; + /* control the DC to DC convertor in the SelfControl register. + Note: This is hooked up to a general purpose pin, might not + always be a DC to DC convertor. */ + + selfcontrol = HCB1_ENBL; /* Enable the HCB1 bit as an output */ + if (((lp->adapter_cnf & A_CNF_DC_DC_POLARITY) != 0) ^ on_not_off) + selfcontrol |= HCB1; + else + selfcontrol &= ~HCB1; + writereg(dev, PP_SelfCTL, selfcontrol); + + /* Wait for the DC/DC converter to power up - 500ms */ + while (jiffies - timenow < HZ) + ; +} + +#define DETECTED_NONE 0 +#define DETECTED_RJ45H 1 +#define DETECTED_RJ45F 2 +#define DETECTED_AUI 3 +#define DETECTED_BNC 4 + +static int +detect_tp(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + int timenow = jiffies; + int fdx; + + if (net_debug > 1) printk("%s: Attempting TP\n", dev->name); + + /* If connected to another full duplex capable 10-Base-T card the link pulses + seem to be lost when the auto detect bit in the LineCTL is set. + To overcome this the auto detect bit will be cleared whilst testing the + 10-Base-T interface. This would not be necessary for the sparrow chip but + is simpler to do it anyway. */ + writereg(dev, PP_LineCTL, lp->linectl &~ AUI_ONLY); + control_dc_dc(dev, 0); + + /* Delay for the hardware to work out if the TP cable is present - 150ms */ + for (timenow = jiffies; jiffies - timenow < 15; ) + ; + if ((readreg(dev, PP_LineST) & LINK_OK) == 0) + return DETECTED_NONE; + + if (lp->chip_type == CS8900) { + switch (lp->force & 0xf0) { +#if 0 + case FORCE_AUTO: + printk("%s: cs8900 doesn't autonegotiate\n",dev->name); + return DETECTED_NONE; +#endif + /* CS8900 doesn't support AUTO, change to HALF*/ + case FORCE_AUTO: + lp->force &= ~FORCE_AUTO; + lp->force |= FORCE_HALF; + break; + case FORCE_HALF: + break; + case FORCE_FULL: + writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900); + break; + } + fdx = readreg(dev, PP_TestCTL) & FDX_8900; + } else { + switch (lp->force & 0xf0) { + case FORCE_AUTO: + lp->auto_neg_cnf = AUTO_NEG_ENABLE; + break; + case FORCE_HALF: + lp->auto_neg_cnf = 0; + break; + case FORCE_FULL: + lp->auto_neg_cnf = RE_NEG_NOW | ALLOW_FDX; + break; + } + + writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK); + + if ((lp->auto_neg_cnf & AUTO_NEG_BITS) == AUTO_NEG_ENABLE) { + printk(KERN_INFO "%s: negotiating duplex...\n",dev->name); + while (readreg(dev, PP_AutoNegST) & AUTO_NEG_BUSY) { + if (jiffies - timenow > 4000) { + printk(KERN_ERR "**** Full / half duplex auto-negotiation timed out ****\n"); + break; + } + } + } + fdx = readreg(dev, PP_AutoNegST) & FDX_ACTIVE; + } + if (fdx) + return DETECTED_RJ45F; + else + return DETECTED_RJ45H; +} + +/* send a test packet - return true if carrier bits are ok */ +static int +send_test_pkt(struct net_device *dev) +{ + char test_packet[] = { 0,0,0,0,0,0, 0,0,0,0,0,0, + 0, 46, /* A 46 in network order */ + 0, 0, /* DSAP=0 & SSAP=0 fields */ + 0xf3, 0 /* Control (Test Req + P bit set) */ }; + long timenow = jiffies; + + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON); + + memcpy(test_packet, dev->dev_addr, ETH_ALEN); + memcpy(test_packet+ETH_ALEN, dev->dev_addr, ETH_ALEN); + + writeword(dev->base_addr, TX_CMD_PORT, TX_AFTER_ALL); + writeword(dev->base_addr, TX_LEN_PORT, ETH_ZLEN); + + /* Test to see if the chip has allocated memory for the packet */ + while (jiffies - timenow < 5) + if (readreg(dev, PP_BusST) & READY_FOR_TX_NOW) + break; + if (jiffies - timenow >= 5) + return 0; /* this shouldn't happen */ + + /* Write the contents of the packet */ + writewords(dev->base_addr, TX_FRAME_PORT,test_packet,(ETH_ZLEN+1) >>1); + + if (net_debug > 1) printk("Sending test packet "); + /* wait a couple of jiffies for packet to be received */ + for (timenow = jiffies; jiffies - timenow < 3; ) + ; + if ((readreg(dev, PP_TxEvent) & TX_SEND_OK_BITS) == TX_OK) { + if (net_debug > 1) printk("succeeded\n"); + return 1; + } + if (net_debug > 1) printk("failed\n"); + return 0; +} + + +static int +detect_aui(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + + if (net_debug > 1) printk("%s: Attempting AUI\n", dev->name); + control_dc_dc(dev, 0); + + writereg(dev, PP_LineCTL, (lp->linectl &~ AUTO_AUI_10BASET) | AUI_ONLY); + + if (send_test_pkt(dev)) + return DETECTED_AUI; + else + return DETECTED_NONE; +} + +static int +detect_bnc(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + + if (net_debug > 1) printk("%s: Attempting BNC\n", dev->name); + control_dc_dc(dev, 1); + + writereg(dev, PP_LineCTL, (lp->linectl &~ AUTO_AUI_10BASET) | AUI_ONLY); + + if (send_test_pkt(dev)) + return DETECTED_BNC; + else + return DETECTED_NONE; +} + + +static void +write_irq(struct net_device *dev, int chip_type, int irq) +{ + int i; + + if (chip_type == CS8900) { + /* Search the mapping table for the corresponding IRQ pin. */ + for (i = 0; i != ARRAY_SIZE(cs8900_irq_map); i++) + if (cs8900_irq_map[i] == irq) + break; + /* Not found */ + if (i == ARRAY_SIZE(cs8900_irq_map)) + i = 3; + writereg(dev, PP_CS8900_ISAINT, i); + } else { + writereg(dev, PP_CS8920_ISAINT, irq); + } +} + +/* Open/initialize the board. This is called (in the current kernel) + sometime after booting when the 'ifconfig' program is run. + + This routine should set everything up anew at each open, even + registers that "should" only need to be set once at boot, so that + there is non-reboot way to recover if something goes wrong. + */ + +/* AKPM: do we need to do any locking here? */ + +static int +net_open(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + int result = 0; + int i; + int ret; + + if (dev->irq < 2) { + /* Allow interrupts to be generated by the chip */ +/* Cirrus' release had this: */ +#if 0 + writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ ); +#endif +/* And 2.3.47 had this: */ + writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON); + + for (i = 2; i < CS8920_NO_INTS; i++) { + if ((1 << i) & lp->irq_map) { + if (request_irq(i, net_interrupt, 0, dev->name, dev) == 0) { + dev->irq = i; + write_irq(dev, lp->chip_type, i); + /* writereg(dev, PP_BufCFG, GENERATE_SW_INTERRUPT); */ + break; + } + } + } + + if (i >= CS8920_NO_INTS) { + writereg(dev, PP_BusCTL, 0); /* disable interrupts. */ + printk(KERN_ERR "cs89x0: can't get an interrupt\n"); + ret = -EAGAIN; + goto bad_out; + } + } + else + { +#ifndef CONFIG_CS89x0_NONISA_IRQ + if (((1 << dev->irq) & lp->irq_map) == 0) { + printk(KERN_ERR "%s: IRQ %d is not in our map of allowable IRQs, which is %x\n", + dev->name, dev->irq, lp->irq_map); + ret = -EAGAIN; + goto bad_out; + } +#endif +/* FIXME: Cirrus' release had this: */ + writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL)|ENABLE_IRQ ); +/* And 2.3.47 had this: */ +#if 0 + writereg(dev, PP_BusCTL, ENABLE_IRQ | MEMORY_ON); +#endif + write_irq(dev, lp->chip_type, dev->irq); + ret = request_irq(dev->irq, net_interrupt, 0, dev->name, dev); + if (ret) { + printk(KERN_ERR "cs89x0: request_irq(%d) failed\n", dev->irq); + goto bad_out; + } + } + +#if ALLOW_DMA + if (lp->use_dma) { + if (lp->isa_config & ANY_ISA_DMA) { + unsigned long flags; + lp->dma_buff = (unsigned char *)__get_dma_pages(GFP_KERNEL, + get_order(lp->dmasize * 1024)); + + if (!lp->dma_buff) { + printk(KERN_ERR "%s: cannot get %dK memory for DMA\n", dev->name, lp->dmasize); + goto release_irq; + } + if (net_debug > 1) { + printk( "%s: dma %lx %lx\n", + dev->name, + (unsigned long)lp->dma_buff, + (unsigned long)isa_virt_to_bus(lp->dma_buff)); + } + if ((unsigned long) lp->dma_buff >= MAX_DMA_ADDRESS || + !dma_page_eq(lp->dma_buff, lp->dma_buff+lp->dmasize*1024-1)) { + printk(KERN_ERR "%s: not usable as DMA buffer\n", dev->name); + goto release_irq; + } + memset(lp->dma_buff, 0, lp->dmasize * 1024); /* Why? */ + if (request_dma(dev->dma, dev->name)) { + printk(KERN_ERR "%s: cannot get dma channel %d\n", dev->name, dev->dma); + goto release_irq; + } + write_dma(dev, lp->chip_type, dev->dma); + lp->rx_dma_ptr = lp->dma_buff; + lp->end_dma_buff = lp->dma_buff + lp->dmasize*1024; + spin_lock_irqsave(&lp->lock, flags); + disable_dma(dev->dma); + clear_dma_ff(dev->dma); + set_dma_mode(dev->dma, DMA_RX_MODE); /* auto_init as well */ + set_dma_addr(dev->dma, isa_virt_to_bus(lp->dma_buff)); + set_dma_count(dev->dma, lp->dmasize*1024); + enable_dma(dev->dma); + spin_unlock_irqrestore(&lp->lock, flags); + } + } +#endif /* ALLOW_DMA */ + + /* set the Ethernet address */ + for (i=0; i < ETH_ALEN/2; i++) + writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); + + /* while we're testing the interface, leave interrupts disabled */ + writereg(dev, PP_BusCTL, MEMORY_ON); + + /* Set the LineCTL quintuplet based on adapter configuration read from EEPROM */ + if ((lp->adapter_cnf & A_CNF_EXTND_10B_2) && (lp->adapter_cnf & A_CNF_LOW_RX_SQUELCH)) + lp->linectl = LOW_RX_SQUELCH; + else + lp->linectl = 0; + + /* check to make sure that they have the "right" hardware available */ + switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) { + case A_CNF_MEDIA_10B_T: result = lp->adapter_cnf & A_CNF_10B_T; break; + case A_CNF_MEDIA_AUI: result = lp->adapter_cnf & A_CNF_AUI; break; + case A_CNF_MEDIA_10B_2: result = lp->adapter_cnf & A_CNF_10B_2; break; + default: result = lp->adapter_cnf & (A_CNF_10B_T | A_CNF_AUI | A_CNF_10B_2); + } + if (!result) { + printk(KERN_ERR "%s: EEPROM is configured for unavailable media\n", dev->name); +release_dma: +#if ALLOW_DMA + free_dma(dev->dma); +release_irq: + release_dma_buff(lp); +#endif + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) & ~(SERIAL_TX_ON | SERIAL_RX_ON)); + free_irq(dev->irq, dev); + ret = -EAGAIN; + goto bad_out; + } + + /* set the hardware to the configured choice */ + switch(lp->adapter_cnf & A_CNF_MEDIA_TYPE) { + case A_CNF_MEDIA_10B_T: + result = detect_tp(dev); + if (result==DETECTED_NONE) { + printk(KERN_WARNING "%s: 10Base-T (RJ-45) has no cable\n", dev->name); + if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ + result = DETECTED_RJ45H; /* Yes! I don't care if I see a link pulse */ + } + break; + case A_CNF_MEDIA_AUI: + result = detect_aui(dev); + if (result==DETECTED_NONE) { + printk(KERN_WARNING "%s: 10Base-5 (AUI) has no cable\n", dev->name); + if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ + result = DETECTED_AUI; /* Yes! I don't care if I see a carrrier */ + } + break; + case A_CNF_MEDIA_10B_2: + result = detect_bnc(dev); + if (result==DETECTED_NONE) { + printk(KERN_WARNING "%s: 10Base-2 (BNC) has no cable\n", dev->name); + if (lp->auto_neg_cnf & IMM_BIT) /* check "ignore missing media" bit */ + result = DETECTED_BNC; /* Yes! I don't care if I can xmit a packet */ + } + break; + case A_CNF_MEDIA_AUTO: + writereg(dev, PP_LineCTL, lp->linectl | AUTO_AUI_10BASET); + if (lp->adapter_cnf & A_CNF_10B_T) + if ((result = detect_tp(dev)) != DETECTED_NONE) + break; + if (lp->adapter_cnf & A_CNF_AUI) + if ((result = detect_aui(dev)) != DETECTED_NONE) + break; + if (lp->adapter_cnf & A_CNF_10B_2) + if ((result = detect_bnc(dev)) != DETECTED_NONE) + break; + printk(KERN_ERR "%s: no media detected\n", dev->name); + goto release_dma; + } + switch(result) { + case DETECTED_NONE: + printk(KERN_ERR "%s: no network cable attached to configured media\n", dev->name); + goto release_dma; + case DETECTED_RJ45H: + printk(KERN_INFO "%s: using half-duplex 10Base-T (RJ-45)\n", dev->name); + break; + case DETECTED_RJ45F: + printk(KERN_INFO "%s: using full-duplex 10Base-T (RJ-45)\n", dev->name); + break; + case DETECTED_AUI: + printk(KERN_INFO "%s: using 10Base-5 (AUI)\n", dev->name); + break; + case DETECTED_BNC: + printk(KERN_INFO "%s: using 10Base-2 (BNC)\n", dev->name); + break; + } + + /* Turn on both receive and transmit operations */ + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); + + /* Receive only error free packets addressed to this card */ + lp->rx_mode = 0; + writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); + + lp->curr_rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL; + + if (lp->isa_config & STREAM_TRANSFER) + lp->curr_rx_cfg |= RX_STREAM_ENBL; +#if ALLOW_DMA + set_dma_cfg(dev); +#endif + writereg(dev, PP_RxCFG, lp->curr_rx_cfg); + + writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | + TX_LATE_COL_ENBL | TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL); + + writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL | +#if ALLOW_DMA + dma_bufcfg(dev) | +#endif + TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL); + + /* now that we've got our act together, enable everything */ + writereg(dev, PP_BusCTL, ENABLE_IRQ + | (dev->mem_start?MEMORY_ON : 0) /* turn memory on */ +#if ALLOW_DMA + | dma_busctl(dev) +#endif + ); + netif_start_queue(dev); + if (net_debug > 1) + printk("cs89x0: net_open() succeeded\n"); + return 0; +bad_out: + return ret; +} + +static void net_timeout(struct net_device *dev) +{ + /* If we get here, some higher level has decided we are broken. + There should really be a "kick me" function call instead. */ + if (net_debug > 0) printk("%s: transmit timed out, %s?\n", dev->name, + tx_done(dev) ? "IRQ conflict ?" : "network cable problem"); + /* Try to restart the adaptor. */ + netif_wake_queue(dev); +} + +static netdev_tx_t net_send_packet(struct sk_buff *skb,struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + unsigned long flags; + + if (net_debug > 3) { + printk("%s: sent %d byte packet of type %x\n", + dev->name, skb->len, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); + } + + /* keep the upload from being interrupted, since we + ask the chip to start transmitting before the + whole packet has been completely uploaded. */ + + spin_lock_irqsave(&lp->lock, flags); + netif_stop_queue(dev); + + /* initiate a transmit sequence */ + writeword(dev->base_addr, TX_CMD_PORT, lp->send_cmd); + writeword(dev->base_addr, TX_LEN_PORT, skb->len); + + /* Test to see if the chip has allocated memory for the packet */ + if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { + /* + * Gasp! It hasn't. But that shouldn't happen since + * we're waiting for TxOk, so return 1 and requeue this packet. + */ + + spin_unlock_irqrestore(&lp->lock, flags); + if (net_debug) printk("cs89x0: Tx buffer not free!\n"); + return NETDEV_TX_BUSY; + } + /* Write the contents of the packet */ + writewords(dev->base_addr, TX_FRAME_PORT,skb->data,(skb->len+1) >>1); + spin_unlock_irqrestore(&lp->lock, flags); + dev->stats.tx_bytes += skb->len; + dev_kfree_skb (skb); + + /* + * We DO NOT call netif_wake_queue() here. + * We also DO NOT call netif_start_queue(). + * + * Either of these would cause another bottom half run through + * net_send_packet() before this packet has fully gone out. That causes + * us to hit the "Gasp!" above and the send is rescheduled. it runs like + * a dog. We just return and wait for the Tx completion interrupt handler + * to restart the netdevice layer + */ + + return NETDEV_TX_OK; +} + +/* The typical workload of the driver: + Handle the network interface interrupts. */ + +static irqreturn_t net_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct net_local *lp; + int ioaddr, status; + int handled = 0; + + ioaddr = dev->base_addr; + lp = netdev_priv(dev); + + /* we MUST read all the events out of the ISQ, otherwise we'll never + get interrupted again. As a consequence, we can't have any limit + on the number of times we loop in the interrupt handler. The + hardware guarantees that eventually we'll run out of events. Of + course, if you're on a slow machine, and packets are arriving + faster than you can read them off, you're screwed. Hasta la + vista, baby! */ + while ((status = readword(dev->base_addr, ISQ_PORT))) { + if (net_debug > 4)printk("%s: event=%04x\n", dev->name, status); + handled = 1; + switch(status & ISQ_EVENT_MASK) { + case ISQ_RECEIVER_EVENT: + /* Got a packet(s). */ + net_rx(dev); + break; + case ISQ_TRANSMITTER_EVENT: + dev->stats.tx_packets++; + netif_wake_queue(dev); /* Inform upper layers. */ + if ((status & ( TX_OK | + TX_LOST_CRS | + TX_SQE_ERROR | + TX_LATE_COL | + TX_16_COL)) != TX_OK) { + if ((status & TX_OK) == 0) + dev->stats.tx_errors++; + if (status & TX_LOST_CRS) + dev->stats.tx_carrier_errors++; + if (status & TX_SQE_ERROR) + dev->stats.tx_heartbeat_errors++; + if (status & TX_LATE_COL) + dev->stats.tx_window_errors++; + if (status & TX_16_COL) + dev->stats.tx_aborted_errors++; + } + break; + case ISQ_BUFFER_EVENT: + if (status & READY_FOR_TX) { + /* we tried to transmit a packet earlier, + but inexplicably ran out of buffers. + That shouldn't happen since we only ever + load one packet. Shrug. Do the right + thing anyway. */ + netif_wake_queue(dev); /* Inform upper layers. */ + } + if (status & TX_UNDERRUN) { + if (net_debug > 0) printk("%s: transmit underrun\n", dev->name); + lp->send_underrun++; + if (lp->send_underrun == 3) lp->send_cmd = TX_AFTER_381; + else if (lp->send_underrun == 6) lp->send_cmd = TX_AFTER_ALL; + /* transmit cycle is done, although + frame wasn't transmitted - this + avoids having to wait for the upper + layers to timeout on us, in the + event of a tx underrun */ + netif_wake_queue(dev); /* Inform upper layers. */ + } +#if ALLOW_DMA + if (lp->use_dma && (status & RX_DMA)) { + int count = readreg(dev, PP_DmaFrameCnt); + while(count) { + if (net_debug > 5) + printk("%s: receiving %d DMA frames\n", dev->name, count); + if (net_debug > 2 && count >1) + printk("%s: receiving %d DMA frames\n", dev->name, count); + dma_rx(dev); + if (--count == 0) + count = readreg(dev, PP_DmaFrameCnt); + if (net_debug > 2 && count > 0) + printk("%s: continuing with %d DMA frames\n", dev->name, count); + } + } +#endif + break; + case ISQ_RX_MISS_EVENT: + dev->stats.rx_missed_errors += (status >> 6); + break; + case ISQ_TX_COL_EVENT: + dev->stats.collisions += (status >> 6); + break; + } + } + return IRQ_RETVAL(handled); +} + +static void +count_rx_errors(int status, struct net_device *dev) +{ + dev->stats.rx_errors++; + if (status & RX_RUNT) + dev->stats.rx_length_errors++; + if (status & RX_EXTRA_DATA) + dev->stats.rx_length_errors++; + if ((status & RX_CRC_ERROR) && !(status & (RX_EXTRA_DATA|RX_RUNT))) + /* per str 172 */ + dev->stats.rx_crc_errors++; + if (status & RX_DRIBBLE) + dev->stats.rx_frame_errors++; +} + +/* We have a good packet(s), get it/them out of the buffers. */ +static void +net_rx(struct net_device *dev) +{ + struct sk_buff *skb; + int status, length; + + int ioaddr = dev->base_addr; + status = readword(ioaddr, RX_FRAME_PORT); + length = readword(ioaddr, RX_FRAME_PORT); + + if ((status & RX_OK) == 0) { + count_rx_errors(status, dev); + return; + } + + /* Malloc up new buffer. */ + skb = dev_alloc_skb(length + 2); + if (skb == NULL) { +#if 0 /* Again, this seems a cruel thing to do */ + printk(KERN_WARNING "%s: Memory squeeze, dropping packet.\n", dev->name); +#endif + dev->stats.rx_dropped++; + return; + } + skb_reserve(skb, 2); /* longword align L3 header */ + + readwords(ioaddr, RX_FRAME_PORT, skb_put(skb, length), length >> 1); + if (length & 1) + skb->data[length-1] = readword(ioaddr, RX_FRAME_PORT); + + if (net_debug > 3) { + printk( "%s: received %d byte packet of type %x\n", + dev->name, length, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) | skb->data[ETH_ALEN+ETH_ALEN+1]); + } + + skb->protocol=eth_type_trans(skb,dev); + netif_rx(skb); + dev->stats.rx_packets++; + dev->stats.rx_bytes += length; +} + +#if ALLOW_DMA +static void release_dma_buff(struct net_local *lp) +{ + if (lp->dma_buff) { + free_pages((unsigned long)(lp->dma_buff), get_order(lp->dmasize * 1024)); + lp->dma_buff = NULL; + } +} +#endif + +/* The inverse routine to net_open(). */ +static int +net_close(struct net_device *dev) +{ +#if ALLOW_DMA + struct net_local *lp = netdev_priv(dev); +#endif + + netif_stop_queue(dev); + + writereg(dev, PP_RxCFG, 0); + writereg(dev, PP_TxCFG, 0); + writereg(dev, PP_BufCFG, 0); + writereg(dev, PP_BusCTL, 0); + + free_irq(dev->irq, dev); + +#if ALLOW_DMA + if (lp->use_dma && lp->dma) { + free_dma(dev->dma); + release_dma_buff(lp); + } +#endif + + /* Update the statistics here. */ + return 0; +} + +/* Get the current statistics. This may be called with the card open or + closed. */ +static struct net_device_stats * +net_get_stats(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + /* Update the statistics from the device registers. */ + dev->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6); + dev->stats.collisions += (readreg(dev, PP_TxCol) >> 6); + spin_unlock_irqrestore(&lp->lock, flags); + + return &dev->stats; +} + +static void set_multicast_list(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + unsigned long flags; + + spin_lock_irqsave(&lp->lock, flags); + if(dev->flags&IFF_PROMISC) + { + lp->rx_mode = RX_ALL_ACCEPT; + } + else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) + { + /* The multicast-accept list is initialized to accept-all, and we + rely on higher-level filtering for now. */ + lp->rx_mode = RX_MULTCAST_ACCEPT; + } + else + lp->rx_mode = 0; + + writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode); + + /* in promiscuous mode, we accept errored packets, so we have to enable interrupts on them also */ + writereg(dev, PP_RxCFG, lp->curr_rx_cfg | + (lp->rx_mode == RX_ALL_ACCEPT? (RX_CRC_ERROR_ENBL|RX_RUNT_ENBL|RX_EXTRA_DATA_ENBL) : 0)); + spin_unlock_irqrestore(&lp->lock, flags); +} + + +static int set_mac_address(struct net_device *dev, void *p) +{ + int i; + struct sockaddr *addr = p; + + if (netif_running(dev)) + return -EBUSY; + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + if (net_debug) + printk("%s: Setting MAC address to %pM.\n", + dev->name, dev->dev_addr); + + /* set the Ethernet address */ + for (i=0; i < ETH_ALEN/2; i++) + writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); + + return 0; +} + +#ifdef MODULE + +static struct net_device *dev_cs89x0; + +/* + * Support the 'debug' module parm even if we're compiled for non-debug to + * avoid breaking someone's startup scripts + */ + +static int io; +static int irq; +static int debug; +static char media[8]; +static int duplex=-1; + +static int use_dma; /* These generate unused var warnings if ALLOW_DMA = 0 */ +static int dma; +static int dmasize=16; /* or 64 */ + +module_param(io, int, 0); +module_param(irq, int, 0); +module_param(debug, int, 0); +module_param_string(media, media, sizeof(media), 0); +module_param(duplex, int, 0); +module_param(dma , int, 0); +module_param(dmasize , int, 0); +module_param(use_dma , int, 0); +MODULE_PARM_DESC(io, "cs89x0 I/O base address"); +MODULE_PARM_DESC(irq, "cs89x0 IRQ number"); +#if DEBUGGING +MODULE_PARM_DESC(debug, "cs89x0 debug level (0-6)"); +#else +MODULE_PARM_DESC(debug, "(ignored)"); +#endif +MODULE_PARM_DESC(media, "Set cs89x0 adapter(s) media type(s) (rj45,bnc,aui)"); +/* No other value than -1 for duplex seems to be currently interpreted */ +MODULE_PARM_DESC(duplex, "(ignored)"); +#if ALLOW_DMA +MODULE_PARM_DESC(dma , "cs89x0 ISA DMA channel; ignored if use_dma=0"); +MODULE_PARM_DESC(dmasize , "cs89x0 DMA size in kB (16,64); ignored if use_dma=0"); +MODULE_PARM_DESC(use_dma , "cs89x0 using DMA (0-1)"); +#else +MODULE_PARM_DESC(dma , "(ignored)"); +MODULE_PARM_DESC(dmasize , "(ignored)"); +MODULE_PARM_DESC(use_dma , "(ignored)"); +#endif + +MODULE_AUTHOR("Mike Cruse, Russwll Nelson , Andrew Morton"); +MODULE_LICENSE("GPL"); + + +/* +* media=t - specify media type + or media=2 + or media=aui + or medai=auto +* duplex=0 - specify forced half/full/autonegotiate duplex +* debug=# - debug level + + +* Default Chip Configuration: + * DMA Burst = enabled + * IOCHRDY Enabled = enabled + * UseSA = enabled + * CS8900 defaults to half-duplex if not specified on command-line + * CS8920 defaults to autoneg if not specified on command-line + * Use reset defaults for other config parameters + +* Assumptions: + * media type specified is supported (circuitry is present) + * if memory address is > 1MB, then required mem decode hw is present + * if 10B-2, then agent other than driver will enable DC/DC converter + (hw or software util) + + +*/ + +int __init init_module(void) +{ + struct net_device *dev = alloc_etherdev(sizeof(struct net_local)); + struct net_local *lp; + int ret = 0; + +#if DEBUGGING + net_debug = debug; +#else + debug = 0; +#endif + if (!dev) + return -ENOMEM; + + dev->irq = irq; + dev->base_addr = io; + lp = netdev_priv(dev); + +#if ALLOW_DMA + if (use_dma) { + lp->use_dma = use_dma; + lp->dma = dma; + lp->dmasize = dmasize; + } +#endif + + spin_lock_init(&lp->lock); + + /* boy, they'd better get these right */ + if (!strcmp(media, "rj45")) + lp->adapter_cnf = A_CNF_MEDIA_10B_T | A_CNF_10B_T; + else if (!strcmp(media, "aui")) + lp->adapter_cnf = A_CNF_MEDIA_AUI | A_CNF_AUI; + else if (!strcmp(media, "bnc")) + lp->adapter_cnf = A_CNF_MEDIA_10B_2 | A_CNF_10B_2; + else + lp->adapter_cnf = A_CNF_MEDIA_10B_T | A_CNF_10B_T; + + if (duplex==-1) + lp->auto_neg_cnf = AUTO_NEG_ENABLE; + + if (io == 0) { + printk(KERN_ERR "cs89x0.c: Module autoprobing not allowed.\n"); + printk(KERN_ERR "cs89x0.c: Append io=0xNNN\n"); + ret = -EPERM; + goto out; + } else if (io <= 0x1ff) { + ret = -ENXIO; + goto out; + } + +#if ALLOW_DMA + if (use_dma && dmasize != 16 && dmasize != 64) { + printk(KERN_ERR "cs89x0.c: dma size must be either 16K or 64K, not %dK\n", dmasize); + ret = -EPERM; + goto out; + } +#endif + ret = cs89x0_probe1(dev, io, 1); + if (ret) + goto out; + + dev_cs89x0 = dev; + return 0; +out: + free_netdev(dev); + return ret; +} + +void __exit +cleanup_module(void) +{ + unregister_netdev(dev_cs89x0); + writeword(dev_cs89x0->base_addr, ADD_PORT, PP_ChipID); + release_region(dev_cs89x0->base_addr, NETCARD_IO_EXTENT); + free_netdev(dev_cs89x0); +} +#endif /* MODULE */ + +/* + * Local variables: + * version-control: t + * kept-new-versions: 5 + * c-indent-level: 8 + * tab-width: 8 + * End: + * + */ diff --git a/drivers/net/ethernet/apple/cs89x0.h b/drivers/net/ethernet/apple/cs89x0.h new file mode 100644 index 00000000000..91423b70bb4 --- /dev/null +++ b/drivers/net/ethernet/apple/cs89x0.h @@ -0,0 +1,465 @@ +/* Copyright, 1988-1992, Russell Nelson, Crynwr Software + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, version 1. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + + +#define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */ + /* offset 2h -> Model/Product Number */ + /* offset 3h -> Chip Revision Number */ + +#define PP_ISAIOB 0x0020 /* IO base address */ +#define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */ +#define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */ +#define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */ +#define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */ +#define PP_ISASOF 0x0026 /* ISA DMA offset */ +#define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */ +#define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */ +#define PP_CS8900_ISAMemB 0x002C /* Memory base */ +#define PP_CS8920_ISAMemB 0x0348 /* */ + +#define PP_ISABootBase 0x0030 /* Boot Prom base */ +#define PP_ISABootMask 0x0034 /* Boot Prom Mask */ + +/* EEPROM data and command registers */ +#define PP_EECMD 0x0040 /* NVR Interface Command register */ +#define PP_EEData 0x0042 /* NVR Interface Data Register */ +#define PP_DebugReg 0x0044 /* Debug Register */ + +#define PP_RxCFG 0x0102 /* Rx Bus config */ +#define PP_RxCTL 0x0104 /* Receive Control Register */ +#define PP_TxCFG 0x0106 /* Transmit Config Register */ +#define PP_TxCMD 0x0108 /* Transmit Command Register */ +#define PP_BufCFG 0x010A /* Bus configuration Register */ +#define PP_LineCTL 0x0112 /* Line Config Register */ +#define PP_SelfCTL 0x0114 /* Self Command Register */ +#define PP_BusCTL 0x0116 /* ISA bus control Register */ +#define PP_TestCTL 0x0118 /* Test Register */ +#define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */ + +#define PP_ISQ 0x0120 /* Interrupt Status */ +#define PP_RxEvent 0x0124 /* Rx Event Register */ +#define PP_TxEvent 0x0128 /* Tx Event Register */ +#define PP_BufEvent 0x012C /* Bus Event Register */ +#define PP_RxMiss 0x0130 /* Receive Miss Count */ +#define PP_TxCol 0x0132 /* Transmit Collision Count */ +#define PP_LineST 0x0134 /* Line State Register */ +#define PP_SelfST 0x0136 /* Self State register */ +#define PP_BusST 0x0138 /* Bus Status */ +#define PP_TDR 0x013C /* Time Domain Reflectometry */ +#define PP_AutoNegST 0x013E /* Auto Neg Status */ +#define PP_TxCommand 0x0144 /* Tx Command */ +#define PP_TxLength 0x0146 /* Tx Length */ +#define PP_LAF 0x0150 /* Hash Table */ +#define PP_IA 0x0158 /* Physical Address Register */ + +#define PP_RxStatus 0x0400 /* Receive start of frame */ +#define PP_RxLength 0x0402 /* Receive Length of frame */ +#define PP_RxFrame 0x0404 /* Receive frame pointer */ +#define PP_TxFrame 0x0A00 /* Transmit frame pointer */ + +/* Primary I/O Base Address. If no I/O base is supplied by the user, then this */ +/* can be used as the default I/O base to access the PacketPage Area. */ +#define DEFAULTIOBASE 0x0300 +#define FIRST_IO 0x020C /* First I/O port to check */ +#define LAST_IO 0x037C /* Last I/O port to check (+10h) */ +#define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */ +#define ADD_SIG 0x3000 /* Expected ID signature */ + +/* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */ +#ifdef CONFIG_MAC +#define LCSLOTBASE 0xfee00000 +#define MMIOBASE 0x40000 +#endif + +#define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */ +#define CHIP_EISA_ID_SIG_STR "0x630E" + +#ifdef IBMEIPKT +#define EISA_ID_SIG 0x4D24 /* IBM */ +#define PART_NO_SIG 0x1010 /* IBM */ +#define MONGOOSE_BIT 0x0000 /* IBM */ +#else +#define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */ +#define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */ +#define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */ +#endif + +#define PRODUCT_ID_ADD 0x0002 /* Address of product ID */ + +/* Mask to find out the types of registers */ +#define REG_TYPE_MASK 0x001F + +/* Eeprom Commands */ +#define ERSE_WR_ENBL 0x00F0 +#define ERSE_WR_DISABLE 0x0000 + +/* Defines Control/Config register quintuplet numbers */ +#define RX_BUF_CFG 0x0003 +#define RX_CONTROL 0x0005 +#define TX_CFG 0x0007 +#define TX_COMMAND 0x0009 +#define BUF_CFG 0x000B +#define LINE_CONTROL 0x0013 +#define SELF_CONTROL 0x0015 +#define BUS_CONTROL 0x0017 +#define TEST_CONTROL 0x0019 + +/* Defines Status/Count registers quintuplet numbers */ +#define RX_EVENT 0x0004 +#define TX_EVENT 0x0008 +#define BUF_EVENT 0x000C +#define RX_MISS_COUNT 0x0010 +#define TX_COL_COUNT 0x0012 +#define LINE_STATUS 0x0014 +#define SELF_STATUS 0x0016 +#define BUS_STATUS 0x0018 +#define TDR 0x001C + +/* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */ +#define SKIP_1 0x0040 +#define RX_STREAM_ENBL 0x0080 +#define RX_OK_ENBL 0x0100 +#define RX_DMA_ONLY 0x0200 +#define AUTO_RX_DMA 0x0400 +#define BUFFER_CRC 0x0800 +#define RX_CRC_ERROR_ENBL 0x1000 +#define RX_RUNT_ENBL 0x2000 +#define RX_EXTRA_DATA_ENBL 0x4000 + +/* PP_RxCTL - Receive Control bit definition - Read/write */ +#define RX_IA_HASH_ACCEPT 0x0040 +#define RX_PROM_ACCEPT 0x0080 +#define RX_OK_ACCEPT 0x0100 +#define RX_MULTCAST_ACCEPT 0x0200 +#define RX_IA_ACCEPT 0x0400 +#define RX_BROADCAST_ACCEPT 0x0800 +#define RX_BAD_CRC_ACCEPT 0x1000 +#define RX_RUNT_ACCEPT 0x2000 +#define RX_EXTRA_DATA_ACCEPT 0x4000 +#define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) +/* Default receive mode - individually addressed, broadcast, and error free */ +#define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) + +/* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */ +#define TX_LOST_CRS_ENBL 0x0040 +#define TX_SQE_ERROR_ENBL 0x0080 +#define TX_OK_ENBL 0x0100 +#define TX_LATE_COL_ENBL 0x0200 +#define TX_JBR_ENBL 0x0400 +#define TX_ANY_COL_ENBL 0x0800 +#define TX_16_COL_ENBL 0x8000 + +/* PP_TxCMD - Transmit Command bit definition - Read-only */ +#define TX_START_4_BYTES 0x0000 +#define TX_START_64_BYTES 0x0040 +#define TX_START_128_BYTES 0x0080 +#define TX_START_ALL_BYTES 0x00C0 +#define TX_FORCE 0x0100 +#define TX_ONE_COL 0x0200 +#define TX_TWO_PART_DEFF_DISABLE 0x0400 +#define TX_NO_CRC 0x1000 +#define TX_RUNT 0x2000 + +/* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */ +#define GENERATE_SW_INTERRUPT 0x0040 +#define RX_DMA_ENBL 0x0080 +#define READY_FOR_TX_ENBL 0x0100 +#define TX_UNDERRUN_ENBL 0x0200 +#define RX_MISS_ENBL 0x0400 +#define RX_128_BYTE_ENBL 0x0800 +#define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 +#define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 +#define RX_DEST_MATCH_ENBL 0x8000 + +/* PP_LineCTL - Line Control bit definition - Read/write */ +#define SERIAL_RX_ON 0x0040 +#define SERIAL_TX_ON 0x0080 +#define AUI_ONLY 0x0100 +#define AUTO_AUI_10BASET 0x0200 +#define MODIFIED_BACKOFF 0x0800 +#define NO_AUTO_POLARITY 0x1000 +#define TWO_PART_DEFDIS 0x2000 +#define LOW_RX_SQUELCH 0x4000 + +/* PP_SelfCTL - Software Self Control bit definition - Read/write */ +#define POWER_ON_RESET 0x0040 +#define SW_STOP 0x0100 +#define SLEEP_ON 0x0200 +#define AUTO_WAKEUP 0x0400 +#define HCB0_ENBL 0x1000 +#define HCB1_ENBL 0x2000 +#define HCB0 0x4000 +#define HCB1 0x8000 + +/* PP_BusCTL - ISA Bus Control bit definition - Read/write */ +#define RESET_RX_DMA 0x0040 +#define MEMORY_ON 0x0400 +#define DMA_BURST_MODE 0x0800 +#define IO_CHANNEL_READY_ON 0x1000 +#define RX_DMA_SIZE_64K 0x2000 +#define ENABLE_IRQ 0x8000 + +/* PP_TestCTL - Test Control bit definition - Read/write */ +#define LINK_OFF 0x0080 +#define ENDEC_LOOPBACK 0x0200 +#define AUI_LOOPBACK 0x0400 +#define BACKOFF_OFF 0x0800 +#define FDX_8900 0x4000 +#define FAST_TEST 0x8000 + +/* PP_RxEvent - Receive Event Bit definition - Read-only */ +#define RX_IA_HASHED 0x0040 +#define RX_DRIBBLE 0x0080 +#define RX_OK 0x0100 +#define RX_HASHED 0x0200 +#define RX_IA 0x0400 +#define RX_BROADCAST 0x0800 +#define RX_CRC_ERROR 0x1000 +#define RX_RUNT 0x2000 +#define RX_EXTRA_DATA 0x4000 + +#define HASH_INDEX_MASK 0x0FC00 + +/* PP_TxEvent - Transmit Event Bit definition - Read-only */ +#define TX_LOST_CRS 0x0040 +#define TX_SQE_ERROR 0x0080 +#define TX_OK 0x0100 +#define TX_LATE_COL 0x0200 +#define TX_JBR 0x0400 +#define TX_16_COL 0x8000 +#define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) +#define TX_COL_COUNT_MASK 0x7800 + +/* PP_BufEvent - Buffer Event Bit definition - Read-only */ +#define SW_INTERRUPT 0x0040 +#define RX_DMA 0x0080 +#define READY_FOR_TX 0x0100 +#define TX_UNDERRUN 0x0200 +#define RX_MISS 0x0400 +#define RX_128_BYTE 0x0800 +#define TX_COL_OVRFLW 0x1000 +#define RX_MISS_OVRFLW 0x2000 +#define RX_DEST_MATCH 0x8000 + +/* PP_LineST - Ethernet Line Status bit definition - Read-only */ +#define LINK_OK 0x0080 +#define AUI_ON 0x0100 +#define TENBASET_ON 0x0200 +#define POLARITY_OK 0x1000 +#define CRS_OK 0x4000 + +/* PP_SelfST - Chip Software Status bit definition */ +#define ACTIVE_33V 0x0040 +#define INIT_DONE 0x0080 +#define SI_BUSY 0x0100 +#define EEPROM_PRESENT 0x0200 +#define EEPROM_OK 0x0400 +#define EL_PRESENT 0x0800 +#define EE_SIZE_64 0x1000 + +/* PP_BusST - ISA Bus Status bit definition */ +#define TX_BID_ERROR 0x0080 +#define READY_FOR_TX_NOW 0x0100 + +/* PP_AutoNegCTL - Auto Negotiation Control bit definition */ +#define RE_NEG_NOW 0x0040 +#define ALLOW_FDX 0x0080 +#define AUTO_NEG_ENABLE 0x0100 +#define NLP_ENABLE 0x0200 +#define FORCE_FDX 0x8000 +#define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) +#define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) + +/* PP_AutoNegST - Auto Negotiation Status bit definition */ +#define AUTO_NEG_BUSY 0x0080 +#define FLP_LINK 0x0100 +#define FLP_LINK_GOOD 0x0800 +#define LINK_FAULT 0x1000 +#define HDX_ACTIVE 0x4000 +#define FDX_ACTIVE 0x8000 + +/* The following block defines the ISQ event types */ +#define ISQ_RECEIVER_EVENT 0x04 +#define ISQ_TRANSMITTER_EVENT 0x08 +#define ISQ_BUFFER_EVENT 0x0c +#define ISQ_RX_MISS_EVENT 0x10 +#define ISQ_TX_COL_EVENT 0x12 + +#define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */ +#define ISQ_HIST 16 /* small history buffer */ +#define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */ + +#define TXRXBUFSIZE 0x0600 +#define RXDMABUFSIZE 0x8000 +#define RXDMASIZE 0x4000 +#define TXRX_LENGTH_MASK 0x07FF + +/* rx options bits */ +#define RCV_WITH_RXON 1 /* Set SerRx ON */ +#define RCV_COUNTS 2 /* Use Framecnt1 */ +#define RCV_PONG 4 /* Pong respondent */ +#define RCV_DONG 8 /* Dong operation */ +#define RCV_POLLING 0x10 /* Poll RxEvent */ +#define RCV_ISQ 0x20 /* Use ISQ, int */ +#define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */ +#define RCV_DMA 0x200 /* Set RxDMA only */ +#define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */ +#define RCV_FIXED_DATA 0x800 /* Every frame same */ +#define RCV_IO 0x1000 /* Use ISA IO only */ +#define RCV_MEMORY 0x2000 /* Use ISA Memory */ + +#define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */ +#define PKT_START PP_TxFrame /* Start of packet RAM */ + +#define RX_FRAME_PORT 0x0000 +#define TX_FRAME_PORT RX_FRAME_PORT +#define TX_CMD_PORT 0x0004 +#define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */ +#define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */ +#define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */ +#define TX_LEN_PORT 0x0006 +#define ISQ_PORT 0x0008 +#define ADD_PORT 0x000A +#define DATA_PORT 0x000C + +#define EEPROM_WRITE_EN 0x00F0 +#define EEPROM_WRITE_DIS 0x0000 +#define EEPROM_WRITE_CMD 0x0100 +#define EEPROM_READ_CMD 0x0200 + +/* Receive Header */ +/* Description of header of each packet in receive area of memory */ +#define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */ +#define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */ +#define RBUF_LEN_LOW 2 /* Length of received data - low byte */ +#define RBUF_LEN_HI 3 /* Length of received data - high byte */ +#define RBUF_HEAD_LEN 4 /* Length of this header */ + +#define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */ +#define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */ + +/* for bios scan */ +/* */ +#ifdef CSDEBUG +/* use these values for debugging bios scan */ +#define BIOS_START_SEG 0x00000 +#define BIOS_OFFSET_INC 0x0010 +#else +#define BIOS_START_SEG 0x0c000 +#define BIOS_OFFSET_INC 0x0200 +#endif + +#define BIOS_LAST_OFFSET 0x0fc00 + +/* Byte offsets into the EEPROM configuration buffer */ +#define ISA_CNF_OFFSET 0x6 +#define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */ +#define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */ + + /* the assumption here is that the bits in the eeprom are generally */ + /* in the same position as those in the autonegctl register. */ + /* Of course the IMM bit is not in that register so it must be */ + /* masked out */ +#define EE_FORCE_FDX 0x8000 +#define EE_NLP_ENABLE 0x0200 +#define EE_AUTO_NEG_ENABLE 0x0100 +#define EE_ALLOW_FDX 0x0080 +#define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) + +#define IMM_BIT 0x0040 /* ignore missing media */ + +#define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) +#define A_CNF_10B_T 0x0001 +#define A_CNF_AUI 0x0002 +#define A_CNF_10B_2 0x0004 +#define A_CNF_MEDIA_TYPE 0x0070 +#define A_CNF_MEDIA_AUTO 0x0070 +#define A_CNF_MEDIA_10B_T 0x0020 +#define A_CNF_MEDIA_AUI 0x0040 +#define A_CNF_MEDIA_10B_2 0x0010 +#define A_CNF_DC_DC_POLARITY 0x0080 +#define A_CNF_NO_AUTO_POLARITY 0x2000 +#define A_CNF_LOW_RX_SQUELCH 0x4000 +#define A_CNF_EXTND_10B_2 0x8000 + +#define PACKET_PAGE_OFFSET 0x8 + +/* Bit definitions for the ISA configuration word from the EEPROM */ +#define INT_NO_MASK 0x000F +#define DMA_NO_MASK 0x0070 +#define ISA_DMA_SIZE 0x0200 +#define ISA_AUTO_RxDMA 0x0400 +#define ISA_RxDMA 0x0800 +#define DMA_BURST 0x1000 +#define STREAM_TRANSFER 0x2000 +#define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) + +/* DMA controller registers */ +#define DMA_BASE 0x00 /* DMA controller base */ +#define DMA_BASE_2 0x0C0 /* DMA controller base */ + +#define DMA_STAT 0x0D0 /* DMA controller status register */ +#define DMA_MASK 0x0D4 /* DMA controller mask register */ +#define DMA_MODE 0x0D6 /* DMA controller mode register */ +#define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */ + +/* DMA data */ +#define DMA_DISABLE 0x04 /* Disable channel n */ +#define DMA_ENABLE 0x00 /* Enable channel n */ +/* Demand transfers, incr. address, auto init, writes, ch. n */ +#define DMA_RX_MODE 0x14 +/* Demand transfers, incr. address, auto init, reads, ch. n */ +#define DMA_TX_MODE 0x18 + +#define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */ + +#define CS8900 0x0000 +#define CS8920 0x4000 +#define CS8920M 0x6000 +#define REVISON_BITS 0x1F00 +#define EEVER_NUMBER 0x12 +#define CHKSUM_LEN 0x14 +#define CHKSUM_VAL 0x0000 +#define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */ +#define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */ +#define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */ +#define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */ +#define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */ + +#define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */ + +#define PNP_ADD_PORT 0x0279 +#define PNP_WRITE_PORT 0x0A79 + +#define GET_PNP_ISA_STRUCT 0x40 +#define PNP_ISA_STRUCT_LEN 0x06 +#define PNP_CSN_CNT_OFF 0x01 +#define PNP_RD_PORT_OFF 0x02 +#define PNP_FUNCTION_OK 0x00 +#define PNP_WAKE 0x03 +#define PNP_RSRC_DATA 0x04 +#define PNP_RSRC_READY 0x01 +#define PNP_STATUS 0x05 +#define PNP_ACTIVATE 0x30 +#define PNP_CNF_IO_H 0x60 +#define PNP_CNF_IO_L 0x61 +#define PNP_CNF_INT 0x70 +#define PNP_CNF_DMA 0x74 +#define PNP_CNF_MEM 0x48 + +#define BIT0 1 +#define BIT15 0x8000 + diff --git a/drivers/net/ethernet/apple/mac89x0.c b/drivers/net/ethernet/apple/mac89x0.c new file mode 100644 index 00000000000..669b317974a --- /dev/null +++ b/drivers/net/ethernet/apple/mac89x0.c @@ -0,0 +1,634 @@ +/* mac89x0.c: A Crystal Semiconductor CS89[02]0 driver for linux. */ +/* + Written 1996 by Russell Nelson, with reference to skeleton.c + written 1993-1994 by Donald Becker. + + This software may be used and distributed according to the terms + of the GNU General Public License, incorporated herein by reference. + + The author may be reached at nelson@crynwr.com, Crynwr + Software, 11 Grant St., Potsdam, NY 13676 + + Changelog: + + Mike Cruse : mcruse@cti-ltd.com + : Changes for Linux 2.0 compatibility. + : Added dev_id parameter in net_interrupt(), + : request_irq() and free_irq(). Just NULL for now. + + Mike Cruse : Added MOD_INC_USE_COUNT and MOD_DEC_USE_COUNT macros + : in net_open() and net_close() so kerneld would know + : that the module is in use and wouldn't eject the + : driver prematurely. + + Mike Cruse : Rewrote init_module() and cleanup_module using 8390.c + : as an example. Disabled autoprobing in init_module(), + : not a good thing to do to other devices while Linux + : is running from all accounts. + + Alan Cox : Removed 1.2 support, added 2.1 extra counters. + + David Huggins-Daines + + Split this off into mac89x0.c, and gutted it of all parts which are + not relevant to the existing CS8900 cards on the Macintosh + (i.e. basically the Daynaport CS and LC cards). To be precise: + + * Removed all the media-detection stuff, because these cards are + TP-only. + + * Lobotomized the ISA interrupt bogosity, because these cards use + a hardwired NuBus interrupt and a magic ISAIRQ value in the card. + + * Basically eliminated everything not relevant to getting the + cards minimally functioning on the Macintosh. + + I might add that these cards are badly designed even from the Mac + standpoint, in that Dayna, in their infinite wisdom, used NuBus slot + I/O space and NuBus interrupts for these cards, but neglected to + provide anything even remotely resembling a NuBus ROM. Therefore we + have to probe for them in a brain-damaged ISA-like fashion. + + Arnaldo Carvalho de Melo - 11/01/2001 + check kmalloc and release the allocated memory on failure in + mac89x0_probe and in init_module + use local_irq_{save,restore}(flags) in net_get_stat, not just + local_irq_{dis,en}able() +*/ + +static char *version = +"cs89x0.c:v1.02 11/26/96 Russell Nelson \n"; + +/* ======================= configure the driver here ======================= */ + +/* use 0 for production, 1 for verification, >2 for debug */ +#ifndef NET_DEBUG +#define NET_DEBUG 0 +#endif + +/* ======================= end of configuration ======================= */ + + +/* Always include 'config.h' first in case the user wants to turn on + or override something. */ +#include + +/* + Sources: + + Crynwr packet driver epktisa. + + Crystal Semiconductor data sheets. + +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "cs89x0.h" + +static unsigned int net_debug = NET_DEBUG; + +/* Information that need to be kept for each board. */ +struct net_local { + int chip_type; /* one of: CS8900, CS8920, CS8920M */ + char chip_revision; /* revision letter of the chip ('A'...) */ + int send_cmd; /* the propercommand used to send a packet. */ + int rx_mode; + int curr_rx_cfg; + int send_underrun; /* keep track of how many underruns in a row we get */ + struct sk_buff *skb; +}; + +/* Index to functions, as function prototypes. */ + +#if 0 +extern void reset_chip(struct net_device *dev); +#endif +static int net_open(struct net_device *dev); +static int net_send_packet(struct sk_buff *skb, struct net_device *dev); +static irqreturn_t net_interrupt(int irq, void *dev_id); +static void set_multicast_list(struct net_device *dev); +static void net_rx(struct net_device *dev); +static int net_close(struct net_device *dev); +static struct net_device_stats *net_get_stats(struct net_device *dev); +static int set_mac_address(struct net_device *dev, void *addr); + + +/* Example routines you must write ;->. */ +#define tx_done(dev) 1 + +/* For reading/writing registers ISA-style */ +static inline int +readreg_io(struct net_device *dev, int portno) +{ + nubus_writew(swab16(portno), dev->base_addr + ADD_PORT); + return swab16(nubus_readw(dev->base_addr + DATA_PORT)); +} + +static inline void +writereg_io(struct net_device *dev, int portno, int value) +{ + nubus_writew(swab16(portno), dev->base_addr + ADD_PORT); + nubus_writew(swab16(value), dev->base_addr + DATA_PORT); +} + +/* These are for reading/writing registers in shared memory */ +static inline int +readreg(struct net_device *dev, int portno) +{ + return swab16(nubus_readw(dev->mem_start + portno)); +} + +static inline void +writereg(struct net_device *dev, int portno, int value) +{ + nubus_writew(swab16(value), dev->mem_start + portno); +} + +static const struct net_device_ops mac89x0_netdev_ops = { + .ndo_open = net_open, + .ndo_stop = net_close, + .ndo_start_xmit = net_send_packet, + .ndo_get_stats = net_get_stats, + .ndo_set_multicast_list = set_multicast_list, + .ndo_set_mac_address = set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = eth_change_mtu, +}; + +/* Probe for the CS8900 card in slot E. We won't bother looking + anywhere else until we have a really good reason to do so. */ +struct net_device * __init mac89x0_probe(int unit) +{ + struct net_device *dev; + static int once_is_enough; + struct net_local *lp; + static unsigned version_printed; + int i, slot; + unsigned rev_type = 0; + unsigned long ioaddr; + unsigned short sig; + int err = -ENODEV; + + if (!MACH_IS_MAC) + return ERR_PTR(-ENODEV); + + dev = alloc_etherdev(sizeof(struct net_local)); + if (!dev) + return ERR_PTR(-ENOMEM); + + if (unit >= 0) { + sprintf(dev->name, "eth%d", unit); + netdev_boot_setup_check(dev); + } + + if (once_is_enough) + goto out; + once_is_enough = 1; + + /* We might have to parameterize this later */ + slot = 0xE; + /* Get out now if there's a real NuBus card in slot E */ + if (nubus_find_slot(slot, NULL) != NULL) + goto out; + + /* The pseudo-ISA bits always live at offset 0x300 (gee, + wonder why...) */ + ioaddr = (unsigned long) + nubus_slot_addr(slot) | (((slot&0xf) << 20) + DEFAULTIOBASE); + { + unsigned long flags; + int card_present; + + local_irq_save(flags); + card_present = (hwreg_present((void*) ioaddr+4) && + hwreg_present((void*) ioaddr + DATA_PORT)); + local_irq_restore(flags); + + if (!card_present) + goto out; + } + + nubus_writew(0, ioaddr + ADD_PORT); + sig = nubus_readw(ioaddr + DATA_PORT); + if (sig != swab16(CHIP_EISA_ID_SIG)) + goto out; + + /* Initialize the net_device structure. */ + lp = netdev_priv(dev); + + /* Fill in the 'dev' fields. */ + dev->base_addr = ioaddr; + dev->mem_start = (unsigned long) + nubus_slot_addr(slot) | (((slot&0xf) << 20) + MMIOBASE); + dev->mem_end = dev->mem_start + 0x1000; + + /* Turn on shared memory */ + writereg_io(dev, PP_BusCTL, MEMORY_ON); + + /* get the chip type */ + rev_type = readreg(dev, PRODUCT_ID_ADD); + lp->chip_type = rev_type &~ REVISON_BITS; + lp->chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A'; + + /* Check the chip type and revision in order to set the correct send command + CS8920 revision C and CS8900 revision F can use the faster send. */ + lp->send_cmd = TX_AFTER_381; + if (lp->chip_type == CS8900 && lp->chip_revision >= 'F') + lp->send_cmd = TX_NOW; + if (lp->chip_type != CS8900 && lp->chip_revision >= 'C') + lp->send_cmd = TX_NOW; + + if (net_debug && version_printed++ == 0) + printk(version); + + printk(KERN_INFO "%s: cs89%c0%s rev %c found at %#8lx", + dev->name, + lp->chip_type==CS8900?'0':'2', + lp->chip_type==CS8920M?"M":"", + lp->chip_revision, + dev->base_addr); + + /* Try to read the MAC address */ + if ((readreg(dev, PP_SelfST) & (EEPROM_PRESENT | EEPROM_OK)) == 0) { + printk("\nmac89x0: No EEPROM, giving up now.\n"); + goto out1; + } else { + for (i = 0; i < ETH_ALEN; i += 2) { + /* Big-endian (why??!) */ + unsigned short s = readreg(dev, PP_IA + i); + dev->dev_addr[i] = s >> 8; + dev->dev_addr[i+1] = s & 0xff; + } + } + + dev->irq = SLOT2IRQ(slot); + + /* print the IRQ and ethernet address. */ + + printk(" IRQ %d ADDR %pM\n", dev->irq, dev->dev_addr); + + dev->netdev_ops = &mac89x0_netdev_ops; + + err = register_netdev(dev); + if (err) + goto out1; + return NULL; +out1: + nubus_writew(0, dev->base_addr + ADD_PORT); +out: + free_netdev(dev); + return ERR_PTR(err); +} + +#if 0 +/* This is useful for something, but I don't know what yet. */ +void __init reset_chip(struct net_device *dev) +{ + int reset_start_time; + + writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); + + /* wait 30 ms */ + msleep_interruptible(30); + + /* Wait until the chip is reset */ + reset_start_time = jiffies; + while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) + ; +} +#endif + +/* Open/initialize the board. This is called (in the current kernel) + sometime after booting when the 'ifconfig' program is run. + + This routine should set everything up anew at each open, even + registers that "should" only need to be set once at boot, so that + there is non-reboot way to recover if something goes wrong. + */ +static int +net_open(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + int i; + + /* Disable the interrupt for now */ + writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ); + + /* Grab the interrupt */ + if (request_irq(dev->irq, net_interrupt, 0, "cs89x0", dev)) + return -EAGAIN; + + /* Set up the IRQ - Apparently magic */ + if (lp->chip_type == CS8900) + writereg(dev, PP_CS8900_ISAINT, 0); + else + writereg(dev, PP_CS8920_ISAINT, 0); + + /* set the Ethernet address */ + for (i=0; i < ETH_ALEN/2; i++) + writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); + + /* Turn on both receive and transmit operations */ + writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); + + /* Receive only error free packets addressed to this card */ + lp->rx_mode = 0; + writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); + + lp->curr_rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL; + + writereg(dev, PP_RxCFG, lp->curr_rx_cfg); + + writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | + TX_LATE_COL_ENBL | TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL); + + writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL | + TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL); + + /* now that we've got our act together, enable everything */ + writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ); + netif_start_queue(dev); + return 0; +} + +static int +net_send_packet(struct sk_buff *skb, struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + unsigned long flags; + + if (net_debug > 3) + printk("%s: sent %d byte packet of type %x\n", + dev->name, skb->len, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) + | skb->data[ETH_ALEN+ETH_ALEN+1]); + + /* keep the upload from being interrupted, since we + ask the chip to start transmitting before the + whole packet has been completely uploaded. */ + local_irq_save(flags); + netif_stop_queue(dev); + + /* initiate a transmit sequence */ + writereg(dev, PP_TxCMD, lp->send_cmd); + writereg(dev, PP_TxLength, skb->len); + + /* Test to see if the chip has allocated memory for the packet */ + if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { + /* Gasp! It hasn't. But that shouldn't happen since + we're waiting for TxOk, so return 1 and requeue this packet. */ + local_irq_restore(flags); + return NETDEV_TX_BUSY; + } + + /* Write the contents of the packet */ + skb_copy_from_linear_data(skb, (void *)(dev->mem_start + PP_TxFrame), + skb->len+1); + + local_irq_restore(flags); + dev_kfree_skb (skb); + + return NETDEV_TX_OK; +} + +/* The typical workload of the driver: + Handle the network interface interrupts. */ +static irqreturn_t net_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct net_local *lp; + int ioaddr, status; + + if (dev == NULL) { + printk ("net_interrupt(): irq %d for unknown device.\n", irq); + return IRQ_NONE; + } + + ioaddr = dev->base_addr; + lp = netdev_priv(dev); + + /* we MUST read all the events out of the ISQ, otherwise we'll never + get interrupted again. As a consequence, we can't have any limit + on the number of times we loop in the interrupt handler. The + hardware guarantees that eventually we'll run out of events. Of + course, if you're on a slow machine, and packets are arriving + faster than you can read them off, you're screwed. Hasta la + vista, baby! */ + while ((status = swab16(nubus_readw(dev->base_addr + ISQ_PORT)))) { + if (net_debug > 4)printk("%s: event=%04x\n", dev->name, status); + switch(status & ISQ_EVENT_MASK) { + case ISQ_RECEIVER_EVENT: + /* Got a packet(s). */ + net_rx(dev); + break; + case ISQ_TRANSMITTER_EVENT: + dev->stats.tx_packets++; + netif_wake_queue(dev); + if ((status & TX_OK) == 0) + dev->stats.tx_errors++; + if (status & TX_LOST_CRS) + dev->stats.tx_carrier_errors++; + if (status & TX_SQE_ERROR) + dev->stats.tx_heartbeat_errors++; + if (status & TX_LATE_COL) + dev->stats.tx_window_errors++; + if (status & TX_16_COL) + dev->stats.tx_aborted_errors++; + break; + case ISQ_BUFFER_EVENT: + if (status & READY_FOR_TX) { + /* we tried to transmit a packet earlier, + but inexplicably ran out of buffers. + That shouldn't happen since we only ever + load one packet. Shrug. Do the right + thing anyway. */ + netif_wake_queue(dev); + } + if (status & TX_UNDERRUN) { + if (net_debug > 0) printk("%s: transmit underrun\n", dev->name); + lp->send_underrun++; + if (lp->send_underrun == 3) lp->send_cmd = TX_AFTER_381; + else if (lp->send_underrun == 6) lp->send_cmd = TX_AFTER_ALL; + } + break; + case ISQ_RX_MISS_EVENT: + dev->stats.rx_missed_errors += (status >> 6); + break; + case ISQ_TX_COL_EVENT: + dev->stats.collisions += (status >> 6); + break; + } + } + return IRQ_HANDLED; +} + +/* We have a good packet(s), get it/them out of the buffers. */ +static void +net_rx(struct net_device *dev) +{ + struct sk_buff *skb; + int status, length; + + status = readreg(dev, PP_RxStatus); + if ((status & RX_OK) == 0) { + dev->stats.rx_errors++; + if (status & RX_RUNT) + dev->stats.rx_length_errors++; + if (status & RX_EXTRA_DATA) + dev->stats.rx_length_errors++; + if ((status & RX_CRC_ERROR) && + !(status & (RX_EXTRA_DATA|RX_RUNT))) + /* per str 172 */ + dev->stats.rx_crc_errors++; + if (status & RX_DRIBBLE) + dev->stats.rx_frame_errors++; + return; + } + + length = readreg(dev, PP_RxLength); + /* Malloc up new buffer. */ + skb = alloc_skb(length, GFP_ATOMIC); + if (skb == NULL) { + printk("%s: Memory squeeze, dropping packet.\n", dev->name); + dev->stats.rx_dropped++; + return; + } + skb_put(skb, length); + + skb_copy_to_linear_data(skb, (void *)(dev->mem_start + PP_RxFrame), + length); + + if (net_debug > 3)printk("%s: received %d byte packet of type %x\n", + dev->name, length, + (skb->data[ETH_ALEN+ETH_ALEN] << 8) + | skb->data[ETH_ALEN+ETH_ALEN+1]); + + skb->protocol=eth_type_trans(skb,dev); + netif_rx(skb); + dev->stats.rx_packets++; + dev->stats.rx_bytes += length; +} + +/* The inverse routine to net_open(). */ +static int +net_close(struct net_device *dev) +{ + + writereg(dev, PP_RxCFG, 0); + writereg(dev, PP_TxCFG, 0); + writereg(dev, PP_BufCFG, 0); + writereg(dev, PP_BusCTL, 0); + + netif_stop_queue(dev); + + free_irq(dev->irq, dev); + + /* Update the statistics here. */ + + return 0; + +} + +/* Get the current statistics. This may be called with the card open or + closed. */ +static struct net_device_stats * +net_get_stats(struct net_device *dev) +{ + unsigned long flags; + + local_irq_save(flags); + /* Update the statistics from the device registers. */ + dev->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6); + dev->stats.collisions += (readreg(dev, PP_TxCol) >> 6); + local_irq_restore(flags); + + return &dev->stats; +} + +static void set_multicast_list(struct net_device *dev) +{ + struct net_local *lp = netdev_priv(dev); + + if(dev->flags&IFF_PROMISC) + { + lp->rx_mode = RX_ALL_ACCEPT; + } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) { + /* The multicast-accept list is initialized to accept-all, and we + rely on higher-level filtering for now. */ + lp->rx_mode = RX_MULTCAST_ACCEPT; + } + else + lp->rx_mode = 0; + + writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode); + + /* in promiscuous mode, we accept errored packets, so we have to enable interrupts on them also */ + writereg(dev, PP_RxCFG, lp->curr_rx_cfg | + (lp->rx_mode == RX_ALL_ACCEPT? (RX_CRC_ERROR_ENBL|RX_RUNT_ENBL|RX_EXTRA_DATA_ENBL) : 0)); +} + + +static int set_mac_address(struct net_device *dev, void *addr) +{ + int i; + printk("%s: Setting MAC address to ", dev->name); + for (i = 0; i < 6; i++) + printk(" %2.2x", dev->dev_addr[i] = ((unsigned char *)addr)[i]); + printk(".\n"); + /* set the Ethernet address */ + for (i=0; i < ETH_ALEN/2; i++) + writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); + + return 0; +} + +#ifdef MODULE + +static struct net_device *dev_cs89x0; +static int debug; + +module_param(debug, int, 0); +MODULE_PARM_DESC(debug, "CS89[02]0 debug level (0-5)"); +MODULE_LICENSE("GPL"); + +int __init +init_module(void) +{ + net_debug = debug; + dev_cs89x0 = mac89x0_probe(-1); + if (IS_ERR(dev_cs89x0)) { + printk(KERN_WARNING "mac89x0.c: No card found\n"); + return PTR_ERR(dev_cs89x0); + } + return 0; +} + +void +cleanup_module(void) +{ + unregister_netdev(dev_cs89x0); + nubus_writew(0, dev_cs89x0->base_addr + ADD_PORT); + free_netdev(dev_cs89x0); +} +#endif /* MODULE */ diff --git a/drivers/net/ethernet/apple/mace.c b/drivers/net/ethernet/apple/mace.c new file mode 100644 index 00000000000..2074e9724ba --- /dev/null +++ b/drivers/net/ethernet/apple/mace.c @@ -0,0 +1,1031 @@ +/* + * Network device driver for the MACE ethernet controller on + * Apple Powermacs. Assumes it's under a DBDMA controller. + * + * Copyright (C) 1996 Paul Mackerras. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mace.h" + +static int port_aaui = -1; + +#define N_RX_RING 8 +#define N_TX_RING 6 +#define MAX_TX_ACTIVE 1 +#define NCMDS_TX 1 /* dma commands per element in tx ring */ +#define RX_BUFLEN (ETH_FRAME_LEN + 8) +#define TX_TIMEOUT HZ /* 1 second */ + +/* Chip rev needs workaround on HW & multicast addr change */ +#define BROKEN_ADDRCHG_REV 0x0941 + +/* Bits in transmit DMA status */ +#define TX_DMA_ERR 0x80 + +struct mace_data { + volatile struct mace __iomem *mace; + volatile struct dbdma_regs __iomem *tx_dma; + int tx_dma_intr; + volatile struct dbdma_regs __iomem *rx_dma; + int rx_dma_intr; + volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ + volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ + struct sk_buff *rx_bufs[N_RX_RING]; + int rx_fill; + int rx_empty; + struct sk_buff *tx_bufs[N_TX_RING]; + int tx_fill; + int tx_empty; + unsigned char maccc; + unsigned char tx_fullup; + unsigned char tx_active; + unsigned char tx_bad_runt; + struct timer_list tx_timeout; + int timeout_active; + int port_aaui; + int chipid; + struct macio_dev *mdev; + spinlock_t lock; +}; + +/* + * Number of bytes of private data per MACE: allow enough for + * the rx and tx dma commands plus a branch dma command each, + * and another 16 bytes to allow us to align the dma command + * buffers on a 16 byte boundary. + */ +#define PRIV_BYTES (sizeof(struct mace_data) \ + + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd)) + +static int mace_open(struct net_device *dev); +static int mace_close(struct net_device *dev); +static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); +static void mace_set_multicast(struct net_device *dev); +static void mace_reset(struct net_device *dev); +static int mace_set_address(struct net_device *dev, void *addr); +static irqreturn_t mace_interrupt(int irq, void *dev_id); +static irqreturn_t mace_txdma_intr(int irq, void *dev_id); +static irqreturn_t mace_rxdma_intr(int irq, void *dev_id); +static void mace_set_timeout(struct net_device *dev); +static void mace_tx_timeout(unsigned long data); +static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma); +static inline void mace_clean_rings(struct mace_data *mp); +static void __mace_set_address(struct net_device *dev, void *addr); + +/* + * If we can't get a skbuff when we need it, we use this area for DMA. + */ +static unsigned char *dummy_buf; + +static const struct net_device_ops mace_netdev_ops = { + .ndo_open = mace_open, + .ndo_stop = mace_close, + .ndo_start_xmit = mace_xmit_start, + .ndo_set_multicast_list = mace_set_multicast, + .ndo_set_mac_address = mace_set_address, + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, +}; + +static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match) +{ + struct device_node *mace = macio_get_of_node(mdev); + struct net_device *dev; + struct mace_data *mp; + const unsigned char *addr; + int j, rev, rc = -EBUSY; + + if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { + printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n", + mace->full_name); + return -ENODEV; + } + + addr = of_get_property(mace, "mac-address", NULL); + if (addr == NULL) { + addr = of_get_property(mace, "local-mac-address", NULL); + if (addr == NULL) { + printk(KERN_ERR "Can't get mac-address for MACE %s\n", + mace->full_name); + return -ENODEV; + } + } + + /* + * lazy allocate the driver-wide dummy buffer. (Note that we + * never have more than one MACE in the system anyway) + */ + if (dummy_buf == NULL) { + dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL); + if (dummy_buf == NULL) { + printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n"); + return -ENOMEM; + } + } + + if (macio_request_resources(mdev, "mace")) { + printk(KERN_ERR "MACE: can't request IO resources !\n"); + return -EBUSY; + } + + dev = alloc_etherdev(PRIV_BYTES); + if (!dev) { + printk(KERN_ERR "MACE: can't allocate ethernet device !\n"); + rc = -ENOMEM; + goto err_release; + } + SET_NETDEV_DEV(dev, &mdev->ofdev.dev); + + mp = netdev_priv(dev); + mp->mdev = mdev; + macio_set_drvdata(mdev, dev); + + dev->base_addr = macio_resource_start(mdev, 0); + mp->mace = ioremap(dev->base_addr, 0x1000); + if (mp->mace == NULL) { + printk(KERN_ERR "MACE: can't map IO resources !\n"); + rc = -ENOMEM; + goto err_free; + } + dev->irq = macio_irq(mdev, 0); + + rev = addr[0] == 0 && addr[1] == 0xA0; + for (j = 0; j < 6; ++j) { + dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; + } + mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | + in_8(&mp->mace->chipid_lo); + + + mp = netdev_priv(dev); + mp->maccc = ENXMT | ENRCV; + + mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000); + if (mp->tx_dma == NULL) { + printk(KERN_ERR "MACE: can't map TX DMA resources !\n"); + rc = -ENOMEM; + goto err_unmap_io; + } + mp->tx_dma_intr = macio_irq(mdev, 1); + + mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000); + if (mp->rx_dma == NULL) { + printk(KERN_ERR "MACE: can't map RX DMA resources !\n"); + rc = -ENOMEM; + goto err_unmap_tx_dma; + } + mp->rx_dma_intr = macio_irq(mdev, 2); + + mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1); + mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1; + + memset((char *) mp->tx_cmds, 0, + (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd)); + init_timer(&mp->tx_timeout); + spin_lock_init(&mp->lock); + mp->timeout_active = 0; + + if (port_aaui >= 0) + mp->port_aaui = port_aaui; + else { + /* Apple Network Server uses the AAUI port */ + if (of_machine_is_compatible("AAPL,ShinerESB")) + mp->port_aaui = 1; + else { +#ifdef CONFIG_MACE_AAUI_PORT + mp->port_aaui = 1; +#else + mp->port_aaui = 0; +#endif + } + } + + dev->netdev_ops = &mace_netdev_ops; + + /* + * Most of what is below could be moved to mace_open() + */ + mace_reset(dev); + + rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev); + if (rc) { + printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq); + goto err_unmap_rx_dma; + } + rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev); + if (rc) { + printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr); + goto err_free_irq; + } + rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev); + if (rc) { + printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr); + goto err_free_tx_irq; + } + + rc = register_netdev(dev); + if (rc) { + printk(KERN_ERR "MACE: Cannot register net device, aborting.\n"); + goto err_free_rx_irq; + } + + printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n", + dev->name, dev->dev_addr, + mp->chipid >> 8, mp->chipid & 0xff); + + return 0; + + err_free_rx_irq: + free_irq(macio_irq(mdev, 2), dev); + err_free_tx_irq: + free_irq(macio_irq(mdev, 1), dev); + err_free_irq: + free_irq(macio_irq(mdev, 0), dev); + err_unmap_rx_dma: + iounmap(mp->rx_dma); + err_unmap_tx_dma: + iounmap(mp->tx_dma); + err_unmap_io: + iounmap(mp->mace); + err_free: + free_netdev(dev); + err_release: + macio_release_resources(mdev); + + return rc; +} + +static int __devexit mace_remove(struct macio_dev *mdev) +{ + struct net_device *dev = macio_get_drvdata(mdev); + struct mace_data *mp; + + BUG_ON(dev == NULL); + + macio_set_drvdata(mdev, NULL); + + mp = netdev_priv(dev); + + unregister_netdev(dev); + + free_irq(dev->irq, dev); + free_irq(mp->tx_dma_intr, dev); + free_irq(mp->rx_dma_intr, dev); + + iounmap(mp->rx_dma); + iounmap(mp->tx_dma); + iounmap(mp->mace); + + free_netdev(dev); + + macio_release_resources(mdev); + + return 0; +} + +static void dbdma_reset(volatile struct dbdma_regs __iomem *dma) +{ + int i; + + out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); + + /* + * Yes this looks peculiar, but apparently it needs to be this + * way on some machines. + */ + for (i = 200; i > 0; --i) + if (ld_le32(&dma->control) & RUN) + udelay(1); +} + +static void mace_reset(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + int i; + + /* soft-reset the chip */ + i = 200; + while (--i) { + out_8(&mb->biucc, SWRST); + if (in_8(&mb->biucc) & SWRST) { + udelay(10); + continue; + } + break; + } + if (!i) { + printk(KERN_ERR "mace: cannot reset chip!\n"); + return; + } + + out_8(&mb->imr, 0xff); /* disable all intrs for now */ + i = in_8(&mb->ir); + out_8(&mb->maccc, 0); /* turn off tx, rx */ + + out_8(&mb->biucc, XMTSP_64); + out_8(&mb->utr, RTRD); + out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); + out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ + out_8(&mb->rcvfc, 0); + + /* load up the hardware address */ + __mace_set_address(dev, dev->dev_addr); + + /* clear the multicast filter */ + if (mp->chipid == BROKEN_ADDRCHG_REV) + out_8(&mb->iac, LOGADDR); + else { + out_8(&mb->iac, ADDRCHG | LOGADDR); + while ((in_8(&mb->iac) & ADDRCHG) != 0) + ; + } + for (i = 0; i < 8; ++i) + out_8(&mb->ladrf, 0); + + /* done changing address */ + if (mp->chipid != BROKEN_ADDRCHG_REV) + out_8(&mb->iac, 0); + + if (mp->port_aaui) + out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO); + else + out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO); +} + +static void __mace_set_address(struct net_device *dev, void *addr) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + unsigned char *p = addr; + int i; + + /* load up the hardware address */ + if (mp->chipid == BROKEN_ADDRCHG_REV) + out_8(&mb->iac, PHYADDR); + else { + out_8(&mb->iac, ADDRCHG | PHYADDR); + while ((in_8(&mb->iac) & ADDRCHG) != 0) + ; + } + for (i = 0; i < 6; ++i) + out_8(&mb->padr, dev->dev_addr[i] = p[i]); + if (mp->chipid != BROKEN_ADDRCHG_REV) + out_8(&mb->iac, 0); +} + +static int mace_set_address(struct net_device *dev, void *addr) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + unsigned long flags; + + spin_lock_irqsave(&mp->lock, flags); + + __mace_set_address(dev, addr); + + /* note: setting ADDRCHG clears ENRCV */ + out_8(&mb->maccc, mp->maccc); + + spin_unlock_irqrestore(&mp->lock, flags); + return 0; +} + +static inline void mace_clean_rings(struct mace_data *mp) +{ + int i; + + /* free some skb's */ + for (i = 0; i < N_RX_RING; ++i) { + if (mp->rx_bufs[i] != NULL) { + dev_kfree_skb(mp->rx_bufs[i]); + mp->rx_bufs[i] = NULL; + } + } + for (i = mp->tx_empty; i != mp->tx_fill; ) { + dev_kfree_skb(mp->tx_bufs[i]); + if (++i >= N_TX_RING) + i = 0; + } +} + +static int mace_open(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + volatile struct dbdma_regs __iomem *rd = mp->rx_dma; + volatile struct dbdma_regs __iomem *td = mp->tx_dma; + volatile struct dbdma_cmd *cp; + int i; + struct sk_buff *skb; + unsigned char *data; + + /* reset the chip */ + mace_reset(dev); + + /* initialize list of sk_buffs for receiving and set up recv dma */ + mace_clean_rings(mp); + memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd)); + cp = mp->rx_cmds; + for (i = 0; i < N_RX_RING - 1; ++i) { + skb = dev_alloc_skb(RX_BUFLEN + 2); + if (!skb) { + data = dummy_buf; + } else { + skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */ + data = skb->data; + } + mp->rx_bufs[i] = skb; + st_le16(&cp->req_count, RX_BUFLEN); + st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); + st_le32(&cp->phy_addr, virt_to_bus(data)); + cp->xfer_status = 0; + ++cp; + } + mp->rx_bufs[i] = NULL; + st_le16(&cp->command, DBDMA_STOP); + mp->rx_fill = i; + mp->rx_empty = 0; + + /* Put a branch back to the beginning of the receive command list */ + ++cp; + st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); + st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds)); + + /* start rx dma */ + out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ + out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds)); + out_le32(&rd->control, (RUN << 16) | RUN); + + /* put a branch at the end of the tx command list */ + cp = mp->tx_cmds + NCMDS_TX * N_TX_RING; + st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); + st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds)); + + /* reset tx dma */ + out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); + out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds)); + mp->tx_fill = 0; + mp->tx_empty = 0; + mp->tx_fullup = 0; + mp->tx_active = 0; + mp->tx_bad_runt = 0; + + /* turn it on! */ + out_8(&mb->maccc, mp->maccc); + /* enable all interrupts except receive interrupts */ + out_8(&mb->imr, RCVINT); + + return 0; +} + +static int mace_close(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + volatile struct dbdma_regs __iomem *rd = mp->rx_dma; + volatile struct dbdma_regs __iomem *td = mp->tx_dma; + + /* disable rx and tx */ + out_8(&mb->maccc, 0); + out_8(&mb->imr, 0xff); /* disable all intrs */ + + /* disable rx and tx dma */ + st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ + st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ + + mace_clean_rings(mp); + + return 0; +} + +static inline void mace_set_timeout(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + + if (mp->timeout_active) + del_timer(&mp->tx_timeout); + mp->tx_timeout.expires = jiffies + TX_TIMEOUT; + mp->tx_timeout.function = mace_tx_timeout; + mp->tx_timeout.data = (unsigned long) dev; + add_timer(&mp->tx_timeout); + mp->timeout_active = 1; +} + +static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *td = mp->tx_dma; + volatile struct dbdma_cmd *cp, *np; + unsigned long flags; + int fill, next, len; + + /* see if there's a free slot in the tx ring */ + spin_lock_irqsave(&mp->lock, flags); + fill = mp->tx_fill; + next = fill + 1; + if (next >= N_TX_RING) + next = 0; + if (next == mp->tx_empty) { + netif_stop_queue(dev); + mp->tx_fullup = 1; + spin_unlock_irqrestore(&mp->lock, flags); + return NETDEV_TX_BUSY; /* can't take it at the moment */ + } + spin_unlock_irqrestore(&mp->lock, flags); + + /* partially fill in the dma command block */ + len = skb->len; + if (len > ETH_FRAME_LEN) { + printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len); + len = ETH_FRAME_LEN; + } + mp->tx_bufs[fill] = skb; + cp = mp->tx_cmds + NCMDS_TX * fill; + st_le16(&cp->req_count, len); + st_le32(&cp->phy_addr, virt_to_bus(skb->data)); + + np = mp->tx_cmds + NCMDS_TX * next; + out_le16(&np->command, DBDMA_STOP); + + /* poke the tx dma channel */ + spin_lock_irqsave(&mp->lock, flags); + mp->tx_fill = next; + if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) { + out_le16(&cp->xfer_status, 0); + out_le16(&cp->command, OUTPUT_LAST); + out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); + ++mp->tx_active; + mace_set_timeout(dev); + } + if (++next >= N_TX_RING) + next = 0; + if (next == mp->tx_empty) + netif_stop_queue(dev); + spin_unlock_irqrestore(&mp->lock, flags); + + return NETDEV_TX_OK; +} + +static void mace_set_multicast(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + int i; + u32 crc; + unsigned long flags; + + spin_lock_irqsave(&mp->lock, flags); + mp->maccc &= ~PROM; + if (dev->flags & IFF_PROMISC) { + mp->maccc |= PROM; + } else { + unsigned char multicast_filter[8]; + struct netdev_hw_addr *ha; + + if (dev->flags & IFF_ALLMULTI) { + for (i = 0; i < 8; i++) + multicast_filter[i] = 0xff; + } else { + for (i = 0; i < 8; i++) + multicast_filter[i] = 0; + netdev_for_each_mc_addr(ha, dev) { + crc = ether_crc_le(6, ha->addr); + i = crc >> 26; /* bit number in multicast_filter */ + multicast_filter[i >> 3] |= 1 << (i & 7); + } + } +#if 0 + printk("Multicast filter :"); + for (i = 0; i < 8; i++) + printk("%02x ", multicast_filter[i]); + printk("\n"); +#endif + + if (mp->chipid == BROKEN_ADDRCHG_REV) + out_8(&mb->iac, LOGADDR); + else { + out_8(&mb->iac, ADDRCHG | LOGADDR); + while ((in_8(&mb->iac) & ADDRCHG) != 0) + ; + } + for (i = 0; i < 8; ++i) + out_8(&mb->ladrf, multicast_filter[i]); + if (mp->chipid != BROKEN_ADDRCHG_REV) + out_8(&mb->iac, 0); + } + /* reset maccc */ + out_8(&mb->maccc, mp->maccc); + spin_unlock_irqrestore(&mp->lock, flags); +} + +static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev) +{ + volatile struct mace __iomem *mb = mp->mace; + static int mace_babbles, mace_jabbers; + + if (intr & MPCO) + dev->stats.rx_missed_errors += 256; + dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */ + if (intr & RNTPCO) + dev->stats.rx_length_errors += 256; + dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */ + if (intr & CERR) + ++dev->stats.tx_heartbeat_errors; + if (intr & BABBLE) + if (mace_babbles++ < 4) + printk(KERN_DEBUG "mace: babbling transmitter\n"); + if (intr & JABBER) + if (mace_jabbers++ < 4) + printk(KERN_DEBUG "mace: jabbering transceiver\n"); +} + +static irqreturn_t mace_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + volatile struct dbdma_regs __iomem *td = mp->tx_dma; + volatile struct dbdma_cmd *cp; + int intr, fs, i, stat, x; + int xcount, dstat; + unsigned long flags; + /* static int mace_last_fs, mace_last_xcount; */ + + spin_lock_irqsave(&mp->lock, flags); + intr = in_8(&mb->ir); /* read interrupt register */ + in_8(&mb->xmtrc); /* get retries */ + mace_handle_misc_intrs(mp, intr, dev); + + i = mp->tx_empty; + while (in_8(&mb->pr) & XMTSV) { + del_timer(&mp->tx_timeout); + mp->timeout_active = 0; + /* + * Clear any interrupt indication associated with this status + * word. This appears to unlatch any error indication from + * the DMA controller. + */ + intr = in_8(&mb->ir); + if (intr != 0) + mace_handle_misc_intrs(mp, intr, dev); + if (mp->tx_bad_runt) { + fs = in_8(&mb->xmtfs); + mp->tx_bad_runt = 0; + out_8(&mb->xmtfc, AUTO_PAD_XMIT); + continue; + } + dstat = ld_le32(&td->status); + /* stop DMA controller */ + out_le32(&td->control, RUN << 16); + /* + * xcount is the number of complete frames which have been + * written to the fifo but for which status has not been read. + */ + xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; + if (xcount == 0 || (dstat & DEAD)) { + /* + * If a packet was aborted before the DMA controller has + * finished transferring it, it seems that there are 2 bytes + * which are stuck in some buffer somewhere. These will get + * transmitted as soon as we read the frame status (which + * reenables the transmit data transfer request). Turning + * off the DMA controller and/or resetting the MACE doesn't + * help. So we disable auto-padding and FCS transmission + * so the two bytes will only be a runt packet which should + * be ignored by other stations. + */ + out_8(&mb->xmtfc, DXMTFCS); + } + fs = in_8(&mb->xmtfs); + if ((fs & XMTSV) == 0) { + printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n", + fs, xcount, dstat); + mace_reset(dev); + /* + * XXX mace likes to hang the machine after a xmtfs error. + * This is hard to reproduce, reseting *may* help + */ + } + cp = mp->tx_cmds + NCMDS_TX * i; + stat = ld_le16(&cp->xfer_status); + if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) { + /* + * Check whether there were in fact 2 bytes written to + * the transmit FIFO. + */ + udelay(1); + x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; + if (x != 0) { + /* there were two bytes with an end-of-packet indication */ + mp->tx_bad_runt = 1; + mace_set_timeout(dev); + } else { + /* + * Either there weren't the two bytes buffered up, or they + * didn't have an end-of-packet indication. + * We flush the transmit FIFO just in case (by setting the + * XMTFWU bit with the transmitter disabled). + */ + out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT); + out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU); + udelay(1); + out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT); + out_8(&mb->xmtfc, AUTO_PAD_XMIT); + } + } + /* dma should have finished */ + if (i == mp->tx_fill) { + printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n", + fs, xcount, dstat); + continue; + } + /* Update stats */ + if (fs & (UFLO|LCOL|LCAR|RTRY)) { + ++dev->stats.tx_errors; + if (fs & LCAR) + ++dev->stats.tx_carrier_errors; + if (fs & (UFLO|LCOL|RTRY)) + ++dev->stats.tx_aborted_errors; + } else { + dev->stats.tx_bytes += mp->tx_bufs[i]->len; + ++dev->stats.tx_packets; + } + dev_kfree_skb_irq(mp->tx_bufs[i]); + --mp->tx_active; + if (++i >= N_TX_RING) + i = 0; +#if 0 + mace_last_fs = fs; + mace_last_xcount = xcount; +#endif + } + + if (i != mp->tx_empty) { + mp->tx_fullup = 0; + netif_wake_queue(dev); + } + mp->tx_empty = i; + i += mp->tx_active; + if (i >= N_TX_RING) + i -= N_TX_RING; + if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) { + do { + /* set up the next one */ + cp = mp->tx_cmds + NCMDS_TX * i; + out_le16(&cp->xfer_status, 0); + out_le16(&cp->command, OUTPUT_LAST); + ++mp->tx_active; + if (++i >= N_TX_RING) + i = 0; + } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE); + out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); + mace_set_timeout(dev); + } + spin_unlock_irqrestore(&mp->lock, flags); + return IRQ_HANDLED; +} + +static void mace_tx_timeout(unsigned long data) +{ + struct net_device *dev = (struct net_device *) data; + struct mace_data *mp = netdev_priv(dev); + volatile struct mace __iomem *mb = mp->mace; + volatile struct dbdma_regs __iomem *td = mp->tx_dma; + volatile struct dbdma_regs __iomem *rd = mp->rx_dma; + volatile struct dbdma_cmd *cp; + unsigned long flags; + int i; + + spin_lock_irqsave(&mp->lock, flags); + mp->timeout_active = 0; + if (mp->tx_active == 0 && !mp->tx_bad_runt) + goto out; + + /* update various counters */ + mace_handle_misc_intrs(mp, in_8(&mb->ir), dev); + + cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty; + + /* turn off both tx and rx and reset the chip */ + out_8(&mb->maccc, 0); + printk(KERN_ERR "mace: transmit timeout - resetting\n"); + dbdma_reset(td); + mace_reset(dev); + + /* restart rx dma */ + cp = bus_to_virt(ld_le32(&rd->cmdptr)); + dbdma_reset(rd); + out_le16(&cp->xfer_status, 0); + out_le32(&rd->cmdptr, virt_to_bus(cp)); + out_le32(&rd->control, (RUN << 16) | RUN); + + /* fix up the transmit side */ + i = mp->tx_empty; + mp->tx_active = 0; + ++dev->stats.tx_errors; + if (mp->tx_bad_runt) { + mp->tx_bad_runt = 0; + } else if (i != mp->tx_fill) { + dev_kfree_skb(mp->tx_bufs[i]); + if (++i >= N_TX_RING) + i = 0; + mp->tx_empty = i; + } + mp->tx_fullup = 0; + netif_wake_queue(dev); + if (i != mp->tx_fill) { + cp = mp->tx_cmds + NCMDS_TX * i; + out_le16(&cp->xfer_status, 0); + out_le16(&cp->command, OUTPUT_LAST); + out_le32(&td->cmdptr, virt_to_bus(cp)); + out_le32(&td->control, (RUN << 16) | RUN); + ++mp->tx_active; + mace_set_timeout(dev); + } + + /* turn it back on */ + out_8(&mb->imr, RCVINT); + out_8(&mb->maccc, mp->maccc); + +out: + spin_unlock_irqrestore(&mp->lock, flags); +} + +static irqreturn_t mace_txdma_intr(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static irqreturn_t mace_rxdma_intr(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct mace_data *mp = netdev_priv(dev); + volatile struct dbdma_regs __iomem *rd = mp->rx_dma; + volatile struct dbdma_cmd *cp, *np; + int i, nb, stat, next; + struct sk_buff *skb; + unsigned frame_status; + static int mace_lost_status; + unsigned char *data; + unsigned long flags; + + spin_lock_irqsave(&mp->lock, flags); + for (i = mp->rx_empty; i != mp->rx_fill; ) { + cp = mp->rx_cmds + i; + stat = ld_le16(&cp->xfer_status); + if ((stat & ACTIVE) == 0) { + next = i + 1; + if (next >= N_RX_RING) + next = 0; + np = mp->rx_cmds + next; + if (next != mp->rx_fill && + (ld_le16(&np->xfer_status) & ACTIVE) != 0) { + printk(KERN_DEBUG "mace: lost a status word\n"); + ++mace_lost_status; + } else + break; + } + nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count); + out_le16(&cp->command, DBDMA_STOP); + /* got a packet, have a look at it */ + skb = mp->rx_bufs[i]; + if (!skb) { + ++dev->stats.rx_dropped; + } else if (nb > 8) { + data = skb->data; + frame_status = (data[nb-3] << 8) + data[nb-4]; + if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) { + ++dev->stats.rx_errors; + if (frame_status & RS_OFLO) + ++dev->stats.rx_over_errors; + if (frame_status & RS_FRAMERR) + ++dev->stats.rx_frame_errors; + if (frame_status & RS_FCSERR) + ++dev->stats.rx_crc_errors; + } else { + /* Mace feature AUTO_STRIP_RCV is on by default, dropping the + * FCS on frames with 802.3 headers. This means that Ethernet + * frames have 8 extra octets at the end, while 802.3 frames + * have only 4. We need to correctly account for this. */ + if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */ + nb -= 4; + else /* Ethernet header; mace includes FCS */ + nb -= 8; + skb_put(skb, nb); + skb->protocol = eth_type_trans(skb, dev); + dev->stats.rx_bytes += skb->len; + netif_rx(skb); + mp->rx_bufs[i] = NULL; + ++dev->stats.rx_packets; + } + } else { + ++dev->stats.rx_errors; + ++dev->stats.rx_length_errors; + } + + /* advance to next */ + if (++i >= N_RX_RING) + i = 0; + } + mp->rx_empty = i; + + i = mp->rx_fill; + for (;;) { + next = i + 1; + if (next >= N_RX_RING) + next = 0; + if (next == mp->rx_empty) + break; + cp = mp->rx_cmds + i; + skb = mp->rx_bufs[i]; + if (!skb) { + skb = dev_alloc_skb(RX_BUFLEN + 2); + if (skb) { + skb_reserve(skb, 2); + mp->rx_bufs[i] = skb; + } + } + st_le16(&cp->req_count, RX_BUFLEN); + data = skb? skb->data: dummy_buf; + st_le32(&cp->phy_addr, virt_to_bus(data)); + out_le16(&cp->xfer_status, 0); + out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); +#if 0 + if ((ld_le32(&rd->status) & ACTIVE) != 0) { + out_le32(&rd->control, (PAUSE << 16) | PAUSE); + while ((in_le32(&rd->status) & ACTIVE) != 0) + ; + } +#endif + i = next; + } + if (i != mp->rx_fill) { + out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE)); + mp->rx_fill = i; + } + spin_unlock_irqrestore(&mp->lock, flags); + return IRQ_HANDLED; +} + +static struct of_device_id mace_match[] = +{ + { + .name = "mace", + }, + {}, +}; +MODULE_DEVICE_TABLE (of, mace_match); + +static struct macio_driver mace_driver = +{ + .driver = { + .name = "mace", + .owner = THIS_MODULE, + .of_match_table = mace_match, + }, + .probe = mace_probe, + .remove = mace_remove, +}; + + +static int __init mace_init(void) +{ + return macio_register_driver(&mace_driver); +} + +static void __exit mace_cleanup(void) +{ + macio_unregister_driver(&mace_driver); + + kfree(dummy_buf); + dummy_buf = NULL; +} + +MODULE_AUTHOR("Paul Mackerras"); +MODULE_DESCRIPTION("PowerMac MACE driver."); +module_param(port_aaui, int, 0); +MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)"); +MODULE_LICENSE("GPL"); + +module_init(mace_init); +module_exit(mace_cleanup); diff --git a/drivers/net/ethernet/apple/mace.h b/drivers/net/ethernet/apple/mace.h new file mode 100644 index 00000000000..30b7ec0cedb --- /dev/null +++ b/drivers/net/ethernet/apple/mace.h @@ -0,0 +1,173 @@ +/* + * mace.h - definitions for the registers in the Am79C940 MACE + * (Medium Access Control for Ethernet) controller. + * + * Copyright (C) 1996 Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#define REG(x) volatile unsigned char x; char x ## _pad[15] + +struct mace { + REG(rcvfifo); /* receive FIFO */ + REG(xmtfifo); /* transmit FIFO */ + REG(xmtfc); /* transmit frame control */ + REG(xmtfs); /* transmit frame status */ + REG(xmtrc); /* transmit retry count */ + REG(rcvfc); /* receive frame control */ + REG(rcvfs); /* receive frame status (4 bytes) */ + REG(fifofc); /* FIFO frame count */ + REG(ir); /* interrupt register */ + REG(imr); /* interrupt mask register */ + REG(pr); /* poll register */ + REG(biucc); /* bus interface unit config control */ + REG(fifocc); /* FIFO configuration control */ + REG(maccc); /* medium access control config control */ + REG(plscc); /* phys layer signalling config control */ + REG(phycc); /* physical configuration control */ + REG(chipid_lo); /* chip ID, lsb */ + REG(chipid_hi); /* chip ID, msb */ + REG(iac); /* internal address config */ + REG(reg19); + REG(ladrf); /* logical address filter (8 bytes) */ + REG(padr); /* physical address (6 bytes) */ + REG(reg22); + REG(reg23); + REG(mpc); /* missed packet count (clears when read) */ + REG(reg25); + REG(rntpc); /* runt packet count (clears when read) */ + REG(rcvcc); /* recv collision count (clears when read) */ + REG(reg28); + REG(utr); /* user test reg */ + REG(reg30); + REG(reg31); +}; + +/* Bits in XMTFC */ +#define DRTRY 0x80 /* don't retry transmission after collision */ +#define DXMTFCS 0x08 /* don't append FCS to transmitted frame */ +#define AUTO_PAD_XMIT 0x01 /* auto-pad short packets on transmission */ + +/* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */ +#define XMTSV 0x80 /* transmit status (i.e. XMTFS) valid */ +#define UFLO 0x40 /* underflow - xmit fifo ran dry */ +#define LCOL 0x20 /* late collision (transmission aborted) */ +#define MORE 0x10 /* 2 or more retries needed to xmit frame */ +#define ONE 0x08 /* 1 retry needed to xmit frame */ +#define DEFER 0x04 /* MACE had to defer xmission (enet busy) */ +#define LCAR 0x02 /* loss of carrier (transmission aborted) */ +#define RTRY 0x01 /* too many retries (transmission aborted) */ + +/* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */ +#define EXDEF 0x80 /* had to defer for excessive time */ +#define RETRY_MASK 0x0f /* number of retries (0 - 15) */ + +/* Bits in RCVFC */ +#define LLRCV 0x08 /* low latency receive: early DMA request */ +#define M_RBAR 0x04 /* sets function of EAM/R pin */ +#define AUTO_STRIP_RCV 0x01 /* auto-strip short LLC frames on recv */ + +/* + * Bits in RCVFS. After a frame is received, four bytes of status + * are automatically read from this register and appended to the frame + * data in memory. These are: + * Byte 0 and 1: message byte count and frame status + * Byte 2: runt packet count + * Byte 3: receive collision count + */ +#define RS_OFLO 0x8000 /* receive FIFO overflowed */ +#define RS_CLSN 0x4000 /* received frame suffered (late) collision */ +#define RS_FRAMERR 0x2000 /* framing error flag */ +#define RS_FCSERR 0x1000 /* frame had FCS error */ +#define RS_COUNT 0x0fff /* mask for byte count field */ + +/* Bits (fields) in FIFOFC */ +#define RCVFC_SH 4 /* receive frame count in FIFO */ +#define RCVFC_MASK 0x0f +#define XMTFC_SH 0 /* transmit frame count in FIFO */ +#define XMTFC_MASK 0x0f + +/* + * Bits in IR and IMR. The IR clears itself when read. + * Setting a bit in the IMR will disable the corresponding interrupt. + */ +#define JABBER 0x80 /* jabber error - 10baseT xmission too long */ +#define BABBLE 0x40 /* babble - xmitter xmitting for too long */ +#define CERR 0x20 /* collision err - no SQE test (heartbeat) */ +#define RCVCCO 0x10 /* RCVCC overflow */ +#define RNTPCO 0x08 /* RNTPC overflow */ +#define MPCO 0x04 /* MPC overflow */ +#define RCVINT 0x02 /* receive interrupt */ +#define XMTINT 0x01 /* transmitter interrupt */ + +/* Bits in PR */ +#define XMTSV 0x80 /* XMTFS valid (same as in XMTFS) */ +#define TDTREQ 0x40 /* set when xmit fifo is requesting data */ +#define RDTREQ 0x20 /* set when recv fifo requests data xfer */ + +/* Bits in BIUCC */ +#define BSWP 0x40 /* byte swap, i.e. big-endian bus */ +#define XMTSP_4 0x00 /* start xmitting when 4 bytes in FIFO */ +#define XMTSP_16 0x10 /* start xmitting when 16 bytes in FIFO */ +#define XMTSP_64 0x20 /* start xmitting when 64 bytes in FIFO */ +#define XMTSP_112 0x30 /* start xmitting when 112 bytes in FIFO */ +#define SWRST 0x01 /* software reset */ + +/* Bits in FIFOCC */ +#define XMTFW_8 0x00 /* xmit fifo watermark = 8 words free */ +#define XMTFW_16 0x40 /* 16 words free */ +#define XMTFW_32 0x80 /* 32 words free */ +#define RCVFW_16 0x00 /* recv fifo watermark = 16 bytes avail */ +#define RCVFW_32 0x10 /* 32 bytes avail */ +#define RCVFW_64 0x20 /* 64 bytes avail */ +#define XMTFWU 0x08 /* xmit fifo watermark update enable */ +#define RCVFWU 0x04 /* recv fifo watermark update enable */ +#define XMTBRST 0x02 /* enable transmit burst mode */ +#define RCVBRST 0x01 /* enable receive burst mode */ + +/* Bits in MACCC */ +#define PROM 0x80 /* promiscuous mode */ +#define DXMT2PD 0x40 /* disable xmit two-part deferral algorithm */ +#define EMBA 0x20 /* enable modified backoff algorithm */ +#define DRCVPA 0x08 /* disable receiving physical address */ +#define DRCVBC 0x04 /* disable receiving broadcasts */ +#define ENXMT 0x02 /* enable transmitter */ +#define ENRCV 0x01 /* enable receiver */ + +/* Bits in PLSCC */ +#define XMTSEL 0x08 /* select DO+/DO- state when idle */ +#define PORTSEL_AUI 0x00 /* select AUI port */ +#define PORTSEL_10T 0x02 /* select 10Base-T port */ +#define PORTSEL_DAI 0x04 /* select DAI port */ +#define PORTSEL_GPSI 0x06 /* select GPSI port */ +#define ENPLSIO 0x01 /* enable optional PLS I/O pins */ + +/* Bits in PHYCC */ +#define LNKFL 0x80 /* reports 10Base-T link failure */ +#define DLNKTST 0x40 /* disable 10Base-T link test */ +#define REVPOL 0x20 /* 10Base-T receiver polarity reversed */ +#define DAPC 0x10 /* disable auto receiver polarity correction */ +#define LRT 0x08 /* low receive threshold for long links */ +#define ASEL 0x04 /* auto-select AUI or 10Base-T port */ +#define RWAKE 0x02 /* remote wake function */ +#define AWAKE 0x01 /* auto wake function */ + +/* Bits in IAC */ +#define ADDRCHG 0x80 /* request address change */ +#define PHYADDR 0x04 /* access physical address */ +#define LOGADDR 0x02 /* access multicast filter */ + +/* Bits in UTR */ +#define RTRE 0x80 /* reserved test register enable. DON'T SET. */ +#define RTRD 0x40 /* reserved test register disable. Sticky */ +#define RPAC 0x20 /* accept runt packets */ +#define FCOLL 0x10 /* force collision */ +#define RCVFCSE 0x08 /* receive FCS enable */ +#define LOOP_NONE 0x00 /* no loopback */ +#define LOOP_EXT 0x02 /* external loopback */ +#define LOOP_INT 0x04 /* internal loopback, excludes MENDEC */ +#define LOOP_MENDEC 0x06 /* internal loopback, includes MENDEC */ diff --git a/drivers/net/ethernet/apple/macmace.c b/drivers/net/ethernet/apple/macmace.c new file mode 100644 index 00000000000..4286e67f963 --- /dev/null +++ b/drivers/net/ethernet/apple/macmace.c @@ -0,0 +1,799 @@ +/* + * Driver for the Macintosh 68K onboard MACE controller with PSC + * driven DMA. The MACE driver code is derived from mace.c. The + * Mac68k theory of operation is courtesy of the MacBSD wizards. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Copyright (C) 1996 Paul Mackerras. + * Copyright (C) 1998 Alan Cox + * + * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver + * + * Copyright (C) 2007 Finn Thain + * + * Converted to DMA API, converted to unified driver model, + * sync'd some routines with mace.c and fixed various bugs. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mace.h" + +static char mac_mace_string[] = "macmace"; + +#define N_TX_BUFF_ORDER 0 +#define N_TX_RING (1 << N_TX_BUFF_ORDER) +#define N_RX_BUFF_ORDER 3 +#define N_RX_RING (1 << N_RX_BUFF_ORDER) + +#define TX_TIMEOUT HZ + +#define MACE_BUFF_SIZE 0x800 + +/* Chip rev needs workaround on HW & multicast addr change */ +#define BROKEN_ADDRCHG_REV 0x0941 + +/* The MACE is simply wired down on a Mac68K box */ + +#define MACE_BASE (void *)(0x50F1C000) +#define MACE_PROM (void *)(0x50F08001) + +struct mace_data { + volatile struct mace *mace; + unsigned char *tx_ring; + dma_addr_t tx_ring_phys; + unsigned char *rx_ring; + dma_addr_t rx_ring_phys; + int dma_intr; + int rx_slot, rx_tail; + int tx_slot, tx_sloti, tx_count; + int chipid; + struct device *device; +}; + +struct mace_frame { + u8 rcvcnt; + u8 pad1; + u8 rcvsts; + u8 pad2; + u8 rntpc; + u8 pad3; + u8 rcvcc; + u8 pad4; + u32 pad5; + u32 pad6; + u8 data[1]; + /* And frame continues.. */ +}; + +#define PRIV_BYTES sizeof(struct mace_data) + +static int mace_open(struct net_device *dev); +static int mace_close(struct net_device *dev); +static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); +static void mace_set_multicast(struct net_device *dev); +static int mace_set_address(struct net_device *dev, void *addr); +static void mace_reset(struct net_device *dev); +static irqreturn_t mace_interrupt(int irq, void *dev_id); +static irqreturn_t mace_dma_intr(int irq, void *dev_id); +static void mace_tx_timeout(struct net_device *dev); +static void __mace_set_address(struct net_device *dev, void *addr); + +/* + * Load a receive DMA channel with a base address and ring length + */ + +static void mace_load_rxdma_base(struct net_device *dev, int set) +{ + struct mace_data *mp = netdev_priv(dev); + + psc_write_word(PSC_ENETRD_CMD + set, 0x0100); + psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); + psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); + psc_write_word(PSC_ENETRD_CMD + set, 0x9800); + mp->rx_tail = 0; +} + +/* + * Reset the receive DMA subsystem + */ + +static void mace_rxdma_reset(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mace = mp->mace; + u8 maccc = mace->maccc; + + mace->maccc = maccc & ~ENRCV; + + psc_write_word(PSC_ENETRD_CTL, 0x8800); + mace_load_rxdma_base(dev, 0x00); + psc_write_word(PSC_ENETRD_CTL, 0x0400); + + psc_write_word(PSC_ENETRD_CTL, 0x8800); + mace_load_rxdma_base(dev, 0x10); + psc_write_word(PSC_ENETRD_CTL, 0x0400); + + mace->maccc = maccc; + mp->rx_slot = 0; + + psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); + psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); +} + +/* + * Reset the transmit DMA subsystem + */ + +static void mace_txdma_reset(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mace = mp->mace; + u8 maccc; + + psc_write_word(PSC_ENETWR_CTL, 0x8800); + + maccc = mace->maccc; + mace->maccc = maccc & ~ENXMT; + + mp->tx_slot = mp->tx_sloti = 0; + mp->tx_count = N_TX_RING; + + psc_write_word(PSC_ENETWR_CTL, 0x0400); + mace->maccc = maccc; +} + +/* + * Disable DMA + */ + +static void mace_dma_off(struct net_device *dev) +{ + psc_write_word(PSC_ENETRD_CTL, 0x8800); + psc_write_word(PSC_ENETRD_CTL, 0x1000); + psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); + psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); + + psc_write_word(PSC_ENETWR_CTL, 0x8800); + psc_write_word(PSC_ENETWR_CTL, 0x1000); + psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); + psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); +} + +static const struct net_device_ops mace_netdev_ops = { + .ndo_open = mace_open, + .ndo_stop = mace_close, + .ndo_start_xmit = mace_xmit_start, + .ndo_tx_timeout = mace_tx_timeout, + .ndo_set_multicast_list = mace_set_multicast, + .ndo_set_mac_address = mace_set_address, + .ndo_change_mtu = eth_change_mtu, + .ndo_validate_addr = eth_validate_addr, +}; + +/* + * Not really much of a probe. The hardware table tells us if this + * model of Macintrash has a MACE (AV macintoshes) + */ + +static int __devinit mace_probe(struct platform_device *pdev) +{ + int j; + struct mace_data *mp; + unsigned char *addr; + struct net_device *dev; + unsigned char checksum = 0; + static int found = 0; + int err; + + if (found || macintosh_config->ether_type != MAC_ETHER_MACE) + return -ENODEV; + + found = 1; /* prevent 'finding' one on every device probe */ + + dev = alloc_etherdev(PRIV_BYTES); + if (!dev) + return -ENOMEM; + + mp = netdev_priv(dev); + + mp->device = &pdev->dev; + SET_NETDEV_DEV(dev, &pdev->dev); + + dev->base_addr = (u32)MACE_BASE; + mp->mace = MACE_BASE; + + dev->irq = IRQ_MAC_MACE; + mp->dma_intr = IRQ_MAC_MACE_DMA; + + mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; + + /* + * The PROM contains 8 bytes which total 0xFF when XOR'd + * together. Due to the usual peculiar apple brain damage + * the bytes are spaced out in a strange boundary and the + * bits are reversed. + */ + + addr = (void *)MACE_PROM; + + for (j = 0; j < 6; ++j) { + u8 v = bitrev8(addr[j<<4]); + checksum ^= v; + dev->dev_addr[j] = v; + } + for (; j < 8; ++j) { + checksum ^= bitrev8(addr[j<<4]); + } + + if (checksum != 0xFF) { + free_netdev(dev); + return -ENODEV; + } + + dev->netdev_ops = &mace_netdev_ops; + dev->watchdog_timeo = TX_TIMEOUT; + + printk(KERN_INFO "%s: 68K MACE, hardware address %pM\n", + dev->name, dev->dev_addr); + + err = register_netdev(dev); + if (!err) + return 0; + + free_netdev(dev); + return err; +} + +/* + * Reset the chip. + */ + +static void mace_reset(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + int i; + + /* soft-reset the chip */ + i = 200; + while (--i) { + mb->biucc = SWRST; + if (mb->biucc & SWRST) { + udelay(10); + continue; + } + break; + } + if (!i) { + printk(KERN_ERR "macmace: cannot reset chip!\n"); + return; + } + + mb->maccc = 0; /* turn off tx, rx */ + mb->imr = 0xFF; /* disable all intrs for now */ + i = mb->ir; + + mb->biucc = XMTSP_64; + mb->utr = RTRD; + mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; + + mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ + mb->rcvfc = 0; + + /* load up the hardware address */ + __mace_set_address(dev, dev->dev_addr); + + /* clear the multicast filter */ + if (mp->chipid == BROKEN_ADDRCHG_REV) + mb->iac = LOGADDR; + else { + mb->iac = ADDRCHG | LOGADDR; + while ((mb->iac & ADDRCHG) != 0) + ; + } + for (i = 0; i < 8; ++i) + mb->ladrf = 0; + + /* done changing address */ + if (mp->chipid != BROKEN_ADDRCHG_REV) + mb->iac = 0; + + mb->plscc = PORTSEL_AUI; +} + +/* + * Load the address on a mace controller. + */ + +static void __mace_set_address(struct net_device *dev, void *addr) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + unsigned char *p = addr; + int i; + + /* load up the hardware address */ + if (mp->chipid == BROKEN_ADDRCHG_REV) + mb->iac = PHYADDR; + else { + mb->iac = ADDRCHG | PHYADDR; + while ((mb->iac & ADDRCHG) != 0) + ; + } + for (i = 0; i < 6; ++i) + mb->padr = dev->dev_addr[i] = p[i]; + if (mp->chipid != BROKEN_ADDRCHG_REV) + mb->iac = 0; +} + +static int mace_set_address(struct net_device *dev, void *addr) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + unsigned long flags; + u8 maccc; + + local_irq_save(flags); + + maccc = mb->maccc; + + __mace_set_address(dev, addr); + + mb->maccc = maccc; + + local_irq_restore(flags); + + return 0; +} + +/* + * Open the Macintosh MACE. Most of this is playing with the DMA + * engine. The ethernet chip is quite friendly. + */ + +static int mace_open(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + + /* reset the chip */ + mace_reset(dev); + + if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { + printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); + return -EAGAIN; + } + if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { + printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); + free_irq(dev->irq, dev); + return -EAGAIN; + } + + /* Allocate the DMA ring buffers */ + + mp->tx_ring = dma_alloc_coherent(mp->device, + N_TX_RING * MACE_BUFF_SIZE, + &mp->tx_ring_phys, GFP_KERNEL); + if (mp->tx_ring == NULL) { + printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); + goto out1; + } + + mp->rx_ring = dma_alloc_coherent(mp->device, + N_RX_RING * MACE_BUFF_SIZE, + &mp->rx_ring_phys, GFP_KERNEL); + if (mp->rx_ring == NULL) { + printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); + goto out2; + } + + mace_dma_off(dev); + + /* Not sure what these do */ + + psc_write_word(PSC_ENETWR_CTL, 0x9000); + psc_write_word(PSC_ENETRD_CTL, 0x9000); + psc_write_word(PSC_ENETWR_CTL, 0x0400); + psc_write_word(PSC_ENETRD_CTL, 0x0400); + + mace_rxdma_reset(dev); + mace_txdma_reset(dev); + + /* turn it on! */ + mb->maccc = ENXMT | ENRCV; + /* enable all interrupts except receive interrupts */ + mb->imr = RCVINT; + return 0; + +out2: + dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, + mp->tx_ring, mp->tx_ring_phys); +out1: + free_irq(dev->irq, dev); + free_irq(mp->dma_intr, dev); + return -ENOMEM; +} + +/* + * Shut down the mace and its interrupt channel + */ + +static int mace_close(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + + mb->maccc = 0; /* disable rx and tx */ + mb->imr = 0xFF; /* disable all irqs */ + mace_dma_off(dev); /* disable rx and tx dma */ + + return 0; +} + +/* + * Transmit a frame + */ + +static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + unsigned long flags; + + /* Stop the queue since there's only the one buffer */ + + local_irq_save(flags); + netif_stop_queue(dev); + if (!mp->tx_count) { + printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); + local_irq_restore(flags); + return NETDEV_TX_BUSY; + } + mp->tx_count--; + local_irq_restore(flags); + + dev->stats.tx_packets++; + dev->stats.tx_bytes += skb->len; + + /* We need to copy into our xmit buffer to take care of alignment and caching issues */ + skb_copy_from_linear_data(skb, mp->tx_ring, skb->len); + + /* load the Tx DMA and fire it off */ + + psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); + psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); + psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); + + mp->tx_slot ^= 0x10; + + dev_kfree_skb(skb); + + return NETDEV_TX_OK; +} + +static void mace_set_multicast(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + int i; + u32 crc; + u8 maccc; + unsigned long flags; + + local_irq_save(flags); + maccc = mb->maccc; + mb->maccc &= ~PROM; + + if (dev->flags & IFF_PROMISC) { + mb->maccc |= PROM; + } else { + unsigned char multicast_filter[8]; + struct netdev_hw_addr *ha; + + if (dev->flags & IFF_ALLMULTI) { + for (i = 0; i < 8; i++) { + multicast_filter[i] = 0xFF; + } + } else { + for (i = 0; i < 8; i++) + multicast_filter[i] = 0; + netdev_for_each_mc_addr(ha, dev) { + crc = ether_crc_le(6, ha->addr); + /* bit number in multicast_filter */ + i = crc >> 26; + multicast_filter[i >> 3] |= 1 << (i & 7); + } + } + + if (mp->chipid == BROKEN_ADDRCHG_REV) + mb->iac = LOGADDR; + else { + mb->iac = ADDRCHG | LOGADDR; + while ((mb->iac & ADDRCHG) != 0) + ; + } + for (i = 0; i < 8; ++i) + mb->ladrf = multicast_filter[i]; + if (mp->chipid != BROKEN_ADDRCHG_REV) + mb->iac = 0; + } + + mb->maccc = maccc; + local_irq_restore(flags); +} + +static void mace_handle_misc_intrs(struct net_device *dev, int intr) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + static int mace_babbles, mace_jabbers; + + if (intr & MPCO) + dev->stats.rx_missed_errors += 256; + dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */ + if (intr & RNTPCO) + dev->stats.rx_length_errors += 256; + dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */ + if (intr & CERR) + ++dev->stats.tx_heartbeat_errors; + if (intr & BABBLE) + if (mace_babbles++ < 4) + printk(KERN_DEBUG "macmace: babbling transmitter\n"); + if (intr & JABBER) + if (mace_jabbers++ < 4) + printk(KERN_DEBUG "macmace: jabbering transceiver\n"); +} + +static irqreturn_t mace_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + int intr, fs; + unsigned long flags; + + /* don't want the dma interrupt handler to fire */ + local_irq_save(flags); + + intr = mb->ir; /* read interrupt register */ + mace_handle_misc_intrs(dev, intr); + + if (intr & XMTINT) { + fs = mb->xmtfs; + if ((fs & XMTSV) == 0) { + printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); + mace_reset(dev); + /* + * XXX mace likes to hang the machine after a xmtfs error. + * This is hard to reproduce, reseting *may* help + */ + } + /* dma should have finished */ + if (!mp->tx_count) { + printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); + } + /* Update stats */ + if (fs & (UFLO|LCOL|LCAR|RTRY)) { + ++dev->stats.tx_errors; + if (fs & LCAR) + ++dev->stats.tx_carrier_errors; + else if (fs & (UFLO|LCOL|RTRY)) { + ++dev->stats.tx_aborted_errors; + if (mb->xmtfs & UFLO) { + printk(KERN_ERR "%s: DMA underrun.\n", dev->name); + dev->stats.tx_fifo_errors++; + mace_txdma_reset(dev); + } + } + } + } + + if (mp->tx_count) + netif_wake_queue(dev); + + local_irq_restore(flags); + + return IRQ_HANDLED; +} + +static void mace_tx_timeout(struct net_device *dev) +{ + struct mace_data *mp = netdev_priv(dev); + volatile struct mace *mb = mp->mace; + unsigned long flags; + + local_irq_save(flags); + + /* turn off both tx and rx and reset the chip */ + mb->maccc = 0; + printk(KERN_ERR "macmace: transmit timeout - resetting\n"); + mace_txdma_reset(dev); + mace_reset(dev); + + /* restart rx dma */ + mace_rxdma_reset(dev); + + mp->tx_count = N_TX_RING; + netif_wake_queue(dev); + + /* turn it on! */ + mb->maccc = ENXMT | ENRCV; + /* enable all interrupts except receive interrupts */ + mb->imr = RCVINT; + + local_irq_restore(flags); +} + +/* + * Handle a newly arrived frame + */ + +static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) +{ + struct sk_buff *skb; + unsigned int frame_status = mf->rcvsts; + + if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { + dev->stats.rx_errors++; + if (frame_status & RS_OFLO) { + printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name); + dev->stats.rx_fifo_errors++; + } + if (frame_status & RS_CLSN) + dev->stats.collisions++; + if (frame_status & RS_FRAMERR) + dev->stats.rx_frame_errors++; + if (frame_status & RS_FCSERR) + dev->stats.rx_crc_errors++; + } else { + unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); + + skb = dev_alloc_skb(frame_length + 2); + if (!skb) { + dev->stats.rx_dropped++; + return; + } + skb_reserve(skb, 2); + memcpy(skb_put(skb, frame_length), mf->data, frame_length); + + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + dev->stats.rx_packets++; + dev->stats.rx_bytes += frame_length; + } +} + +/* + * The PSC has passed us a DMA interrupt event. + */ + +static irqreturn_t mace_dma_intr(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *) dev_id; + struct mace_data *mp = netdev_priv(dev); + int left, head; + u16 status; + u32 baka; + + /* Not sure what this does */ + + while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); + if (!(baka & 0x60000000)) return IRQ_NONE; + + /* + * Process the read queue + */ + + status = psc_read_word(PSC_ENETRD_CTL); + + if (status & 0x2000) { + mace_rxdma_reset(dev); + } else if (status & 0x0100) { + psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); + + left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); + head = N_RX_RING - left; + + /* Loop through the ring buffer and process new packages */ + + while (mp->rx_tail < head) { + mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring + + (mp->rx_tail * MACE_BUFF_SIZE))); + mp->rx_tail++; + } + + /* If we're out of buffers in this ring then switch to */ + /* the other set, otherwise just reactivate this one. */ + + if (!left) { + mace_load_rxdma_base(dev, mp->rx_slot); + mp->rx_slot ^= 0x10; + } else { + psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); + } + } + + /* + * Process the write queue + */ + + status = psc_read_word(PSC_ENETWR_CTL); + + if (status & 0x2000) { + mace_txdma_reset(dev); + } else if (status & 0x0100) { + psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); + mp->tx_sloti ^= 0x10; + mp->tx_count++; + } + return IRQ_HANDLED; +} + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); +MODULE_ALIAS("platform:macmace"); + +static int __devexit mac_mace_device_remove (struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct mace_data *mp = netdev_priv(dev); + + unregister_netdev(dev); + + free_irq(dev->irq, dev); + free_irq(IRQ_MAC_MACE_DMA, dev); + + dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, + mp->rx_ring, mp->rx_ring_phys); + dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, + mp->tx_ring, mp->tx_ring_phys); + + free_netdev(dev); + + return 0; +} + +static struct platform_driver mac_mace_driver = { + .probe = mace_probe, + .remove = __devexit_p(mac_mace_device_remove), + .driver = { + .name = mac_mace_string, + .owner = THIS_MODULE, + }, +}; + +static int __init mac_mace_init_module(void) +{ + if (!MACH_IS_MAC) + return -ENODEV; + + return platform_driver_register(&mac_mace_driver); +} + +static void __exit mac_mace_cleanup_module(void) +{ + platform_driver_unregister(&mac_mace_driver); +} + +module_init(mac_mace_init_module); +module_exit(mac_mace_cleanup_module); diff --git a/drivers/net/mac89x0.c b/drivers/net/mac89x0.c deleted file mode 100644 index 669b317974a..00000000000 --- a/drivers/net/mac89x0.c +++ /dev/null @@ -1,634 +0,0 @@ -/* mac89x0.c: A Crystal Semiconductor CS89[02]0 driver for linux. */ -/* - Written 1996 by Russell Nelson, with reference to skeleton.c - written 1993-1994 by Donald Becker. - - This software may be used and distributed according to the terms - of the GNU General Public License, incorporated herein by reference. - - The author may be reached at nelson@crynwr.com, Crynwr - Software, 11 Grant St., Potsdam, NY 13676 - - Changelog: - - Mike Cruse : mcruse@cti-ltd.com - : Changes for Linux 2.0 compatibility. - : Added dev_id parameter in net_interrupt(), - : request_irq() and free_irq(). Just NULL for now. - - Mike Cruse : Added MOD_INC_USE_COUNT and MOD_DEC_USE_COUNT macros - : in net_open() and net_close() so kerneld would know - : that the module is in use and wouldn't eject the - : driver prematurely. - - Mike Cruse : Rewrote init_module() and cleanup_module using 8390.c - : as an example. Disabled autoprobing in init_module(), - : not a good thing to do to other devices while Linux - : is running from all accounts. - - Alan Cox : Removed 1.2 support, added 2.1 extra counters. - - David Huggins-Daines - - Split this off into mac89x0.c, and gutted it of all parts which are - not relevant to the existing CS8900 cards on the Macintosh - (i.e. basically the Daynaport CS and LC cards). To be precise: - - * Removed all the media-detection stuff, because these cards are - TP-only. - - * Lobotomized the ISA interrupt bogosity, because these cards use - a hardwired NuBus interrupt and a magic ISAIRQ value in the card. - - * Basically eliminated everything not relevant to getting the - cards minimally functioning on the Macintosh. - - I might add that these cards are badly designed even from the Mac - standpoint, in that Dayna, in their infinite wisdom, used NuBus slot - I/O space and NuBus interrupts for these cards, but neglected to - provide anything even remotely resembling a NuBus ROM. Therefore we - have to probe for them in a brain-damaged ISA-like fashion. - - Arnaldo Carvalho de Melo - 11/01/2001 - check kmalloc and release the allocated memory on failure in - mac89x0_probe and in init_module - use local_irq_{save,restore}(flags) in net_get_stat, not just - local_irq_{dis,en}able() -*/ - -static char *version = -"cs89x0.c:v1.02 11/26/96 Russell Nelson \n"; - -/* ======================= configure the driver here ======================= */ - -/* use 0 for production, 1 for verification, >2 for debug */ -#ifndef NET_DEBUG -#define NET_DEBUG 0 -#endif - -/* ======================= end of configuration ======================= */ - - -/* Always include 'config.h' first in case the user wants to turn on - or override something. */ -#include - -/* - Sources: - - Crynwr packet driver epktisa. - - Crystal Semiconductor data sheets. - -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "cs89x0.h" - -static unsigned int net_debug = NET_DEBUG; - -/* Information that need to be kept for each board. */ -struct net_local { - int chip_type; /* one of: CS8900, CS8920, CS8920M */ - char chip_revision; /* revision letter of the chip ('A'...) */ - int send_cmd; /* the propercommand used to send a packet. */ - int rx_mode; - int curr_rx_cfg; - int send_underrun; /* keep track of how many underruns in a row we get */ - struct sk_buff *skb; -}; - -/* Index to functions, as function prototypes. */ - -#if 0 -extern void reset_chip(struct net_device *dev); -#endif -static int net_open(struct net_device *dev); -static int net_send_packet(struct sk_buff *skb, struct net_device *dev); -static irqreturn_t net_interrupt(int irq, void *dev_id); -static void set_multicast_list(struct net_device *dev); -static void net_rx(struct net_device *dev); -static int net_close(struct net_device *dev); -static struct net_device_stats *net_get_stats(struct net_device *dev); -static int set_mac_address(struct net_device *dev, void *addr); - - -/* Example routines you must write ;->. */ -#define tx_done(dev) 1 - -/* For reading/writing registers ISA-style */ -static inline int -readreg_io(struct net_device *dev, int portno) -{ - nubus_writew(swab16(portno), dev->base_addr + ADD_PORT); - return swab16(nubus_readw(dev->base_addr + DATA_PORT)); -} - -static inline void -writereg_io(struct net_device *dev, int portno, int value) -{ - nubus_writew(swab16(portno), dev->base_addr + ADD_PORT); - nubus_writew(swab16(value), dev->base_addr + DATA_PORT); -} - -/* These are for reading/writing registers in shared memory */ -static inline int -readreg(struct net_device *dev, int portno) -{ - return swab16(nubus_readw(dev->mem_start + portno)); -} - -static inline void -writereg(struct net_device *dev, int portno, int value) -{ - nubus_writew(swab16(value), dev->mem_start + portno); -} - -static const struct net_device_ops mac89x0_netdev_ops = { - .ndo_open = net_open, - .ndo_stop = net_close, - .ndo_start_xmit = net_send_packet, - .ndo_get_stats = net_get_stats, - .ndo_set_multicast_list = set_multicast_list, - .ndo_set_mac_address = set_mac_address, - .ndo_validate_addr = eth_validate_addr, - .ndo_change_mtu = eth_change_mtu, -}; - -/* Probe for the CS8900 card in slot E. We won't bother looking - anywhere else until we have a really good reason to do so. */ -struct net_device * __init mac89x0_probe(int unit) -{ - struct net_device *dev; - static int once_is_enough; - struct net_local *lp; - static unsigned version_printed; - int i, slot; - unsigned rev_type = 0; - unsigned long ioaddr; - unsigned short sig; - int err = -ENODEV; - - if (!MACH_IS_MAC) - return ERR_PTR(-ENODEV); - - dev = alloc_etherdev(sizeof(struct net_local)); - if (!dev) - return ERR_PTR(-ENOMEM); - - if (unit >= 0) { - sprintf(dev->name, "eth%d", unit); - netdev_boot_setup_check(dev); - } - - if (once_is_enough) - goto out; - once_is_enough = 1; - - /* We might have to parameterize this later */ - slot = 0xE; - /* Get out now if there's a real NuBus card in slot E */ - if (nubus_find_slot(slot, NULL) != NULL) - goto out; - - /* The pseudo-ISA bits always live at offset 0x300 (gee, - wonder why...) */ - ioaddr = (unsigned long) - nubus_slot_addr(slot) | (((slot&0xf) << 20) + DEFAULTIOBASE); - { - unsigned long flags; - int card_present; - - local_irq_save(flags); - card_present = (hwreg_present((void*) ioaddr+4) && - hwreg_present((void*) ioaddr + DATA_PORT)); - local_irq_restore(flags); - - if (!card_present) - goto out; - } - - nubus_writew(0, ioaddr + ADD_PORT); - sig = nubus_readw(ioaddr + DATA_PORT); - if (sig != swab16(CHIP_EISA_ID_SIG)) - goto out; - - /* Initialize the net_device structure. */ - lp = netdev_priv(dev); - - /* Fill in the 'dev' fields. */ - dev->base_addr = ioaddr; - dev->mem_start = (unsigned long) - nubus_slot_addr(slot) | (((slot&0xf) << 20) + MMIOBASE); - dev->mem_end = dev->mem_start + 0x1000; - - /* Turn on shared memory */ - writereg_io(dev, PP_BusCTL, MEMORY_ON); - - /* get the chip type */ - rev_type = readreg(dev, PRODUCT_ID_ADD); - lp->chip_type = rev_type &~ REVISON_BITS; - lp->chip_revision = ((rev_type & REVISON_BITS) >> 8) + 'A'; - - /* Check the chip type and revision in order to set the correct send command - CS8920 revision C and CS8900 revision F can use the faster send. */ - lp->send_cmd = TX_AFTER_381; - if (lp->chip_type == CS8900 && lp->chip_revision >= 'F') - lp->send_cmd = TX_NOW; - if (lp->chip_type != CS8900 && lp->chip_revision >= 'C') - lp->send_cmd = TX_NOW; - - if (net_debug && version_printed++ == 0) - printk(version); - - printk(KERN_INFO "%s: cs89%c0%s rev %c found at %#8lx", - dev->name, - lp->chip_type==CS8900?'0':'2', - lp->chip_type==CS8920M?"M":"", - lp->chip_revision, - dev->base_addr); - - /* Try to read the MAC address */ - if ((readreg(dev, PP_SelfST) & (EEPROM_PRESENT | EEPROM_OK)) == 0) { - printk("\nmac89x0: No EEPROM, giving up now.\n"); - goto out1; - } else { - for (i = 0; i < ETH_ALEN; i += 2) { - /* Big-endian (why??!) */ - unsigned short s = readreg(dev, PP_IA + i); - dev->dev_addr[i] = s >> 8; - dev->dev_addr[i+1] = s & 0xff; - } - } - - dev->irq = SLOT2IRQ(slot); - - /* print the IRQ and ethernet address. */ - - printk(" IRQ %d ADDR %pM\n", dev->irq, dev->dev_addr); - - dev->netdev_ops = &mac89x0_netdev_ops; - - err = register_netdev(dev); - if (err) - goto out1; - return NULL; -out1: - nubus_writew(0, dev->base_addr + ADD_PORT); -out: - free_netdev(dev); - return ERR_PTR(err); -} - -#if 0 -/* This is useful for something, but I don't know what yet. */ -void __init reset_chip(struct net_device *dev) -{ - int reset_start_time; - - writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); - - /* wait 30 ms */ - msleep_interruptible(30); - - /* Wait until the chip is reset */ - reset_start_time = jiffies; - while( (readreg(dev, PP_SelfST) & INIT_DONE) == 0 && jiffies - reset_start_time < 2) - ; -} -#endif - -/* Open/initialize the board. This is called (in the current kernel) - sometime after booting when the 'ifconfig' program is run. - - This routine should set everything up anew at each open, even - registers that "should" only need to be set once at boot, so that - there is non-reboot way to recover if something goes wrong. - */ -static int -net_open(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - int i; - - /* Disable the interrupt for now */ - writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ); - - /* Grab the interrupt */ - if (request_irq(dev->irq, net_interrupt, 0, "cs89x0", dev)) - return -EAGAIN; - - /* Set up the IRQ - Apparently magic */ - if (lp->chip_type == CS8900) - writereg(dev, PP_CS8900_ISAINT, 0); - else - writereg(dev, PP_CS8920_ISAINT, 0); - - /* set the Ethernet address */ - for (i=0; i < ETH_ALEN/2; i++) - writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); - - /* Turn on both receive and transmit operations */ - writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); - - /* Receive only error free packets addressed to this card */ - lp->rx_mode = 0; - writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); - - lp->curr_rx_cfg = RX_OK_ENBL | RX_CRC_ERROR_ENBL; - - writereg(dev, PP_RxCFG, lp->curr_rx_cfg); - - writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | - TX_LATE_COL_ENBL | TX_JBR_ENBL | TX_ANY_COL_ENBL | TX_16_COL_ENBL); - - writereg(dev, PP_BufCFG, READY_FOR_TX_ENBL | RX_MISS_COUNT_OVRFLOW_ENBL | - TX_COL_COUNT_OVRFLOW_ENBL | TX_UNDERRUN_ENBL); - - /* now that we've got our act together, enable everything */ - writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) | ENABLE_IRQ); - netif_start_queue(dev); - return 0; -} - -static int -net_send_packet(struct sk_buff *skb, struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - unsigned long flags; - - if (net_debug > 3) - printk("%s: sent %d byte packet of type %x\n", - dev->name, skb->len, - (skb->data[ETH_ALEN+ETH_ALEN] << 8) - | skb->data[ETH_ALEN+ETH_ALEN+1]); - - /* keep the upload from being interrupted, since we - ask the chip to start transmitting before the - whole packet has been completely uploaded. */ - local_irq_save(flags); - netif_stop_queue(dev); - - /* initiate a transmit sequence */ - writereg(dev, PP_TxCMD, lp->send_cmd); - writereg(dev, PP_TxLength, skb->len); - - /* Test to see if the chip has allocated memory for the packet */ - if ((readreg(dev, PP_BusST) & READY_FOR_TX_NOW) == 0) { - /* Gasp! It hasn't. But that shouldn't happen since - we're waiting for TxOk, so return 1 and requeue this packet. */ - local_irq_restore(flags); - return NETDEV_TX_BUSY; - } - - /* Write the contents of the packet */ - skb_copy_from_linear_data(skb, (void *)(dev->mem_start + PP_TxFrame), - skb->len+1); - - local_irq_restore(flags); - dev_kfree_skb (skb); - - return NETDEV_TX_OK; -} - -/* The typical workload of the driver: - Handle the network interface interrupts. */ -static irqreturn_t net_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct net_local *lp; - int ioaddr, status; - - if (dev == NULL) { - printk ("net_interrupt(): irq %d for unknown device.\n", irq); - return IRQ_NONE; - } - - ioaddr = dev->base_addr; - lp = netdev_priv(dev); - - /* we MUST read all the events out of the ISQ, otherwise we'll never - get interrupted again. As a consequence, we can't have any limit - on the number of times we loop in the interrupt handler. The - hardware guarantees that eventually we'll run out of events. Of - course, if you're on a slow machine, and packets are arriving - faster than you can read them off, you're screwed. Hasta la - vista, baby! */ - while ((status = swab16(nubus_readw(dev->base_addr + ISQ_PORT)))) { - if (net_debug > 4)printk("%s: event=%04x\n", dev->name, status); - switch(status & ISQ_EVENT_MASK) { - case ISQ_RECEIVER_EVENT: - /* Got a packet(s). */ - net_rx(dev); - break; - case ISQ_TRANSMITTER_EVENT: - dev->stats.tx_packets++; - netif_wake_queue(dev); - if ((status & TX_OK) == 0) - dev->stats.tx_errors++; - if (status & TX_LOST_CRS) - dev->stats.tx_carrier_errors++; - if (status & TX_SQE_ERROR) - dev->stats.tx_heartbeat_errors++; - if (status & TX_LATE_COL) - dev->stats.tx_window_errors++; - if (status & TX_16_COL) - dev->stats.tx_aborted_errors++; - break; - case ISQ_BUFFER_EVENT: - if (status & READY_FOR_TX) { - /* we tried to transmit a packet earlier, - but inexplicably ran out of buffers. - That shouldn't happen since we only ever - load one packet. Shrug. Do the right - thing anyway. */ - netif_wake_queue(dev); - } - if (status & TX_UNDERRUN) { - if (net_debug > 0) printk("%s: transmit underrun\n", dev->name); - lp->send_underrun++; - if (lp->send_underrun == 3) lp->send_cmd = TX_AFTER_381; - else if (lp->send_underrun == 6) lp->send_cmd = TX_AFTER_ALL; - } - break; - case ISQ_RX_MISS_EVENT: - dev->stats.rx_missed_errors += (status >> 6); - break; - case ISQ_TX_COL_EVENT: - dev->stats.collisions += (status >> 6); - break; - } - } - return IRQ_HANDLED; -} - -/* We have a good packet(s), get it/them out of the buffers. */ -static void -net_rx(struct net_device *dev) -{ - struct sk_buff *skb; - int status, length; - - status = readreg(dev, PP_RxStatus); - if ((status & RX_OK) == 0) { - dev->stats.rx_errors++; - if (status & RX_RUNT) - dev->stats.rx_length_errors++; - if (status & RX_EXTRA_DATA) - dev->stats.rx_length_errors++; - if ((status & RX_CRC_ERROR) && - !(status & (RX_EXTRA_DATA|RX_RUNT))) - /* per str 172 */ - dev->stats.rx_crc_errors++; - if (status & RX_DRIBBLE) - dev->stats.rx_frame_errors++; - return; - } - - length = readreg(dev, PP_RxLength); - /* Malloc up new buffer. */ - skb = alloc_skb(length, GFP_ATOMIC); - if (skb == NULL) { - printk("%s: Memory squeeze, dropping packet.\n", dev->name); - dev->stats.rx_dropped++; - return; - } - skb_put(skb, length); - - skb_copy_to_linear_data(skb, (void *)(dev->mem_start + PP_RxFrame), - length); - - if (net_debug > 3)printk("%s: received %d byte packet of type %x\n", - dev->name, length, - (skb->data[ETH_ALEN+ETH_ALEN] << 8) - | skb->data[ETH_ALEN+ETH_ALEN+1]); - - skb->protocol=eth_type_trans(skb,dev); - netif_rx(skb); - dev->stats.rx_packets++; - dev->stats.rx_bytes += length; -} - -/* The inverse routine to net_open(). */ -static int -net_close(struct net_device *dev) -{ - - writereg(dev, PP_RxCFG, 0); - writereg(dev, PP_TxCFG, 0); - writereg(dev, PP_BufCFG, 0); - writereg(dev, PP_BusCTL, 0); - - netif_stop_queue(dev); - - free_irq(dev->irq, dev); - - /* Update the statistics here. */ - - return 0; - -} - -/* Get the current statistics. This may be called with the card open or - closed. */ -static struct net_device_stats * -net_get_stats(struct net_device *dev) -{ - unsigned long flags; - - local_irq_save(flags); - /* Update the statistics from the device registers. */ - dev->stats.rx_missed_errors += (readreg(dev, PP_RxMiss) >> 6); - dev->stats.collisions += (readreg(dev, PP_TxCol) >> 6); - local_irq_restore(flags); - - return &dev->stats; -} - -static void set_multicast_list(struct net_device *dev) -{ - struct net_local *lp = netdev_priv(dev); - - if(dev->flags&IFF_PROMISC) - { - lp->rx_mode = RX_ALL_ACCEPT; - } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) { - /* The multicast-accept list is initialized to accept-all, and we - rely on higher-level filtering for now. */ - lp->rx_mode = RX_MULTCAST_ACCEPT; - } - else - lp->rx_mode = 0; - - writereg(dev, PP_RxCTL, DEF_RX_ACCEPT | lp->rx_mode); - - /* in promiscuous mode, we accept errored packets, so we have to enable interrupts on them also */ - writereg(dev, PP_RxCFG, lp->curr_rx_cfg | - (lp->rx_mode == RX_ALL_ACCEPT? (RX_CRC_ERROR_ENBL|RX_RUNT_ENBL|RX_EXTRA_DATA_ENBL) : 0)); -} - - -static int set_mac_address(struct net_device *dev, void *addr) -{ - int i; - printk("%s: Setting MAC address to ", dev->name); - for (i = 0; i < 6; i++) - printk(" %2.2x", dev->dev_addr[i] = ((unsigned char *)addr)[i]); - printk(".\n"); - /* set the Ethernet address */ - for (i=0; i < ETH_ALEN/2; i++) - writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); - - return 0; -} - -#ifdef MODULE - -static struct net_device *dev_cs89x0; -static int debug; - -module_param(debug, int, 0); -MODULE_PARM_DESC(debug, "CS89[02]0 debug level (0-5)"); -MODULE_LICENSE("GPL"); - -int __init -init_module(void) -{ - net_debug = debug; - dev_cs89x0 = mac89x0_probe(-1); - if (IS_ERR(dev_cs89x0)) { - printk(KERN_WARNING "mac89x0.c: No card found\n"); - return PTR_ERR(dev_cs89x0); - } - return 0; -} - -void -cleanup_module(void) -{ - unregister_netdev(dev_cs89x0); - nubus_writew(0, dev_cs89x0->base_addr + ADD_PORT); - free_netdev(dev_cs89x0); -} -#endif /* MODULE */ diff --git a/drivers/net/mace.c b/drivers/net/mace.c deleted file mode 100644 index 2074e9724ba..00000000000 --- a/drivers/net/mace.c +++ /dev/null @@ -1,1031 +0,0 @@ -/* - * Network device driver for the MACE ethernet controller on - * Apple Powermacs. Assumes it's under a DBDMA controller. - * - * Copyright (C) 1996 Paul Mackerras. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mace.h" - -static int port_aaui = -1; - -#define N_RX_RING 8 -#define N_TX_RING 6 -#define MAX_TX_ACTIVE 1 -#define NCMDS_TX 1 /* dma commands per element in tx ring */ -#define RX_BUFLEN (ETH_FRAME_LEN + 8) -#define TX_TIMEOUT HZ /* 1 second */ - -/* Chip rev needs workaround on HW & multicast addr change */ -#define BROKEN_ADDRCHG_REV 0x0941 - -/* Bits in transmit DMA status */ -#define TX_DMA_ERR 0x80 - -struct mace_data { - volatile struct mace __iomem *mace; - volatile struct dbdma_regs __iomem *tx_dma; - int tx_dma_intr; - volatile struct dbdma_regs __iomem *rx_dma; - int rx_dma_intr; - volatile struct dbdma_cmd *tx_cmds; /* xmit dma command list */ - volatile struct dbdma_cmd *rx_cmds; /* recv dma command list */ - struct sk_buff *rx_bufs[N_RX_RING]; - int rx_fill; - int rx_empty; - struct sk_buff *tx_bufs[N_TX_RING]; - int tx_fill; - int tx_empty; - unsigned char maccc; - unsigned char tx_fullup; - unsigned char tx_active; - unsigned char tx_bad_runt; - struct timer_list tx_timeout; - int timeout_active; - int port_aaui; - int chipid; - struct macio_dev *mdev; - spinlock_t lock; -}; - -/* - * Number of bytes of private data per MACE: allow enough for - * the rx and tx dma commands plus a branch dma command each, - * and another 16 bytes to allow us to align the dma command - * buffers on a 16 byte boundary. - */ -#define PRIV_BYTES (sizeof(struct mace_data) \ - + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd)) - -static int mace_open(struct net_device *dev); -static int mace_close(struct net_device *dev); -static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); -static void mace_set_multicast(struct net_device *dev); -static void mace_reset(struct net_device *dev); -static int mace_set_address(struct net_device *dev, void *addr); -static irqreturn_t mace_interrupt(int irq, void *dev_id); -static irqreturn_t mace_txdma_intr(int irq, void *dev_id); -static irqreturn_t mace_rxdma_intr(int irq, void *dev_id); -static void mace_set_timeout(struct net_device *dev); -static void mace_tx_timeout(unsigned long data); -static inline void dbdma_reset(volatile struct dbdma_regs __iomem *dma); -static inline void mace_clean_rings(struct mace_data *mp); -static void __mace_set_address(struct net_device *dev, void *addr); - -/* - * If we can't get a skbuff when we need it, we use this area for DMA. - */ -static unsigned char *dummy_buf; - -static const struct net_device_ops mace_netdev_ops = { - .ndo_open = mace_open, - .ndo_stop = mace_close, - .ndo_start_xmit = mace_xmit_start, - .ndo_set_multicast_list = mace_set_multicast, - .ndo_set_mac_address = mace_set_address, - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, -}; - -static int __devinit mace_probe(struct macio_dev *mdev, const struct of_device_id *match) -{ - struct device_node *mace = macio_get_of_node(mdev); - struct net_device *dev; - struct mace_data *mp; - const unsigned char *addr; - int j, rev, rc = -EBUSY; - - if (macio_resource_count(mdev) != 3 || macio_irq_count(mdev) != 3) { - printk(KERN_ERR "can't use MACE %s: need 3 addrs and 3 irqs\n", - mace->full_name); - return -ENODEV; - } - - addr = of_get_property(mace, "mac-address", NULL); - if (addr == NULL) { - addr = of_get_property(mace, "local-mac-address", NULL); - if (addr == NULL) { - printk(KERN_ERR "Can't get mac-address for MACE %s\n", - mace->full_name); - return -ENODEV; - } - } - - /* - * lazy allocate the driver-wide dummy buffer. (Note that we - * never have more than one MACE in the system anyway) - */ - if (dummy_buf == NULL) { - dummy_buf = kmalloc(RX_BUFLEN+2, GFP_KERNEL); - if (dummy_buf == NULL) { - printk(KERN_ERR "MACE: couldn't allocate dummy buffer\n"); - return -ENOMEM; - } - } - - if (macio_request_resources(mdev, "mace")) { - printk(KERN_ERR "MACE: can't request IO resources !\n"); - return -EBUSY; - } - - dev = alloc_etherdev(PRIV_BYTES); - if (!dev) { - printk(KERN_ERR "MACE: can't allocate ethernet device !\n"); - rc = -ENOMEM; - goto err_release; - } - SET_NETDEV_DEV(dev, &mdev->ofdev.dev); - - mp = netdev_priv(dev); - mp->mdev = mdev; - macio_set_drvdata(mdev, dev); - - dev->base_addr = macio_resource_start(mdev, 0); - mp->mace = ioremap(dev->base_addr, 0x1000); - if (mp->mace == NULL) { - printk(KERN_ERR "MACE: can't map IO resources !\n"); - rc = -ENOMEM; - goto err_free; - } - dev->irq = macio_irq(mdev, 0); - - rev = addr[0] == 0 && addr[1] == 0xA0; - for (j = 0; j < 6; ++j) { - dev->dev_addr[j] = rev ? bitrev8(addr[j]): addr[j]; - } - mp->chipid = (in_8(&mp->mace->chipid_hi) << 8) | - in_8(&mp->mace->chipid_lo); - - - mp = netdev_priv(dev); - mp->maccc = ENXMT | ENRCV; - - mp->tx_dma = ioremap(macio_resource_start(mdev, 1), 0x1000); - if (mp->tx_dma == NULL) { - printk(KERN_ERR "MACE: can't map TX DMA resources !\n"); - rc = -ENOMEM; - goto err_unmap_io; - } - mp->tx_dma_intr = macio_irq(mdev, 1); - - mp->rx_dma = ioremap(macio_resource_start(mdev, 2), 0x1000); - if (mp->rx_dma == NULL) { - printk(KERN_ERR "MACE: can't map RX DMA resources !\n"); - rc = -ENOMEM; - goto err_unmap_tx_dma; - } - mp->rx_dma_intr = macio_irq(mdev, 2); - - mp->tx_cmds = (volatile struct dbdma_cmd *) DBDMA_ALIGN(mp + 1); - mp->rx_cmds = mp->tx_cmds + NCMDS_TX * N_TX_RING + 1; - - memset((char *) mp->tx_cmds, 0, - (NCMDS_TX*N_TX_RING + N_RX_RING + 2) * sizeof(struct dbdma_cmd)); - init_timer(&mp->tx_timeout); - spin_lock_init(&mp->lock); - mp->timeout_active = 0; - - if (port_aaui >= 0) - mp->port_aaui = port_aaui; - else { - /* Apple Network Server uses the AAUI port */ - if (of_machine_is_compatible("AAPL,ShinerESB")) - mp->port_aaui = 1; - else { -#ifdef CONFIG_MACE_AAUI_PORT - mp->port_aaui = 1; -#else - mp->port_aaui = 0; -#endif - } - } - - dev->netdev_ops = &mace_netdev_ops; - - /* - * Most of what is below could be moved to mace_open() - */ - mace_reset(dev); - - rc = request_irq(dev->irq, mace_interrupt, 0, "MACE", dev); - if (rc) { - printk(KERN_ERR "MACE: can't get irq %d\n", dev->irq); - goto err_unmap_rx_dma; - } - rc = request_irq(mp->tx_dma_intr, mace_txdma_intr, 0, "MACE-txdma", dev); - if (rc) { - printk(KERN_ERR "MACE: can't get irq %d\n", mp->tx_dma_intr); - goto err_free_irq; - } - rc = request_irq(mp->rx_dma_intr, mace_rxdma_intr, 0, "MACE-rxdma", dev); - if (rc) { - printk(KERN_ERR "MACE: can't get irq %d\n", mp->rx_dma_intr); - goto err_free_tx_irq; - } - - rc = register_netdev(dev); - if (rc) { - printk(KERN_ERR "MACE: Cannot register net device, aborting.\n"); - goto err_free_rx_irq; - } - - printk(KERN_INFO "%s: MACE at %pM, chip revision %d.%d\n", - dev->name, dev->dev_addr, - mp->chipid >> 8, mp->chipid & 0xff); - - return 0; - - err_free_rx_irq: - free_irq(macio_irq(mdev, 2), dev); - err_free_tx_irq: - free_irq(macio_irq(mdev, 1), dev); - err_free_irq: - free_irq(macio_irq(mdev, 0), dev); - err_unmap_rx_dma: - iounmap(mp->rx_dma); - err_unmap_tx_dma: - iounmap(mp->tx_dma); - err_unmap_io: - iounmap(mp->mace); - err_free: - free_netdev(dev); - err_release: - macio_release_resources(mdev); - - return rc; -} - -static int __devexit mace_remove(struct macio_dev *mdev) -{ - struct net_device *dev = macio_get_drvdata(mdev); - struct mace_data *mp; - - BUG_ON(dev == NULL); - - macio_set_drvdata(mdev, NULL); - - mp = netdev_priv(dev); - - unregister_netdev(dev); - - free_irq(dev->irq, dev); - free_irq(mp->tx_dma_intr, dev); - free_irq(mp->rx_dma_intr, dev); - - iounmap(mp->rx_dma); - iounmap(mp->tx_dma); - iounmap(mp->mace); - - free_netdev(dev); - - macio_release_resources(mdev); - - return 0; -} - -static void dbdma_reset(volatile struct dbdma_regs __iomem *dma) -{ - int i; - - out_le32(&dma->control, (WAKE|FLUSH|PAUSE|RUN) << 16); - - /* - * Yes this looks peculiar, but apparently it needs to be this - * way on some machines. - */ - for (i = 200; i > 0; --i) - if (ld_le32(&dma->control) & RUN) - udelay(1); -} - -static void mace_reset(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - int i; - - /* soft-reset the chip */ - i = 200; - while (--i) { - out_8(&mb->biucc, SWRST); - if (in_8(&mb->biucc) & SWRST) { - udelay(10); - continue; - } - break; - } - if (!i) { - printk(KERN_ERR "mace: cannot reset chip!\n"); - return; - } - - out_8(&mb->imr, 0xff); /* disable all intrs for now */ - i = in_8(&mb->ir); - out_8(&mb->maccc, 0); /* turn off tx, rx */ - - out_8(&mb->biucc, XMTSP_64); - out_8(&mb->utr, RTRD); - out_8(&mb->fifocc, RCVFW_32 | XMTFW_16 | XMTFWU | RCVFWU | XMTBRST); - out_8(&mb->xmtfc, AUTO_PAD_XMIT); /* auto-pad short frames */ - out_8(&mb->rcvfc, 0); - - /* load up the hardware address */ - __mace_set_address(dev, dev->dev_addr); - - /* clear the multicast filter */ - if (mp->chipid == BROKEN_ADDRCHG_REV) - out_8(&mb->iac, LOGADDR); - else { - out_8(&mb->iac, ADDRCHG | LOGADDR); - while ((in_8(&mb->iac) & ADDRCHG) != 0) - ; - } - for (i = 0; i < 8; ++i) - out_8(&mb->ladrf, 0); - - /* done changing address */ - if (mp->chipid != BROKEN_ADDRCHG_REV) - out_8(&mb->iac, 0); - - if (mp->port_aaui) - out_8(&mb->plscc, PORTSEL_AUI + ENPLSIO); - else - out_8(&mb->plscc, PORTSEL_GPSI + ENPLSIO); -} - -static void __mace_set_address(struct net_device *dev, void *addr) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - unsigned char *p = addr; - int i; - - /* load up the hardware address */ - if (mp->chipid == BROKEN_ADDRCHG_REV) - out_8(&mb->iac, PHYADDR); - else { - out_8(&mb->iac, ADDRCHG | PHYADDR); - while ((in_8(&mb->iac) & ADDRCHG) != 0) - ; - } - for (i = 0; i < 6; ++i) - out_8(&mb->padr, dev->dev_addr[i] = p[i]); - if (mp->chipid != BROKEN_ADDRCHG_REV) - out_8(&mb->iac, 0); -} - -static int mace_set_address(struct net_device *dev, void *addr) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - unsigned long flags; - - spin_lock_irqsave(&mp->lock, flags); - - __mace_set_address(dev, addr); - - /* note: setting ADDRCHG clears ENRCV */ - out_8(&mb->maccc, mp->maccc); - - spin_unlock_irqrestore(&mp->lock, flags); - return 0; -} - -static inline void mace_clean_rings(struct mace_data *mp) -{ - int i; - - /* free some skb's */ - for (i = 0; i < N_RX_RING; ++i) { - if (mp->rx_bufs[i] != NULL) { - dev_kfree_skb(mp->rx_bufs[i]); - mp->rx_bufs[i] = NULL; - } - } - for (i = mp->tx_empty; i != mp->tx_fill; ) { - dev_kfree_skb(mp->tx_bufs[i]); - if (++i >= N_TX_RING) - i = 0; - } -} - -static int mace_open(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - volatile struct dbdma_regs __iomem *rd = mp->rx_dma; - volatile struct dbdma_regs __iomem *td = mp->tx_dma; - volatile struct dbdma_cmd *cp; - int i; - struct sk_buff *skb; - unsigned char *data; - - /* reset the chip */ - mace_reset(dev); - - /* initialize list of sk_buffs for receiving and set up recv dma */ - mace_clean_rings(mp); - memset((char *)mp->rx_cmds, 0, N_RX_RING * sizeof(struct dbdma_cmd)); - cp = mp->rx_cmds; - for (i = 0; i < N_RX_RING - 1; ++i) { - skb = dev_alloc_skb(RX_BUFLEN + 2); - if (!skb) { - data = dummy_buf; - } else { - skb_reserve(skb, 2); /* so IP header lands on 4-byte bdry */ - data = skb->data; - } - mp->rx_bufs[i] = skb; - st_le16(&cp->req_count, RX_BUFLEN); - st_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); - st_le32(&cp->phy_addr, virt_to_bus(data)); - cp->xfer_status = 0; - ++cp; - } - mp->rx_bufs[i] = NULL; - st_le16(&cp->command, DBDMA_STOP); - mp->rx_fill = i; - mp->rx_empty = 0; - - /* Put a branch back to the beginning of the receive command list */ - ++cp; - st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); - st_le32(&cp->cmd_dep, virt_to_bus(mp->rx_cmds)); - - /* start rx dma */ - out_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ - out_le32(&rd->cmdptr, virt_to_bus(mp->rx_cmds)); - out_le32(&rd->control, (RUN << 16) | RUN); - - /* put a branch at the end of the tx command list */ - cp = mp->tx_cmds + NCMDS_TX * N_TX_RING; - st_le16(&cp->command, DBDMA_NOP + BR_ALWAYS); - st_le32(&cp->cmd_dep, virt_to_bus(mp->tx_cmds)); - - /* reset tx dma */ - out_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); - out_le32(&td->cmdptr, virt_to_bus(mp->tx_cmds)); - mp->tx_fill = 0; - mp->tx_empty = 0; - mp->tx_fullup = 0; - mp->tx_active = 0; - mp->tx_bad_runt = 0; - - /* turn it on! */ - out_8(&mb->maccc, mp->maccc); - /* enable all interrupts except receive interrupts */ - out_8(&mb->imr, RCVINT); - - return 0; -} - -static int mace_close(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - volatile struct dbdma_regs __iomem *rd = mp->rx_dma; - volatile struct dbdma_regs __iomem *td = mp->tx_dma; - - /* disable rx and tx */ - out_8(&mb->maccc, 0); - out_8(&mb->imr, 0xff); /* disable all intrs */ - - /* disable rx and tx dma */ - st_le32(&rd->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ - st_le32(&td->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* clear run bit */ - - mace_clean_rings(mp); - - return 0; -} - -static inline void mace_set_timeout(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - - if (mp->timeout_active) - del_timer(&mp->tx_timeout); - mp->tx_timeout.expires = jiffies + TX_TIMEOUT; - mp->tx_timeout.function = mace_tx_timeout; - mp->tx_timeout.data = (unsigned long) dev; - add_timer(&mp->tx_timeout); - mp->timeout_active = 1; -} - -static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *td = mp->tx_dma; - volatile struct dbdma_cmd *cp, *np; - unsigned long flags; - int fill, next, len; - - /* see if there's a free slot in the tx ring */ - spin_lock_irqsave(&mp->lock, flags); - fill = mp->tx_fill; - next = fill + 1; - if (next >= N_TX_RING) - next = 0; - if (next == mp->tx_empty) { - netif_stop_queue(dev); - mp->tx_fullup = 1; - spin_unlock_irqrestore(&mp->lock, flags); - return NETDEV_TX_BUSY; /* can't take it at the moment */ - } - spin_unlock_irqrestore(&mp->lock, flags); - - /* partially fill in the dma command block */ - len = skb->len; - if (len > ETH_FRAME_LEN) { - printk(KERN_DEBUG "mace: xmit frame too long (%d)\n", len); - len = ETH_FRAME_LEN; - } - mp->tx_bufs[fill] = skb; - cp = mp->tx_cmds + NCMDS_TX * fill; - st_le16(&cp->req_count, len); - st_le32(&cp->phy_addr, virt_to_bus(skb->data)); - - np = mp->tx_cmds + NCMDS_TX * next; - out_le16(&np->command, DBDMA_STOP); - - /* poke the tx dma channel */ - spin_lock_irqsave(&mp->lock, flags); - mp->tx_fill = next; - if (!mp->tx_bad_runt && mp->tx_active < MAX_TX_ACTIVE) { - out_le16(&cp->xfer_status, 0); - out_le16(&cp->command, OUTPUT_LAST); - out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); - ++mp->tx_active; - mace_set_timeout(dev); - } - if (++next >= N_TX_RING) - next = 0; - if (next == mp->tx_empty) - netif_stop_queue(dev); - spin_unlock_irqrestore(&mp->lock, flags); - - return NETDEV_TX_OK; -} - -static void mace_set_multicast(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - int i; - u32 crc; - unsigned long flags; - - spin_lock_irqsave(&mp->lock, flags); - mp->maccc &= ~PROM; - if (dev->flags & IFF_PROMISC) { - mp->maccc |= PROM; - } else { - unsigned char multicast_filter[8]; - struct netdev_hw_addr *ha; - - if (dev->flags & IFF_ALLMULTI) { - for (i = 0; i < 8; i++) - multicast_filter[i] = 0xff; - } else { - for (i = 0; i < 8; i++) - multicast_filter[i] = 0; - netdev_for_each_mc_addr(ha, dev) { - crc = ether_crc_le(6, ha->addr); - i = crc >> 26; /* bit number in multicast_filter */ - multicast_filter[i >> 3] |= 1 << (i & 7); - } - } -#if 0 - printk("Multicast filter :"); - for (i = 0; i < 8; i++) - printk("%02x ", multicast_filter[i]); - printk("\n"); -#endif - - if (mp->chipid == BROKEN_ADDRCHG_REV) - out_8(&mb->iac, LOGADDR); - else { - out_8(&mb->iac, ADDRCHG | LOGADDR); - while ((in_8(&mb->iac) & ADDRCHG) != 0) - ; - } - for (i = 0; i < 8; ++i) - out_8(&mb->ladrf, multicast_filter[i]); - if (mp->chipid != BROKEN_ADDRCHG_REV) - out_8(&mb->iac, 0); - } - /* reset maccc */ - out_8(&mb->maccc, mp->maccc); - spin_unlock_irqrestore(&mp->lock, flags); -} - -static void mace_handle_misc_intrs(struct mace_data *mp, int intr, struct net_device *dev) -{ - volatile struct mace __iomem *mb = mp->mace; - static int mace_babbles, mace_jabbers; - - if (intr & MPCO) - dev->stats.rx_missed_errors += 256; - dev->stats.rx_missed_errors += in_8(&mb->mpc); /* reading clears it */ - if (intr & RNTPCO) - dev->stats.rx_length_errors += 256; - dev->stats.rx_length_errors += in_8(&mb->rntpc); /* reading clears it */ - if (intr & CERR) - ++dev->stats.tx_heartbeat_errors; - if (intr & BABBLE) - if (mace_babbles++ < 4) - printk(KERN_DEBUG "mace: babbling transmitter\n"); - if (intr & JABBER) - if (mace_jabbers++ < 4) - printk(KERN_DEBUG "mace: jabbering transceiver\n"); -} - -static irqreturn_t mace_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - volatile struct dbdma_regs __iomem *td = mp->tx_dma; - volatile struct dbdma_cmd *cp; - int intr, fs, i, stat, x; - int xcount, dstat; - unsigned long flags; - /* static int mace_last_fs, mace_last_xcount; */ - - spin_lock_irqsave(&mp->lock, flags); - intr = in_8(&mb->ir); /* read interrupt register */ - in_8(&mb->xmtrc); /* get retries */ - mace_handle_misc_intrs(mp, intr, dev); - - i = mp->tx_empty; - while (in_8(&mb->pr) & XMTSV) { - del_timer(&mp->tx_timeout); - mp->timeout_active = 0; - /* - * Clear any interrupt indication associated with this status - * word. This appears to unlatch any error indication from - * the DMA controller. - */ - intr = in_8(&mb->ir); - if (intr != 0) - mace_handle_misc_intrs(mp, intr, dev); - if (mp->tx_bad_runt) { - fs = in_8(&mb->xmtfs); - mp->tx_bad_runt = 0; - out_8(&mb->xmtfc, AUTO_PAD_XMIT); - continue; - } - dstat = ld_le32(&td->status); - /* stop DMA controller */ - out_le32(&td->control, RUN << 16); - /* - * xcount is the number of complete frames which have been - * written to the fifo but for which status has not been read. - */ - xcount = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; - if (xcount == 0 || (dstat & DEAD)) { - /* - * If a packet was aborted before the DMA controller has - * finished transferring it, it seems that there are 2 bytes - * which are stuck in some buffer somewhere. These will get - * transmitted as soon as we read the frame status (which - * reenables the transmit data transfer request). Turning - * off the DMA controller and/or resetting the MACE doesn't - * help. So we disable auto-padding and FCS transmission - * so the two bytes will only be a runt packet which should - * be ignored by other stations. - */ - out_8(&mb->xmtfc, DXMTFCS); - } - fs = in_8(&mb->xmtfs); - if ((fs & XMTSV) == 0) { - printk(KERN_ERR "mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n", - fs, xcount, dstat); - mace_reset(dev); - /* - * XXX mace likes to hang the machine after a xmtfs error. - * This is hard to reproduce, reseting *may* help - */ - } - cp = mp->tx_cmds + NCMDS_TX * i; - stat = ld_le16(&cp->xfer_status); - if ((fs & (UFLO|LCOL|LCAR|RTRY)) || (dstat & DEAD) || xcount == 0) { - /* - * Check whether there were in fact 2 bytes written to - * the transmit FIFO. - */ - udelay(1); - x = (in_8(&mb->fifofc) >> XMTFC_SH) & XMTFC_MASK; - if (x != 0) { - /* there were two bytes with an end-of-packet indication */ - mp->tx_bad_runt = 1; - mace_set_timeout(dev); - } else { - /* - * Either there weren't the two bytes buffered up, or they - * didn't have an end-of-packet indication. - * We flush the transmit FIFO just in case (by setting the - * XMTFWU bit with the transmitter disabled). - */ - out_8(&mb->maccc, in_8(&mb->maccc) & ~ENXMT); - out_8(&mb->fifocc, in_8(&mb->fifocc) | XMTFWU); - udelay(1); - out_8(&mb->maccc, in_8(&mb->maccc) | ENXMT); - out_8(&mb->xmtfc, AUTO_PAD_XMIT); - } - } - /* dma should have finished */ - if (i == mp->tx_fill) { - printk(KERN_DEBUG "mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n", - fs, xcount, dstat); - continue; - } - /* Update stats */ - if (fs & (UFLO|LCOL|LCAR|RTRY)) { - ++dev->stats.tx_errors; - if (fs & LCAR) - ++dev->stats.tx_carrier_errors; - if (fs & (UFLO|LCOL|RTRY)) - ++dev->stats.tx_aborted_errors; - } else { - dev->stats.tx_bytes += mp->tx_bufs[i]->len; - ++dev->stats.tx_packets; - } - dev_kfree_skb_irq(mp->tx_bufs[i]); - --mp->tx_active; - if (++i >= N_TX_RING) - i = 0; -#if 0 - mace_last_fs = fs; - mace_last_xcount = xcount; -#endif - } - - if (i != mp->tx_empty) { - mp->tx_fullup = 0; - netif_wake_queue(dev); - } - mp->tx_empty = i; - i += mp->tx_active; - if (i >= N_TX_RING) - i -= N_TX_RING; - if (!mp->tx_bad_runt && i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE) { - do { - /* set up the next one */ - cp = mp->tx_cmds + NCMDS_TX * i; - out_le16(&cp->xfer_status, 0); - out_le16(&cp->command, OUTPUT_LAST); - ++mp->tx_active; - if (++i >= N_TX_RING) - i = 0; - } while (i != mp->tx_fill && mp->tx_active < MAX_TX_ACTIVE); - out_le32(&td->control, ((RUN|WAKE) << 16) + (RUN|WAKE)); - mace_set_timeout(dev); - } - spin_unlock_irqrestore(&mp->lock, flags); - return IRQ_HANDLED; -} - -static void mace_tx_timeout(unsigned long data) -{ - struct net_device *dev = (struct net_device *) data; - struct mace_data *mp = netdev_priv(dev); - volatile struct mace __iomem *mb = mp->mace; - volatile struct dbdma_regs __iomem *td = mp->tx_dma; - volatile struct dbdma_regs __iomem *rd = mp->rx_dma; - volatile struct dbdma_cmd *cp; - unsigned long flags; - int i; - - spin_lock_irqsave(&mp->lock, flags); - mp->timeout_active = 0; - if (mp->tx_active == 0 && !mp->tx_bad_runt) - goto out; - - /* update various counters */ - mace_handle_misc_intrs(mp, in_8(&mb->ir), dev); - - cp = mp->tx_cmds + NCMDS_TX * mp->tx_empty; - - /* turn off both tx and rx and reset the chip */ - out_8(&mb->maccc, 0); - printk(KERN_ERR "mace: transmit timeout - resetting\n"); - dbdma_reset(td); - mace_reset(dev); - - /* restart rx dma */ - cp = bus_to_virt(ld_le32(&rd->cmdptr)); - dbdma_reset(rd); - out_le16(&cp->xfer_status, 0); - out_le32(&rd->cmdptr, virt_to_bus(cp)); - out_le32(&rd->control, (RUN << 16) | RUN); - - /* fix up the transmit side */ - i = mp->tx_empty; - mp->tx_active = 0; - ++dev->stats.tx_errors; - if (mp->tx_bad_runt) { - mp->tx_bad_runt = 0; - } else if (i != mp->tx_fill) { - dev_kfree_skb(mp->tx_bufs[i]); - if (++i >= N_TX_RING) - i = 0; - mp->tx_empty = i; - } - mp->tx_fullup = 0; - netif_wake_queue(dev); - if (i != mp->tx_fill) { - cp = mp->tx_cmds + NCMDS_TX * i; - out_le16(&cp->xfer_status, 0); - out_le16(&cp->command, OUTPUT_LAST); - out_le32(&td->cmdptr, virt_to_bus(cp)); - out_le32(&td->control, (RUN << 16) | RUN); - ++mp->tx_active; - mace_set_timeout(dev); - } - - /* turn it back on */ - out_8(&mb->imr, RCVINT); - out_8(&mb->maccc, mp->maccc); - -out: - spin_unlock_irqrestore(&mp->lock, flags); -} - -static irqreturn_t mace_txdma_intr(int irq, void *dev_id) -{ - return IRQ_HANDLED; -} - -static irqreturn_t mace_rxdma_intr(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct mace_data *mp = netdev_priv(dev); - volatile struct dbdma_regs __iomem *rd = mp->rx_dma; - volatile struct dbdma_cmd *cp, *np; - int i, nb, stat, next; - struct sk_buff *skb; - unsigned frame_status; - static int mace_lost_status; - unsigned char *data; - unsigned long flags; - - spin_lock_irqsave(&mp->lock, flags); - for (i = mp->rx_empty; i != mp->rx_fill; ) { - cp = mp->rx_cmds + i; - stat = ld_le16(&cp->xfer_status); - if ((stat & ACTIVE) == 0) { - next = i + 1; - if (next >= N_RX_RING) - next = 0; - np = mp->rx_cmds + next; - if (next != mp->rx_fill && - (ld_le16(&np->xfer_status) & ACTIVE) != 0) { - printk(KERN_DEBUG "mace: lost a status word\n"); - ++mace_lost_status; - } else - break; - } - nb = ld_le16(&cp->req_count) - ld_le16(&cp->res_count); - out_le16(&cp->command, DBDMA_STOP); - /* got a packet, have a look at it */ - skb = mp->rx_bufs[i]; - if (!skb) { - ++dev->stats.rx_dropped; - } else if (nb > 8) { - data = skb->data; - frame_status = (data[nb-3] << 8) + data[nb-4]; - if (frame_status & (RS_OFLO|RS_CLSN|RS_FRAMERR|RS_FCSERR)) { - ++dev->stats.rx_errors; - if (frame_status & RS_OFLO) - ++dev->stats.rx_over_errors; - if (frame_status & RS_FRAMERR) - ++dev->stats.rx_frame_errors; - if (frame_status & RS_FCSERR) - ++dev->stats.rx_crc_errors; - } else { - /* Mace feature AUTO_STRIP_RCV is on by default, dropping the - * FCS on frames with 802.3 headers. This means that Ethernet - * frames have 8 extra octets at the end, while 802.3 frames - * have only 4. We need to correctly account for this. */ - if (*(unsigned short *)(data+12) < 1536) /* 802.3 header */ - nb -= 4; - else /* Ethernet header; mace includes FCS */ - nb -= 8; - skb_put(skb, nb); - skb->protocol = eth_type_trans(skb, dev); - dev->stats.rx_bytes += skb->len; - netif_rx(skb); - mp->rx_bufs[i] = NULL; - ++dev->stats.rx_packets; - } - } else { - ++dev->stats.rx_errors; - ++dev->stats.rx_length_errors; - } - - /* advance to next */ - if (++i >= N_RX_RING) - i = 0; - } - mp->rx_empty = i; - - i = mp->rx_fill; - for (;;) { - next = i + 1; - if (next >= N_RX_RING) - next = 0; - if (next == mp->rx_empty) - break; - cp = mp->rx_cmds + i; - skb = mp->rx_bufs[i]; - if (!skb) { - skb = dev_alloc_skb(RX_BUFLEN + 2); - if (skb) { - skb_reserve(skb, 2); - mp->rx_bufs[i] = skb; - } - } - st_le16(&cp->req_count, RX_BUFLEN); - data = skb? skb->data: dummy_buf; - st_le32(&cp->phy_addr, virt_to_bus(data)); - out_le16(&cp->xfer_status, 0); - out_le16(&cp->command, INPUT_LAST + INTR_ALWAYS); -#if 0 - if ((ld_le32(&rd->status) & ACTIVE) != 0) { - out_le32(&rd->control, (PAUSE << 16) | PAUSE); - while ((in_le32(&rd->status) & ACTIVE) != 0) - ; - } -#endif - i = next; - } - if (i != mp->rx_fill) { - out_le32(&rd->control, ((RUN|WAKE) << 16) | (RUN|WAKE)); - mp->rx_fill = i; - } - spin_unlock_irqrestore(&mp->lock, flags); - return IRQ_HANDLED; -} - -static struct of_device_id mace_match[] = -{ - { - .name = "mace", - }, - {}, -}; -MODULE_DEVICE_TABLE (of, mace_match); - -static struct macio_driver mace_driver = -{ - .driver = { - .name = "mace", - .owner = THIS_MODULE, - .of_match_table = mace_match, - }, - .probe = mace_probe, - .remove = mace_remove, -}; - - -static int __init mace_init(void) -{ - return macio_register_driver(&mace_driver); -} - -static void __exit mace_cleanup(void) -{ - macio_unregister_driver(&mace_driver); - - kfree(dummy_buf); - dummy_buf = NULL; -} - -MODULE_AUTHOR("Paul Mackerras"); -MODULE_DESCRIPTION("PowerMac MACE driver."); -module_param(port_aaui, int, 0); -MODULE_PARM_DESC(port_aaui, "MACE uses AAUI port (0-1)"); -MODULE_LICENSE("GPL"); - -module_init(mace_init); -module_exit(mace_cleanup); diff --git a/drivers/net/mace.h b/drivers/net/mace.h deleted file mode 100644 index 30b7ec0cedb..00000000000 --- a/drivers/net/mace.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * mace.h - definitions for the registers in the Am79C940 MACE - * (Medium Access Control for Ethernet) controller. - * - * Copyright (C) 1996 Paul Mackerras. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#define REG(x) volatile unsigned char x; char x ## _pad[15] - -struct mace { - REG(rcvfifo); /* receive FIFO */ - REG(xmtfifo); /* transmit FIFO */ - REG(xmtfc); /* transmit frame control */ - REG(xmtfs); /* transmit frame status */ - REG(xmtrc); /* transmit retry count */ - REG(rcvfc); /* receive frame control */ - REG(rcvfs); /* receive frame status (4 bytes) */ - REG(fifofc); /* FIFO frame count */ - REG(ir); /* interrupt register */ - REG(imr); /* interrupt mask register */ - REG(pr); /* poll register */ - REG(biucc); /* bus interface unit config control */ - REG(fifocc); /* FIFO configuration control */ - REG(maccc); /* medium access control config control */ - REG(plscc); /* phys layer signalling config control */ - REG(phycc); /* physical configuration control */ - REG(chipid_lo); /* chip ID, lsb */ - REG(chipid_hi); /* chip ID, msb */ - REG(iac); /* internal address config */ - REG(reg19); - REG(ladrf); /* logical address filter (8 bytes) */ - REG(padr); /* physical address (6 bytes) */ - REG(reg22); - REG(reg23); - REG(mpc); /* missed packet count (clears when read) */ - REG(reg25); - REG(rntpc); /* runt packet count (clears when read) */ - REG(rcvcc); /* recv collision count (clears when read) */ - REG(reg28); - REG(utr); /* user test reg */ - REG(reg30); - REG(reg31); -}; - -/* Bits in XMTFC */ -#define DRTRY 0x80 /* don't retry transmission after collision */ -#define DXMTFCS 0x08 /* don't append FCS to transmitted frame */ -#define AUTO_PAD_XMIT 0x01 /* auto-pad short packets on transmission */ - -/* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */ -#define XMTSV 0x80 /* transmit status (i.e. XMTFS) valid */ -#define UFLO 0x40 /* underflow - xmit fifo ran dry */ -#define LCOL 0x20 /* late collision (transmission aborted) */ -#define MORE 0x10 /* 2 or more retries needed to xmit frame */ -#define ONE 0x08 /* 1 retry needed to xmit frame */ -#define DEFER 0x04 /* MACE had to defer xmission (enet busy) */ -#define LCAR 0x02 /* loss of carrier (transmission aborted) */ -#define RTRY 0x01 /* too many retries (transmission aborted) */ - -/* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */ -#define EXDEF 0x80 /* had to defer for excessive time */ -#define RETRY_MASK 0x0f /* number of retries (0 - 15) */ - -/* Bits in RCVFC */ -#define LLRCV 0x08 /* low latency receive: early DMA request */ -#define M_RBAR 0x04 /* sets function of EAM/R pin */ -#define AUTO_STRIP_RCV 0x01 /* auto-strip short LLC frames on recv */ - -/* - * Bits in RCVFS. After a frame is received, four bytes of status - * are automatically read from this register and appended to the frame - * data in memory. These are: - * Byte 0 and 1: message byte count and frame status - * Byte 2: runt packet count - * Byte 3: receive collision count - */ -#define RS_OFLO 0x8000 /* receive FIFO overflowed */ -#define RS_CLSN 0x4000 /* received frame suffered (late) collision */ -#define RS_FRAMERR 0x2000 /* framing error flag */ -#define RS_FCSERR 0x1000 /* frame had FCS error */ -#define RS_COUNT 0x0fff /* mask for byte count field */ - -/* Bits (fields) in FIFOFC */ -#define RCVFC_SH 4 /* receive frame count in FIFO */ -#define RCVFC_MASK 0x0f -#define XMTFC_SH 0 /* transmit frame count in FIFO */ -#define XMTFC_MASK 0x0f - -/* - * Bits in IR and IMR. The IR clears itself when read. - * Setting a bit in the IMR will disable the corresponding interrupt. - */ -#define JABBER 0x80 /* jabber error - 10baseT xmission too long */ -#define BABBLE 0x40 /* babble - xmitter xmitting for too long */ -#define CERR 0x20 /* collision err - no SQE test (heartbeat) */ -#define RCVCCO 0x10 /* RCVCC overflow */ -#define RNTPCO 0x08 /* RNTPC overflow */ -#define MPCO 0x04 /* MPC overflow */ -#define RCVINT 0x02 /* receive interrupt */ -#define XMTINT 0x01 /* transmitter interrupt */ - -/* Bits in PR */ -#define XMTSV 0x80 /* XMTFS valid (same as in XMTFS) */ -#define TDTREQ 0x40 /* set when xmit fifo is requesting data */ -#define RDTREQ 0x20 /* set when recv fifo requests data xfer */ - -/* Bits in BIUCC */ -#define BSWP 0x40 /* byte swap, i.e. big-endian bus */ -#define XMTSP_4 0x00 /* start xmitting when 4 bytes in FIFO */ -#define XMTSP_16 0x10 /* start xmitting when 16 bytes in FIFO */ -#define XMTSP_64 0x20 /* start xmitting when 64 bytes in FIFO */ -#define XMTSP_112 0x30 /* start xmitting when 112 bytes in FIFO */ -#define SWRST 0x01 /* software reset */ - -/* Bits in FIFOCC */ -#define XMTFW_8 0x00 /* xmit fifo watermark = 8 words free */ -#define XMTFW_16 0x40 /* 16 words free */ -#define XMTFW_32 0x80 /* 32 words free */ -#define RCVFW_16 0x00 /* recv fifo watermark = 16 bytes avail */ -#define RCVFW_32 0x10 /* 32 bytes avail */ -#define RCVFW_64 0x20 /* 64 bytes avail */ -#define XMTFWU 0x08 /* xmit fifo watermark update enable */ -#define RCVFWU 0x04 /* recv fifo watermark update enable */ -#define XMTBRST 0x02 /* enable transmit burst mode */ -#define RCVBRST 0x01 /* enable receive burst mode */ - -/* Bits in MACCC */ -#define PROM 0x80 /* promiscuous mode */ -#define DXMT2PD 0x40 /* disable xmit two-part deferral algorithm */ -#define EMBA 0x20 /* enable modified backoff algorithm */ -#define DRCVPA 0x08 /* disable receiving physical address */ -#define DRCVBC 0x04 /* disable receiving broadcasts */ -#define ENXMT 0x02 /* enable transmitter */ -#define ENRCV 0x01 /* enable receiver */ - -/* Bits in PLSCC */ -#define XMTSEL 0x08 /* select DO+/DO- state when idle */ -#define PORTSEL_AUI 0x00 /* select AUI port */ -#define PORTSEL_10T 0x02 /* select 10Base-T port */ -#define PORTSEL_DAI 0x04 /* select DAI port */ -#define PORTSEL_GPSI 0x06 /* select GPSI port */ -#define ENPLSIO 0x01 /* enable optional PLS I/O pins */ - -/* Bits in PHYCC */ -#define LNKFL 0x80 /* reports 10Base-T link failure */ -#define DLNKTST 0x40 /* disable 10Base-T link test */ -#define REVPOL 0x20 /* 10Base-T receiver polarity reversed */ -#define DAPC 0x10 /* disable auto receiver polarity correction */ -#define LRT 0x08 /* low receive threshold for long links */ -#define ASEL 0x04 /* auto-select AUI or 10Base-T port */ -#define RWAKE 0x02 /* remote wake function */ -#define AWAKE 0x01 /* auto wake function */ - -/* Bits in IAC */ -#define ADDRCHG 0x80 /* request address change */ -#define PHYADDR 0x04 /* access physical address */ -#define LOGADDR 0x02 /* access multicast filter */ - -/* Bits in UTR */ -#define RTRE 0x80 /* reserved test register enable. DON'T SET. */ -#define RTRD 0x40 /* reserved test register disable. Sticky */ -#define RPAC 0x20 /* accept runt packets */ -#define FCOLL 0x10 /* force collision */ -#define RCVFCSE 0x08 /* receive FCS enable */ -#define LOOP_NONE 0x00 /* no loopback */ -#define LOOP_EXT 0x02 /* external loopback */ -#define LOOP_INT 0x04 /* internal loopback, excludes MENDEC */ -#define LOOP_MENDEC 0x06 /* internal loopback, includes MENDEC */ diff --git a/drivers/net/macmace.c b/drivers/net/macmace.c deleted file mode 100644 index 4286e67f963..00000000000 --- a/drivers/net/macmace.c +++ /dev/null @@ -1,799 +0,0 @@ -/* - * Driver for the Macintosh 68K onboard MACE controller with PSC - * driven DMA. The MACE driver code is derived from mace.c. The - * Mac68k theory of operation is courtesy of the MacBSD wizards. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Copyright (C) 1996 Paul Mackerras. - * Copyright (C) 1998 Alan Cox - * - * Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver - * - * Copyright (C) 2007 Finn Thain - * - * Converted to DMA API, converted to unified driver model, - * sync'd some routines with mace.c and fixed various bugs. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mace.h" - -static char mac_mace_string[] = "macmace"; - -#define N_TX_BUFF_ORDER 0 -#define N_TX_RING (1 << N_TX_BUFF_ORDER) -#define N_RX_BUFF_ORDER 3 -#define N_RX_RING (1 << N_RX_BUFF_ORDER) - -#define TX_TIMEOUT HZ - -#define MACE_BUFF_SIZE 0x800 - -/* Chip rev needs workaround on HW & multicast addr change */ -#define BROKEN_ADDRCHG_REV 0x0941 - -/* The MACE is simply wired down on a Mac68K box */ - -#define MACE_BASE (void *)(0x50F1C000) -#define MACE_PROM (void *)(0x50F08001) - -struct mace_data { - volatile struct mace *mace; - unsigned char *tx_ring; - dma_addr_t tx_ring_phys; - unsigned char *rx_ring; - dma_addr_t rx_ring_phys; - int dma_intr; - int rx_slot, rx_tail; - int tx_slot, tx_sloti, tx_count; - int chipid; - struct device *device; -}; - -struct mace_frame { - u8 rcvcnt; - u8 pad1; - u8 rcvsts; - u8 pad2; - u8 rntpc; - u8 pad3; - u8 rcvcc; - u8 pad4; - u32 pad5; - u32 pad6; - u8 data[1]; - /* And frame continues.. */ -}; - -#define PRIV_BYTES sizeof(struct mace_data) - -static int mace_open(struct net_device *dev); -static int mace_close(struct net_device *dev); -static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev); -static void mace_set_multicast(struct net_device *dev); -static int mace_set_address(struct net_device *dev, void *addr); -static void mace_reset(struct net_device *dev); -static irqreturn_t mace_interrupt(int irq, void *dev_id); -static irqreturn_t mace_dma_intr(int irq, void *dev_id); -static void mace_tx_timeout(struct net_device *dev); -static void __mace_set_address(struct net_device *dev, void *addr); - -/* - * Load a receive DMA channel with a base address and ring length - */ - -static void mace_load_rxdma_base(struct net_device *dev, int set) -{ - struct mace_data *mp = netdev_priv(dev); - - psc_write_word(PSC_ENETRD_CMD + set, 0x0100); - psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); - psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); - psc_write_word(PSC_ENETRD_CMD + set, 0x9800); - mp->rx_tail = 0; -} - -/* - * Reset the receive DMA subsystem - */ - -static void mace_rxdma_reset(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mace = mp->mace; - u8 maccc = mace->maccc; - - mace->maccc = maccc & ~ENRCV; - - psc_write_word(PSC_ENETRD_CTL, 0x8800); - mace_load_rxdma_base(dev, 0x00); - psc_write_word(PSC_ENETRD_CTL, 0x0400); - - psc_write_word(PSC_ENETRD_CTL, 0x8800); - mace_load_rxdma_base(dev, 0x10); - psc_write_word(PSC_ENETRD_CTL, 0x0400); - - mace->maccc = maccc; - mp->rx_slot = 0; - - psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800); - psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800); -} - -/* - * Reset the transmit DMA subsystem - */ - -static void mace_txdma_reset(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mace = mp->mace; - u8 maccc; - - psc_write_word(PSC_ENETWR_CTL, 0x8800); - - maccc = mace->maccc; - mace->maccc = maccc & ~ENXMT; - - mp->tx_slot = mp->tx_sloti = 0; - mp->tx_count = N_TX_RING; - - psc_write_word(PSC_ENETWR_CTL, 0x0400); - mace->maccc = maccc; -} - -/* - * Disable DMA - */ - -static void mace_dma_off(struct net_device *dev) -{ - psc_write_word(PSC_ENETRD_CTL, 0x8800); - psc_write_word(PSC_ENETRD_CTL, 0x1000); - psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100); - psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100); - - psc_write_word(PSC_ENETWR_CTL, 0x8800); - psc_write_word(PSC_ENETWR_CTL, 0x1000); - psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100); - psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100); -} - -static const struct net_device_ops mace_netdev_ops = { - .ndo_open = mace_open, - .ndo_stop = mace_close, - .ndo_start_xmit = mace_xmit_start, - .ndo_tx_timeout = mace_tx_timeout, - .ndo_set_multicast_list = mace_set_multicast, - .ndo_set_mac_address = mace_set_address, - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, -}; - -/* - * Not really much of a probe. The hardware table tells us if this - * model of Macintrash has a MACE (AV macintoshes) - */ - -static int __devinit mace_probe(struct platform_device *pdev) -{ - int j; - struct mace_data *mp; - unsigned char *addr; - struct net_device *dev; - unsigned char checksum = 0; - static int found = 0; - int err; - - if (found || macintosh_config->ether_type != MAC_ETHER_MACE) - return -ENODEV; - - found = 1; /* prevent 'finding' one on every device probe */ - - dev = alloc_etherdev(PRIV_BYTES); - if (!dev) - return -ENOMEM; - - mp = netdev_priv(dev); - - mp->device = &pdev->dev; - SET_NETDEV_DEV(dev, &pdev->dev); - - dev->base_addr = (u32)MACE_BASE; - mp->mace = MACE_BASE; - - dev->irq = IRQ_MAC_MACE; - mp->dma_intr = IRQ_MAC_MACE_DMA; - - mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo; - - /* - * The PROM contains 8 bytes which total 0xFF when XOR'd - * together. Due to the usual peculiar apple brain damage - * the bytes are spaced out in a strange boundary and the - * bits are reversed. - */ - - addr = (void *)MACE_PROM; - - for (j = 0; j < 6; ++j) { - u8 v = bitrev8(addr[j<<4]); - checksum ^= v; - dev->dev_addr[j] = v; - } - for (; j < 8; ++j) { - checksum ^= bitrev8(addr[j<<4]); - } - - if (checksum != 0xFF) { - free_netdev(dev); - return -ENODEV; - } - - dev->netdev_ops = &mace_netdev_ops; - dev->watchdog_timeo = TX_TIMEOUT; - - printk(KERN_INFO "%s: 68K MACE, hardware address %pM\n", - dev->name, dev->dev_addr); - - err = register_netdev(dev); - if (!err) - return 0; - - free_netdev(dev); - return err; -} - -/* - * Reset the chip. - */ - -static void mace_reset(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - int i; - - /* soft-reset the chip */ - i = 200; - while (--i) { - mb->biucc = SWRST; - if (mb->biucc & SWRST) { - udelay(10); - continue; - } - break; - } - if (!i) { - printk(KERN_ERR "macmace: cannot reset chip!\n"); - return; - } - - mb->maccc = 0; /* turn off tx, rx */ - mb->imr = 0xFF; /* disable all intrs for now */ - i = mb->ir; - - mb->biucc = XMTSP_64; - mb->utr = RTRD; - mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU; - - mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */ - mb->rcvfc = 0; - - /* load up the hardware address */ - __mace_set_address(dev, dev->dev_addr); - - /* clear the multicast filter */ - if (mp->chipid == BROKEN_ADDRCHG_REV) - mb->iac = LOGADDR; - else { - mb->iac = ADDRCHG | LOGADDR; - while ((mb->iac & ADDRCHG) != 0) - ; - } - for (i = 0; i < 8; ++i) - mb->ladrf = 0; - - /* done changing address */ - if (mp->chipid != BROKEN_ADDRCHG_REV) - mb->iac = 0; - - mb->plscc = PORTSEL_AUI; -} - -/* - * Load the address on a mace controller. - */ - -static void __mace_set_address(struct net_device *dev, void *addr) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - unsigned char *p = addr; - int i; - - /* load up the hardware address */ - if (mp->chipid == BROKEN_ADDRCHG_REV) - mb->iac = PHYADDR; - else { - mb->iac = ADDRCHG | PHYADDR; - while ((mb->iac & ADDRCHG) != 0) - ; - } - for (i = 0; i < 6; ++i) - mb->padr = dev->dev_addr[i] = p[i]; - if (mp->chipid != BROKEN_ADDRCHG_REV) - mb->iac = 0; -} - -static int mace_set_address(struct net_device *dev, void *addr) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - unsigned long flags; - u8 maccc; - - local_irq_save(flags); - - maccc = mb->maccc; - - __mace_set_address(dev, addr); - - mb->maccc = maccc; - - local_irq_restore(flags); - - return 0; -} - -/* - * Open the Macintosh MACE. Most of this is playing with the DMA - * engine. The ethernet chip is quite friendly. - */ - -static int mace_open(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - - /* reset the chip */ - mace_reset(dev); - - if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) { - printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq); - return -EAGAIN; - } - if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) { - printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr); - free_irq(dev->irq, dev); - return -EAGAIN; - } - - /* Allocate the DMA ring buffers */ - - mp->tx_ring = dma_alloc_coherent(mp->device, - N_TX_RING * MACE_BUFF_SIZE, - &mp->tx_ring_phys, GFP_KERNEL); - if (mp->tx_ring == NULL) { - printk(KERN_ERR "%s: unable to allocate DMA tx buffers\n", dev->name); - goto out1; - } - - mp->rx_ring = dma_alloc_coherent(mp->device, - N_RX_RING * MACE_BUFF_SIZE, - &mp->rx_ring_phys, GFP_KERNEL); - if (mp->rx_ring == NULL) { - printk(KERN_ERR "%s: unable to allocate DMA rx buffers\n", dev->name); - goto out2; - } - - mace_dma_off(dev); - - /* Not sure what these do */ - - psc_write_word(PSC_ENETWR_CTL, 0x9000); - psc_write_word(PSC_ENETRD_CTL, 0x9000); - psc_write_word(PSC_ENETWR_CTL, 0x0400); - psc_write_word(PSC_ENETRD_CTL, 0x0400); - - mace_rxdma_reset(dev); - mace_txdma_reset(dev); - - /* turn it on! */ - mb->maccc = ENXMT | ENRCV; - /* enable all interrupts except receive interrupts */ - mb->imr = RCVINT; - return 0; - -out2: - dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, - mp->tx_ring, mp->tx_ring_phys); -out1: - free_irq(dev->irq, dev); - free_irq(mp->dma_intr, dev); - return -ENOMEM; -} - -/* - * Shut down the mace and its interrupt channel - */ - -static int mace_close(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - - mb->maccc = 0; /* disable rx and tx */ - mb->imr = 0xFF; /* disable all irqs */ - mace_dma_off(dev); /* disable rx and tx dma */ - - return 0; -} - -/* - * Transmit a frame - */ - -static int mace_xmit_start(struct sk_buff *skb, struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - unsigned long flags; - - /* Stop the queue since there's only the one buffer */ - - local_irq_save(flags); - netif_stop_queue(dev); - if (!mp->tx_count) { - printk(KERN_ERR "macmace: tx queue running but no free buffers.\n"); - local_irq_restore(flags); - return NETDEV_TX_BUSY; - } - mp->tx_count--; - local_irq_restore(flags); - - dev->stats.tx_packets++; - dev->stats.tx_bytes += skb->len; - - /* We need to copy into our xmit buffer to take care of alignment and caching issues */ - skb_copy_from_linear_data(skb, mp->tx_ring, skb->len); - - /* load the Tx DMA and fire it off */ - - psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys); - psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len); - psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800); - - mp->tx_slot ^= 0x10; - - dev_kfree_skb(skb); - - return NETDEV_TX_OK; -} - -static void mace_set_multicast(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - int i; - u32 crc; - u8 maccc; - unsigned long flags; - - local_irq_save(flags); - maccc = mb->maccc; - mb->maccc &= ~PROM; - - if (dev->flags & IFF_PROMISC) { - mb->maccc |= PROM; - } else { - unsigned char multicast_filter[8]; - struct netdev_hw_addr *ha; - - if (dev->flags & IFF_ALLMULTI) { - for (i = 0; i < 8; i++) { - multicast_filter[i] = 0xFF; - } - } else { - for (i = 0; i < 8; i++) - multicast_filter[i] = 0; - netdev_for_each_mc_addr(ha, dev) { - crc = ether_crc_le(6, ha->addr); - /* bit number in multicast_filter */ - i = crc >> 26; - multicast_filter[i >> 3] |= 1 << (i & 7); - } - } - - if (mp->chipid == BROKEN_ADDRCHG_REV) - mb->iac = LOGADDR; - else { - mb->iac = ADDRCHG | LOGADDR; - while ((mb->iac & ADDRCHG) != 0) - ; - } - for (i = 0; i < 8; ++i) - mb->ladrf = multicast_filter[i]; - if (mp->chipid != BROKEN_ADDRCHG_REV) - mb->iac = 0; - } - - mb->maccc = maccc; - local_irq_restore(flags); -} - -static void mace_handle_misc_intrs(struct net_device *dev, int intr) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - static int mace_babbles, mace_jabbers; - - if (intr & MPCO) - dev->stats.rx_missed_errors += 256; - dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */ - if (intr & RNTPCO) - dev->stats.rx_length_errors += 256; - dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */ - if (intr & CERR) - ++dev->stats.tx_heartbeat_errors; - if (intr & BABBLE) - if (mace_babbles++ < 4) - printk(KERN_DEBUG "macmace: babbling transmitter\n"); - if (intr & JABBER) - if (mace_jabbers++ < 4) - printk(KERN_DEBUG "macmace: jabbering transceiver\n"); -} - -static irqreturn_t mace_interrupt(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - int intr, fs; - unsigned long flags; - - /* don't want the dma interrupt handler to fire */ - local_irq_save(flags); - - intr = mb->ir; /* read interrupt register */ - mace_handle_misc_intrs(dev, intr); - - if (intr & XMTINT) { - fs = mb->xmtfs; - if ((fs & XMTSV) == 0) { - printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs); - mace_reset(dev); - /* - * XXX mace likes to hang the machine after a xmtfs error. - * This is hard to reproduce, reseting *may* help - */ - } - /* dma should have finished */ - if (!mp->tx_count) { - printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs); - } - /* Update stats */ - if (fs & (UFLO|LCOL|LCAR|RTRY)) { - ++dev->stats.tx_errors; - if (fs & LCAR) - ++dev->stats.tx_carrier_errors; - else if (fs & (UFLO|LCOL|RTRY)) { - ++dev->stats.tx_aborted_errors; - if (mb->xmtfs & UFLO) { - printk(KERN_ERR "%s: DMA underrun.\n", dev->name); - dev->stats.tx_fifo_errors++; - mace_txdma_reset(dev); - } - } - } - } - - if (mp->tx_count) - netif_wake_queue(dev); - - local_irq_restore(flags); - - return IRQ_HANDLED; -} - -static void mace_tx_timeout(struct net_device *dev) -{ - struct mace_data *mp = netdev_priv(dev); - volatile struct mace *mb = mp->mace; - unsigned long flags; - - local_irq_save(flags); - - /* turn off both tx and rx and reset the chip */ - mb->maccc = 0; - printk(KERN_ERR "macmace: transmit timeout - resetting\n"); - mace_txdma_reset(dev); - mace_reset(dev); - - /* restart rx dma */ - mace_rxdma_reset(dev); - - mp->tx_count = N_TX_RING; - netif_wake_queue(dev); - - /* turn it on! */ - mb->maccc = ENXMT | ENRCV; - /* enable all interrupts except receive interrupts */ - mb->imr = RCVINT; - - local_irq_restore(flags); -} - -/* - * Handle a newly arrived frame - */ - -static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf) -{ - struct sk_buff *skb; - unsigned int frame_status = mf->rcvsts; - - if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) { - dev->stats.rx_errors++; - if (frame_status & RS_OFLO) { - printk(KERN_DEBUG "%s: fifo overflow.\n", dev->name); - dev->stats.rx_fifo_errors++; - } - if (frame_status & RS_CLSN) - dev->stats.collisions++; - if (frame_status & RS_FRAMERR) - dev->stats.rx_frame_errors++; - if (frame_status & RS_FCSERR) - dev->stats.rx_crc_errors++; - } else { - unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 ); - - skb = dev_alloc_skb(frame_length + 2); - if (!skb) { - dev->stats.rx_dropped++; - return; - } - skb_reserve(skb, 2); - memcpy(skb_put(skb, frame_length), mf->data, frame_length); - - skb->protocol = eth_type_trans(skb, dev); - netif_rx(skb); - dev->stats.rx_packets++; - dev->stats.rx_bytes += frame_length; - } -} - -/* - * The PSC has passed us a DMA interrupt event. - */ - -static irqreturn_t mace_dma_intr(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *) dev_id; - struct mace_data *mp = netdev_priv(dev); - int left, head; - u16 status; - u32 baka; - - /* Not sure what this does */ - - while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY)); - if (!(baka & 0x60000000)) return IRQ_NONE; - - /* - * Process the read queue - */ - - status = psc_read_word(PSC_ENETRD_CTL); - - if (status & 0x2000) { - mace_rxdma_reset(dev); - } else if (status & 0x0100) { - psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100); - - left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot); - head = N_RX_RING - left; - - /* Loop through the ring buffer and process new packages */ - - while (mp->rx_tail < head) { - mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring - + (mp->rx_tail * MACE_BUFF_SIZE))); - mp->rx_tail++; - } - - /* If we're out of buffers in this ring then switch to */ - /* the other set, otherwise just reactivate this one. */ - - if (!left) { - mace_load_rxdma_base(dev, mp->rx_slot); - mp->rx_slot ^= 0x10; - } else { - psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800); - } - } - - /* - * Process the write queue - */ - - status = psc_read_word(PSC_ENETWR_CTL); - - if (status & 0x2000) { - mace_txdma_reset(dev); - } else if (status & 0x0100) { - psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100); - mp->tx_sloti ^= 0x10; - mp->tx_count++; - } - return IRQ_HANDLED; -} - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Macintosh MACE ethernet driver"); -MODULE_ALIAS("platform:macmace"); - -static int __devexit mac_mace_device_remove (struct platform_device *pdev) -{ - struct net_device *dev = platform_get_drvdata(pdev); - struct mace_data *mp = netdev_priv(dev); - - unregister_netdev(dev); - - free_irq(dev->irq, dev); - free_irq(IRQ_MAC_MACE_DMA, dev); - - dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE, - mp->rx_ring, mp->rx_ring_phys); - dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE, - mp->tx_ring, mp->tx_ring_phys); - - free_netdev(dev); - - return 0; -} - -static struct platform_driver mac_mace_driver = { - .probe = mace_probe, - .remove = __devexit_p(mac_mace_device_remove), - .driver = { - .name = mac_mace_string, - .owner = THIS_MODULE, - }, -}; - -static int __init mac_mace_init_module(void) -{ - if (!MACH_IS_MAC) - return -ENODEV; - - return platform_driver_register(&mac_mace_driver); -} - -static void __exit mac_mace_cleanup_module(void) -{ - platform_driver_unregister(&mac_mace_driver); -} - -module_init(mac_mace_init_module); -module_exit(mac_mace_cleanup_module); -- cgit v1.2.3