diff options
Diffstat (limited to 'drivers/net/ethernet/intel/e1000/e1000_oem_phy.h')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000/e1000_oem_phy.h | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000/e1000_oem_phy.h b/drivers/net/ethernet/intel/e1000/e1000_oem_phy.h new file mode 100644 index 00000000000..4c9bc15c61c --- /dev/null +++ b/drivers/net/ethernet/intel/e1000/e1000_oem_phy.h @@ -0,0 +1,225 @@ +/******************************************************************************* + +GPL LICENSE SUMMARY + + Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. + + This program is free software; you can redistribute it and/or modify + it under the terms of version 2 of the GNU General Public License as + published by the Free Software Foundation. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + The full GNU General Public License is included in this distribution + in the file called LICENSE.GPL. + + Contact Information: + Intel Corporation + + version: Embedded.Release.Patch.L.1.0.7-5 + + Contact Information: + + Intel Corporation, 5000 W Chandler Blvd, Chandler, AZ 85226 + +*******************************************************************************/ +#ifndef _E1000_OEM_PHY_H_ +#define _E1000_OEM_PHY_H_ + +#include <linux/types.h> + +#define E1000_CTRL_AUX 0x000E0 /* Aux Control -RW */ +#define E1000_82542_CTRL_AUX E1000_CTRL_AUX + +/* Bit definitions for valid PHY IDs. */ +/* I = Integrated + * E = External + */ +#define M88E1000_E_PHY_ID 0x01410C50 +#define M88E1000_I_PHY_ID 0x01410C30 +#define M88E1011_I_PHY_ID 0x01410C20 +#define IGP01E1000_I_PHY_ID 0x02A80380 +#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID +#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID +#define M88E1011_I_REV_4 0x04 +#define M88E1141_E_PHY_ID 0x01410CD0 +#define L1LXT971A_PHY_ID 0x001378E0 +#define VSC8211_E_PHY_ID 0x000FC4B1 +#define VSC8601_E_PHY_ID 0x00070420 + +/* RGMII TX and RX Timing Control*/ +#define M88E1000_EPSCR_TX_TIME_CTRL 0x0002 /* Add Delay */ +#define M88E1000_EPSCR_RX_TIME_CTRL 0x0080 /* Add Delay */ + +/* M88E1000 Specific Registers */ +#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ +#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ +#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ +#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ +#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ +#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ + +#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ +#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ +#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ +#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ +#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ + +#define IGP01E1000_IEEE_REGS_PAGE 0x0000 +#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 +#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 + +/* IGP01E1000 Specific Registers */ +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ +#define IGP02E1000_PHY_POWER_MGMT 0x19 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ + +/* VSC8211 Specific Registers */ +#define VSC8211_BYPASS_CTRL 0x12 +#define VSC8211_PHY_CTRL_1 0x17 +#define VSC8211_AUX_CTRL_STS 0x1C +#define VSC8211_EXT_PAGE_ACCESS 0x1F + +/* VSC8601 Specific Registers */ +#define VSC8601_BYPASS_CTRL 0x12 +#define VSC8601_PHY_CTRL_1 0x17 +#define VSC8601_AUX_CTRL_STS 0x1C + +/* VSC8211 BYPASS Control Register */ +#define VSC8211_BYPASS_POLAR_INVERS_DISABLE 0x0010 +#define VSC8211_BYPASS_AUTO_MDI_DISABLE 0x0020 + +/* VSC8211 Auxiliary Control & Status Register */ +#define VSC8211_AUX_SPEED_MASK 0x0018 +#define VSC8211_AUX_SPEED_IS_1000 0x0010 +#define VSC8211_AUX_SPEED_IS_100 0x0008 +#define VSC8211_AUX_SPEED_IS_10 0x0000 + +#define VSC8211_AUX_FDX_MASK 0x0020 +#define VSC8211_AUX_FDX_IS_FULL 0x0020 +#define VSC8211_AUX_FDX_IS_HALF 0x0000 + +/* VSC8211 PHY Control Register #1 */ +#define VSC8211_PHY_CTRL1_INTF_MODE1_RGMII 0x1000 +#define VSC8211_PHY_CTRL1_INTF_MODE1_GMII 0x3000 + +#define VSC8211_PHY_CTRL1_TXC_SKEW_2NS 0x0800 +#define VSC8211_PHY_CTRL1_RXC_SKEW_2NS 0x0200 + +#define VSC8211_PHY_CTRL1_RX_IDLE_CLK_ENABLE 0x0020 +#define VSC8211_PHY_CTRL1_RX_IDLE_CLK_DISABLE 0x0000 + +#define VSC8211_PHY_CTRL1_INTF_MODE2_CAT5 0x0004 +#define VSC8211_PHY_CTRL1_INTF_MODE2_FIBER 0x0002 + +/* VSC8601 BYPASS Control Register */ +#define VSC8601_BYPASS_POLAR_INVERS_DISABLE 0x0010 +#define VSC8601_BYPASS_AUTO_MDI_DISABLE 0x0020 + +/* VSC8601 Auxiliary Control & Status Register */ +#define VSC8601_AUX_SPEED_MASK 0x0018 +#define VSC8601_AUX_SPEED_IS_1000 0x0010 +#define VSC8601_AUX_SPEED_IS_100 0x0008 +#define VSC8601_AUX_SPEED_IS_10 0x0000 + +#define VSC8601_AUX_FDX_MASK 0x0020 +#define VSC8601_AUX_FDX_IS_FULL 0x0020 +#define VSC8601_AUX_FDX_IS_HALF 0x0000 + +/* + * ICP GbE devices are not assigned Intel part numbers yet so just + * identify them via their device id's + */ +#define E1000_DEV_ID_ICP_5040 0x5040 +#define E1000_DEV_ID_ICP_5041 0x5041 +#define E1000_DEV_ID_ICP_5042 0x5042 +#define E1000_DEV_ID_ICP_5043 0x5043 +#define E1000_DEV_ID_ICP_5044 0x5044 +#define E1000_DEV_ID_ICP_5045 0x5045 +#define E1000_DEV_ID_ICP_5046 0x5046 +#define E1000_DEV_ID_ICP_5047 0x5047 +#define E1000_DEV_ID_ICP_5048 0x5048 +#define E1000_DEV_ID_ICP_5049 0x5049 +#define E1000_DEV_ID_ICP_504A 0x504A +#define E1000_DEV_ID_ICP_504B 0x504B + +struct e1000_hw; +struct e1000_adapter; +struct ifreq; +struct e1000_phy_info; + +int32_t e1000_oem_setup_link(struct e1000_hw *hw); +int32_t e1000_oem_set_trans_gasket(struct e1000_hw *hw); + +uint32_t e1000_oem_get_tipg(struct e1000_hw *hw); +int e1000_oem_phy_is_copper(struct e1000_hw *hw); +uint32_t e1000_oem_get_phy_dev_number(struct e1000_hw *hw); +int e1000_oem_mii_ioctl(struct e1000_adapter *adapter, unsigned long flags, + struct ifreq *ifr, int cmd); +void e1000_oem_get_phy_regs(struct e1000_adapter *adapter, uint32_t *data, + uint32_t data_length); +int e1000_oem_phy_loopback(struct e1000_adapter *adapter); +void e1000_oem_loopback_cleanup(struct e1000_adapter *adapter); +uint32_t e1000_oem_phy_speed_downgraded(struct e1000_hw *hw, + uint16_t *isDowngraded); +int32_t e1000_oem_check_polarity(struct e1000_hw *hw, uint16_t *polarity); + +int32_t e1000_oem_phy_is_full_duplex(struct e1000_hw *hw, int *isFD); +int32_t e1000_oem_phy_is_speed_1000(struct e1000_hw *hw, int *is1000); +int32_t e1000_oem_phy_is_speed_100(struct e1000_hw *hw, int *is100); + +int32_t e1000_oem_force_mdi(struct e1000_hw *hw, int *resetPhy); +int32_t e1000_oem_phy_reset_dsp(struct e1000_hw *hw); +int32_t e1000_oem_cleanup_after_phy_reset(struct e1000_hw *hw); + +int32_t e1000_oem_phy_get_info(struct e1000_hw *hw, + struct e1000_phy_info *phy_info); + +int32_t e1000_oem_phy_hw_reset(struct e1000_hw *hw); +void e1000_oem_phy_init_script(struct e1000_hw *hw); + +int32_t e1000_oem_read_phy_reg_ex(struct e1000_hw *hw, + uint32_t reg_addr, uint16_t *phy_data); +int32_t e1000_oem_write_phy_reg_ex(struct e1000_hw *hw, + uint32_t reg_addr, uint16_t phy_data); + +int e1000_oem_phy_needs_reset_with_mac(struct e1000_hw *hw); + +int32_t e1000_oem_config_dsp_after_link_change(struct e1000_hw *hw, + int link_up); + +int32_t e1000_oem_get_cable_length(struct e1000_hw *hw, + uint16_t *min_length, + uint16_t *max_length); + +int32_t e1000_oem_phy_is_link_up(struct e1000_hw *hw, int *isUp); + +/* Default Register Macros */ + +#define ICP_XXXX_MAC_0 0 /* PCI Device numbers associated with MACs on */ +#define ICP_XXXX_MAC_1 1 /* ICP_XXXX family of controllers */ +#define ICP_XXXX_MAC_2 2 + +#define DEFAULT_ICP_XXXX_TIPG_IPGT 8 /* Inter Packet Gap Transmit Time */ +#define ICP_XXXX_TIPG_IPGT_MASK 0x000003FFUL + +/* Miscellaneous defines */ +#ifdef IEGBE_10_100_ONLY + #define ICP_XXXX_AUTONEG_ADV_DEFAULT 0x0F +#else + #define ICP_XXXX_AUTONEG_ADV_DEFAULT 0x2F +#endif + +#endif /* ifndef _IEGBE_OEM_PHY_H_ */ + |