diff options
Diffstat (limited to 'drivers/net/ethernet/intel/e1000/e1000_hw.h')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000/e1000_hw.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.h b/drivers/net/ethernet/intel/e1000/e1000_hw.h index 11578c8978d..c275be83c6d 100644 --- a/drivers/net/ethernet/intel/e1000/e1000_hw.h +++ b/drivers/net/ethernet/intel/e1000/e1000_hw.h @@ -51,6 +51,7 @@ typedef enum { e1000_82540, e1000_82545, e1000_82545_rev_3, + e1000_icp_xxxx, e1000_82546, e1000_ce4100, e1000_82546_rev_3, @@ -75,6 +76,7 @@ typedef enum { e1000_media_type_copper = 0, e1000_media_type_fiber = 1, e1000_media_type_internal_serdes = 2, + e1000_media_type_oem = 3, e1000_num_media_types } e1000_media_type; @@ -104,6 +106,8 @@ typedef enum { e1000_bus_type_unknown = 0, e1000_bus_type_pci, e1000_bus_type_pcix, + e1000_bus_type_pci_express, + e1000_bus_type_cpp, e1000_bus_type_reserved } e1000_bus_type; @@ -212,6 +216,7 @@ typedef enum { typedef enum { e1000_phy_m88 = 0, e1000_phy_igp, + e1000_phy_oem, e1000_phy_8211, e1000_phy_8201, e1000_phy_undefined = 0xFF @@ -403,11 +408,28 @@ int e1000_pcix_get_mmrbc(struct e1000_hw *hw); /* Port I/O is only supported on 82544 and newer */ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); + +int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up); +int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); +int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); +int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active); + #define E1000_READ_REG_IO(a, reg) \ e1000_read_reg_io((a), E1000_##reg) #define E1000_WRITE_REG_IO(a, reg, val) \ e1000_write_reg_io((a), E1000_##reg, val) +/* ICP xxxx Signal Target Capability */ +#define PCI_CAP_ID_ST 0x09 +#define PCI_ST_SCID_MASK 0x000000FF +#define PCI_ST_SCP_MASK 0x0000FF00 +#define PCI_ST_SBC_MASK 0x00FF0000 +#define PCI_ST_STYP_MASK 0xFF000000 +#define PCI_ST_SMIA_MASK 0x000000FF +#define PCI_ST_SMACC_MASK 0x0000FF00 +#define PCI_ST_SDATA_MASK 0xFFFF0000 +#define PCI_ST_SMIA_OFFSET 0x00000004 + /* PCI Device IDs */ #define E1000_DEV_ID_82542 0x1000 #define E1000_DEV_ID_82543GC_FIBER 0x1001 @@ -875,6 +897,8 @@ struct e1000_ffvt_entry { #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define E1000_IMC1 0x008D8 /* Interrupt Mask Clear 1 - RW */ +#define E1000_IMC2 0x008F8 /* Interrupt Mask 2 Clear - WO */ #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ @@ -1077,6 +1101,8 @@ struct e1000_ffvt_entry { #define E1000_82542_ICS E1000_ICS #define E1000_82542_IMS E1000_IMS #define E1000_82542_IMC E1000_IMC +#define E1000_82542_IMC1 E1000_IMC1 +#define E1000_82542_IMC2 E1000_IMC2 #define E1000_82542_RCTL E1000_RCTL #define E1000_82542_RDTR 0x00108 #define E1000_82542_RDFH E1000_RDFH @@ -1433,6 +1459,7 @@ struct e1000_hw { bool leave_av_bit_off; bool bad_tx_carr_stats_fd; bool has_smbus; + bool icp_xxxx_is_link_up; }; #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ @@ -2252,6 +2279,14 @@ struct e1000_host_command_info { #define EEPROM_FLASH_VERSION 0x0032 #define EEPROM_CHECKSUM_REG 0x003F +/* ICP PCI Dev ID xxxx macros to calculate word offsets for IA, IPv4 and IPv6 */ +#define EEPROM_CTRL3_APME_ICP_xxxx 0x0004 +#define EEPROM_MGMT_CONTROL_ICP_xxxx(dev_num) (((dev_num) + 1) << 4) +#define EEPROM_INIT_CONTROL3_ICP_xxxx(dev_num) ((((dev_num) + 1) << 4) + 1) +#define EEPROM_IA_START_ICP_xxxx(dev_num) ((((dev_num) + 1) << 4) + 2) +#define EEPROM_IPV4_START_ICP_xxxx(dev_num) ((((dev_num) + 1) << 4) + 5) +#define EEPROM_IPV6_START_ICP_xxxx(dev_num) ((((dev_num) + 1) << 4) + 7) + #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ |