/*
 *  XIOH power sequence
 *  Copyright (C) 2013  Avencall
 *
 *  hardware.h - platform definitions
 *  Author:
 *    Guillaume Knispel
 *
 *  This program is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HARDWARE_H
#define HARDWARE_H

enum port_gpio {
	P1, P2, P3, P4,	// not really used; might detect spurious defines
};

enum gpio_dir {		// fixed values
	DIR_IN = 0,
	DIR_OUT = 1,
};

enum gpio_ren {		// fixed values
	REN_NO = 0,
	REN_PULL = 1,
};

enum gpio_sel {		// fixed values
	SEL_GPIO = 0,
	SEL_PERIPH = 1,
};


/* macros for dir_ren_sel */
#define GPIO_IN_FLOAT	DIR_IN,  REN_NO,   SEL_GPIO
#define GPIO_IN_PULL	DIR_IN,  REN_PULL, SEL_GPIO
#define GPIO_OUT	DIR_OUT, REN_NO,   SEL_GPIO
#define PERIPH		DIR_IN,  REN_NO,   SEL_PERIPH

/*
for i in xrange(1, 5):
    for b in xrange(0, 8):
        print "#define P" + str(i) + "_" + str(b) + \
              "\t\tP" + str(i) + ", BIT" + str(b)
    print
*/

#define P1_0		P1, BIT0
#define P1_1		P1, BIT1
#define P1_2		P1, BIT2
#define P1_3		P1, BIT3
#define P1_4		P1, BIT4
#define P1_5		P1, BIT5
#define P1_6		P1, BIT6
#define P1_7		P1, BIT7

#define P2_0		P2, BIT0
#define P2_1		P2, BIT1
#define P2_2		P2, BIT2
#define P2_3		P2, BIT3
#define P2_4		P2, BIT4
#define P2_5		P2, BIT5
#define P2_6		P2, BIT6
#define P2_7		P2, BIT7

#define P3_0		P3, BIT0
#define P3_1		P3, BIT1
#define P3_2		P3, BIT2
#define P3_3		P3, BIT3
#define P3_4		P3, BIT4
#define P3_5		P3, BIT5
#define P3_6		P3, BIT6
#define P3_7		P3, BIT7

#define P4_0		P4, BIT0
#define P4_1		P4, BIT1
#define P4_2		P4, BIT2
#define P4_3		P4, BIT3
#define P4_4		P4, BIT4
#define P4_5		P4, BIT5
#define P4_6		P4, BIT6
#define P4_7		P4, BIT7

/**
 * GD(w, port, bit, dir, ren, sel, out) - Gpio Descriptor
 *
 * GD describes both on which pin the signal is and the initial
 * configuration to be given to it.
 *
 * w: Propagated from the parameter of the signal symbol
 *    At use time, this selects in which way the macro expands
 *
 * port: one of P1 to P4 - port in which the pin is
 * bit: one of BIT0 to BIT7 - pin in the port
 *
 * =WARNING= see MSP430 datasheets and errata for restrictions
 * on the following parameters
 *
 * dir: DIR_IN or DIR_OUT
 *      Initial value in register PxDIR
 *      Drive the output if DIR_OUT (only if ren=REN_NO)
 *
 * ren: REN_NO or REN_PULL
 *      Initial value in register PxREN
 *      Activate pull down / up if REN_PULL
 *
 * sel: SEL_GPIO or SEL_PERIPH
 *      Initial value in register PxSEL
 *
 * out: 0 or 1
 *      Initial value in register PxOUT
 *      If sel=SEL_GPIO:
 *          If ren=REN_PULL: Pull down or up
 *          Else If dir=DIR_OUT: Drive low or high
 */
#define GD(w, port, bit, dir, ren, sel, out) \
	GD__##w(port, bit, dir, ren, sel, out)

/**
 * GD_(w, port_bit, dir_ren_sel, out) - Like GD(), except shorter
 *
 * GD_ lets you use shortcuts to describe signals and pins more concisely.
 *
 * w: Propagated from the parameter of the signal symbol
 *    At use time, this selects in which way the macro expands
 *
 * port_bit: for ex. P1_5 means bit 5 on port 1
 *
 * dir_ren_sel: for ex. GPIO_IN_FLOAT or PERIPH
 *
 * out: 0 or 1, see description in GD()
 */
#define GD_(w, port_bit, dir_ren_sel, out) \
	GD(w, port_bit, dir_ren_sel, out)

#define GD__out(port, bit, dir, ren, sel, out)	(port##OUT), (bit)
#define GD__ren(port, bit, dir, ren, sel, out)	(port##REN), (bit)
#define GD__sel(port, bit, dir, ren, sel, out)	(port##SEL), (bit)
#define GD__dir(port, bit, dir, ren, sel, out)	(port##DIR), (bit)

#define GD__in(port, bit, dir, ren, sel, out)	(!!((port##IN) & (bit)))

#define GD__inreg(port, bit, dir, ren, sel, out) (port##IN)
#define GD__bit(port, bit, dir, ren, sel, out)	(bit)

#define SetBit(reg, bit)	((reg) |= (bit))
#define ClrBit(reg, bit)	((reg) &= (~(bit)))

#define Set(reg_bit)		SetBit(reg_bit)
#define Clr(reg_bit)		ClrBit(reg_bit)

#if defined(XIOH_V5)
# include "xioh_v5.h"
#elif defined(XIOH_V6)
# include "xioh_v6.h"
#endif

#endif //HARDWARE_H