From 92a55b1a757353d598f2d79665f48a596a7593c2 Mon Sep 17 00:00:00 2001 From: Guillaume Knispel Date: Thu, 26 Jul 2012 19:12:22 +0200 Subject: intermediate and still buggy version intermediate version modified by jmo: - modifications made at Asteel Flash - attempt to add handling of the reset button by forwarding the signal (modifications made at the office during a hands on debug session) --- hardware.h | 4 ++-- main.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++----------- 2 files changed, 64 insertions(+), 15 deletions(-) diff --git a/hardware.h b/hardware.h index 38f397b..dfd7bbe 100644 --- a/hardware.h +++ b/hardware.h @@ -97,9 +97,9 @@ PxIES_INIT //Interrupt Edge Select (0=pos 1=neg) // PORT2 #define P2OUT_INIT (CK410_PWR_GD_N | CPU_VCCP_EN_N | GREEN_LED_N \ - | RED_LED_N | IMCH_RSMRST_N) + | RED_LED_N | IMCH_RSMRST_N | SYS_RESET_N) #define P2DIR_INIT (CPU_VCCP_EN_N | GREEN_LED_N | RED_LED_N) -#define P2REN_INIT (CK410_PWR_GD_N | IMCH_RSMRST_N) +#define P2REN_INIT (CK410_PWR_GD_N | IMCH_RSMRST_N | SYS_RESET_N) #define P2SEL_INIT 0 #define P2IE_INIT 0 #define P2IES_INIT 0 diff --git a/main.c b/main.c index b3842d3..7310e0f 100644 --- a/main.c +++ b/main.c @@ -31,7 +31,9 @@ static void InitPorts(void); static void GlobalInit(void); +volatile u16 TAVector; volatile u16 Timer1; +volatile u16 Timer2; volatile u16 SW1State; volatile u16 SW2State; @@ -54,20 +56,25 @@ volatile u8 bVCC3 = true; #endif -#define STOP 10 -#define WAIT_START 20 -#define WAIT_ATX_OK 30 -#define WAIT_V1P0 40 -#define WAIT_V1P2 50 -#define WAIT_V1P8 60 -#define WAIT_RSMRST 70 -#define CK410_VTT_GD 80 -#define CPU_RUN 90 -#define WAIT_STOP 100 +#define STOP 10 +#define WAIT_START 20 +#define WAIT_ATX_OK 30 +#define WAIT_V1P0 40 +#define WAIT_V1P2 50 +#define WAIT_V1P8 60 +#define WAIT_RSMRST 70 +#define CK410_VTT_GD 80 +#define STATE_SYS_PWR_OK 90 +#define CPU_RUN 100 +#define WAIT_STOP 110 + +#define RST_STATE 10 +#define ON_STATE 20 +#define RST_WAIT 30 int main(void) { - u16 state; + u16 state, resetState; WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer to prevent time out reset @@ -79,7 +86,33 @@ int main(void) __enable_interrupt(); state = WAIT_START; + resetState = ON_STATE; while (1) { + + switch (resetState) { + case ON_STATE: + if (SW2State > 300) { + resetState = RST_STATE; + } + break; + + case RST_STATE: + SetBit(P2DIR, IMCH_RSMRST_N); + ClrBit(P2OUT, IMCH_RSMRST_N); + Timer2 = 100; + resetState = RST_WAIT; + break; + + case RST_WAIT: + if (Timer2 == 0) { + ClrBit(P2DIR, IMCH_RSMRST_N); + SetBit(P2OUT, IMCH_RSMRST_N); + if (SW2State == 0) + resetState = ON_STATE; + } + break; + } + switch (state) { case WAIT_START: if (SW1State > 30) @@ -97,6 +130,9 @@ int main(void) if (SW1State || TENSION_EXPIRED) state = STOP; if ((P4IN & ATX_PWROK) && TENSION_WAIT(bV2P5 && bVCC3)) { + SetBit(P2DIR, SYS_RESET_N); //modif jmo 25072012 + ClrBit(P2OUT, SYS_RESET_N); //modif jmo 25072012 + ClrBit(P1OUT, V1P2_CORE_EN_N); Timer1 = 30; state = WAIT_V1P2; @@ -148,8 +184,16 @@ int main(void) if (Timer1 == 0) { SetBit(P2DIR, CK410_PWR_GD_N); ClrBit(P2OUT, CK410_PWR_GD_N); - Timer1 = 300; - state = CPU_RUN; + Timer1 = 110; + state = STATE_SYS_PWR_OK; + } + break; + + case STATE_SYS_PWR_OK: + if (Timer1 == 0) { + SetBit(P3OUT, SYS_PWR_OK); + Timer1 = 10; + state = CPU_RUN; } break; @@ -215,6 +259,11 @@ __interrupt void Timer_A(void) if (Timer1) Timer1--; + + if (Timer2) + Timer2--; + + TAVector = TAIV; } static void InitPorts(void) -- cgit v1.2.3